Backlight unit and display device having the same

This application claims priority from and the benefit of Korean Patent Application No. 10-2012-0137169, filed on Nov. 29, 2012, which is hereby incorporated by reference for all purposes as if fully set forth herein.

1. Field

Exemplary embodiments of the present invention relate to a backlight unit and a display device having the backlight unit.

2. Discussion of the Background

As one of several kinds of user interfaces, a display device is required to be employed in electronic devices, and a flat-panel display device is widely used as the display is device for lightweight, slimness, and low power consumption of the electronic devices.

A liquid crystal display, which is generally referred to as the flat-panel display device, controls an amount of light provided thereto from an external source to display an image. That is, because certain liquid crystal displays are not self-emissive, they include a separate light source, i.e., a backlight unit including a backlight lamp.

In recent years, a light emitting diode (LED) has been widely used as the light source because it possesses several advantages, such as low power consumption, environment-friendly features, slim design, etc. However, the LED has a disadvantage regarding the optical design required to maintain uniformity of brightness and color of the display device, and a special technique is required to momentarily control electrical current flowing through the LED.

In addition, the backlight unit includes plural LED strings to secure sufficient brightness in the display device, but the LED strings have high power consumption.

Exemplary embodiments of the present invention provide a backlight unit having reduced power consumption.

Exemplary embodiments of the present invention also provide a display device having the backlight unit.

Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

An exemplary embodiment of the present invention discloses a backlight unit including a power converter configured to generate a light source driving voltage in response to a is voltage control signal, a plurality of light emitting diode strings each configured to receive the light source driving voltage through an end thereof, and a controller connected to the other end of each light emitting diode string and configured to generate a plurality of current control signals used to control a current flowing through each light emitting diode string and the voltage control signal. The controller is configured to generate the voltage control signal in response to a current control signal among the current control signals which is applied to a light emitting diode string configured to receive a lowest forward driving voltage among the light emitting diode strings.

An exemplary embodiment of the present invention also discloses a device including a display panel that includes a plurality of pixels, a driving circuit configured to control the display panel such that an image is displayed on the display panel, and a backlight unit configured to supply a light to the display panel. The backlight unit includes a power converter configured to generate a light source driving voltage in response to a voltage control signal, a plurality of light emitting diode strings each configured to receive the light source driving voltage through an end thereof, and a controller connected to the other end of each light emitting diode string and configured to generate a plurality of current control signals used to control a current flowing through each light emitting diode string and the voltage control signal. The controller is configured to generate the voltage control signal in response to a current control signal among the current control signals, which is applied to a light emitting diode string receiving a lowest forward driving voltage among the light emitting diode strings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

FIG. 1 is a circuit diagram showing a backlight unit according to an exemplary embodiment of the present invention.

FIG. 2 is a graph showing a current-voltage characteristic of an LED string shown in FIG. 1 .

FIG. 3 is a view showing a variation of power consumption according to the current-voltage characteristic of the LED string shown in FIG. 2 .

FIG. 4 is a circuit diagram showing the controller shown in FIG. 1 .

FIG. 5 is a waveform diagram showing signals generated by the voltage control signal generator shown in FIG. 4 .

FIG. 6 is a circuit diagram showing the current controller shown in FIG. 4 .

FIG. 7 is a waveform diagram showing signals generated by the current controller shown in FIG. 6 .

FIG. 8 is a circuit diagram showing the minimum error voltage generator shown in FIG. 4 .

FIG. 9 is a block diagram showing a display device including the backlight unit according to an exemplary embodiment of the present invention.

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.

It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

FIG. 1 is a circuit diagram showing a backlight unit according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a backlight unit 100 includes a light source 110 , a power converter 120 , a controller 130 , a plurality of resistors R 1 and R 2 , and a plurality of transistors T 1 and T 2 . Each of the plurality of resistors R 1 and R 2 is a pull-down resistor. The backlight unit 100 is used as a light source of a display panel of a liquid crystal display that requires the light source. In the present exemplary embodiment, the backlight unit 100 employed in the display panel will be described, but it should not be limited to the display panel. That is, the backlight unit 100 may be used in various fields, e.g., an illumination device, a commercial image board, etc.

The light source 110 includes a plurality of light emitting diode (LED) strings 111 and 112 . In the present exemplary embodiment, the light source 110 includes two LED strings 111 and 112 , but the light source 110 may include three or more LED strings.

Each of the LED strings 111 and 112 includes a plurality of LEDs connected to each other in series. Each LED includes a white LED emitting a white light, a red LED emitting a red light, a blue LED emitting a blue light, and a green LED emitting a green light. The white, red, blue, and green LEDs have different light emitting characteristics from each other, e.g., forward driving voltages (Vf) of the LEDs. To reduce power consumption, the LEDs may be driven by a low forward driving voltage (Vf). In addition, in order to secure uniformity of brightness, a deviation of the forward driving voltage (Vf) may be made small. In the present exemplary embodiment, the light source 110 includes the LED strings 111 and 112 each including the LEDs, but the LEDs may be replaced with laser diodes or carbon nano tubes.

An end of each of the LED strings 111 and 112 is connected to a light source driving voltage LVDD from the power converter 120 . The other end of each of the LED strings 111 and 112 is connected to a corresponding transistor of the transistors T 1 and T 2 . The transistor T 1 is connected between the other end of the LED string 111 and an end of the resistor R 1 and includes a gate terminal controlled by a current control signal PWM 1 . The transistor T 2 is connected between the other end of the LED string 112 and an end of the resistor R 2 and includes a gate terminal controlled by a current control signal PWM 2 . The other end of each of the resistors R 1 and R 2 is grounded.

The power converter 120 is configured to convert a source voltage EVDD from is an exterior to the light source driving voltage LVDD. The light source driving voltage LVDD has a voltage level high enough to drive the LEDs of the LED strings 111 and 112 .

The power converter 120 includes an inductor 121 , an NMOS transistor 122 , a diode 123 , and a capacitor 124 . The inductor 121 is connected between the source voltage EVDD and a node Q 1 . The NMOS transistor 122 is connected between the node Q 1 and ground. The NMOS transistor 122 includes a gate electrode configured to receive a voltage control signal CTRLV from the controller 130 . The diode 123 is connected between the node Q 1 and a node Q 2 . In the present exemplary embodiment, the diode 123 may be a Schottky diode. The capacitor 124 is connected between the node Q 2 and ground. The light source driving voltage LVDD at the node Q 2 is applied to the end of each of the LED strings 111 and 112 .

The power converter 120 having the above-mentioned configuration is configured to convert the source voltage EVDD to the light source driving voltage LVDD. In particular, the NMOS transistor 122 is turned on or off in response to the voltage control signal CTRLV applied to the gate electrode of the NMOS transistor 122 , and thus the voltage level of the light source driving voltage LVDD is controlled.

The controller 130 is configured to receive a current flowing through a node at which the transistor T 1 and the resistor R 1 are connected to each other as a feedback signal FB 1 and is configured to output the current control signal PWM 1 to the gate terminal of the transistor T 1 . The controller 130 is configured to receive a current flowing through a node at which the transistor T 2 and the resistor R 2 are connected to each other as a feedback signal FB 2 and is configured to output the current control signal PWM 2 to the gate terminal of the transistor T 2 .

The transistor T 1 is turned on or off in response to the current control signal PWM 1 . The current flowing through the LED string 111 is controlled by the turn on and off of is the transistor T 1 . The transistor T 2 is turned on or off in response to the current control signal PWM 2 . The current flowing through the LED string 112 is controlled by the turn on and off of the transistor T 2 .

The resistors R 1 and R 2 compensate for non-uniform voltage distribution between the LED strings 111 and 112 . That is, one of the resistors R 1 and R 2 , which has relatively low resistance, is connected to the LED string of the LED strings 111 and 112 that requires a relatively high forward driving voltage Vf, and the other one of the resistors R 1 and R 2 which has relatively high resistance, is connected to the other LED string of the LED strings 111 and 112 that requires a relatively low forward driving voltage Vf. Accordingly, a total power consumed in the LED strings 111 and 112 and the resistors R 1 and R 2 may be uniform.

The controller 130 is configured to output the voltage control signal CTRLV on the basis of the current control signals PWM 1 and PWM 2 generated by the feedback signals FB 1 and FB 2 , thereby controlling the voltage level of the light source driving voltage LVDD.

FIG. 2 is a graph showing a current-voltage characteristic of an LED string shown in FIG. 1 , and FIG. 3 is a view showing a variation of power consumption according to the current-voltage characteristic of the LED string shown in FIG. 2 .

Referring to FIGS. 1 and 2 , when the forward driving voltage Vf of the LED string 111 is about 100 volts, the current IL 1 flowing through the LED string 111 is about 100 mA, and when the forward driving voltage Vf of the LED string 111 is about 110 volts, the current IL 1 flowing through the LED string 111 is about 110 mA.

Referring to FIGS. 1 and 3 , although the forward driving voltage Vf of the LED string 111 differs from the forward driving voltage Vf of the LED string 112 , current flowing through the LED strings 111 and 112 should be controlled to allow the LED strings 111 and 112 is to have the same brightness. Thus, the current flowing through the LED strings 111 and 112 may be controlled by the turn on and off of the transistors T 1 and T 2 .

For instance, in a case that the current IL 1 of about 100 mA flows through the LED string 111 during a time period t 1 when the forward driving voltage Vf of the LED string 111 is about 100 volts, the current IL 1 of about 110 mA flows through the LED string 111 during a time period t 2 when the forward driving voltage Vf of the LED string 111 is about 110 volts. Thus, the brightness may be uniformly maintained. In this case, the time period t 1 is greater than the time period t 2 (t 1 >t 2 ). For instance, when t 1 is 1, t 2 may be obtained by multiplying t 1 by 0.909.

When the forward driving voltage Vf is about 100 volts, power consumption P 1 is represented by the following equation 1:

P 1=100 V×100 mA×1.0=10 W  Equation 1

When the forward driving voltage Vf is about 110 volts, power consumption P 2 is represented by the following equation 2:

P 2=110V×110 mA×0.909=10.99 W  Equation 2

That is, a pulse width of the current control signal PWM 1 applied to the gate electrode of the transistor T 1 is narrower when the forward driving voltage Vf is about 110 volts than that when the forward driving voltage Vf is about 100 volts (PW 1 >PW 2 ), and the power is consumption is greater when the forward driving voltage Vf is about 110 volts than that when the forward driving voltage Vf is about 100 volts (P 1 <P 2 ).

Therefore, when the light source driving voltage LVDD is applied to allow the pulse width of the current control signals PWM 1 and PWM 2 to be maximum, the power consumption of the backlight unit 100 may be reduced.

FIG. 4 is a circuit diagram showing the controller shown in FIG. 1 .

Referring to FIG. 4 , the controller 130 includes a voltage control signal generator 132 , a minimum error voltage generator 134 , and current controllers 136 and 138 . The voltage control signal generator 132 is configured to generate the voltage control signal CTRLV corresponding to the current control signal of the current control signals PWM 1 and PWM 2 that has the widest pulse width.

The minimum error voltage generator 134 is configured to receive the feedback signals FB 1 and FB 2 and to generate a minimum error voltage LEV corresponding to the feedback signal of the feedback signals FB 1 and FB 2 that has the lowest voltage level.

The current controller 136 is configured to receive a corresponding feedback signal FB 1 of the feedback signals FB 1 and FB 2 and to generate the current control signal PWM 1 . The current controller 138 is configured to receive a corresponding feedback signal FB 2 of the feedback signals FB 1 and FB 2 and to generate the current control signal PWM 2 .

The voltage control signal generator 132 includes diodes D 1 and D 2 , resistors R 11 to R 15 , a capacitor C 11 , transistors T 11 and T 12 , and a comparator 210 . Each of the plurality of resistors R 11 and R 15 is a pull-down resistor. An anode terminal of each of the diodes D 1 and D 2 is configured to receive a corresponding current control signal of the current control signals PWM 1 and PWM 2 output from the current controllers 136 and 138 . A cathode terminal of each of the diodes D 1 and D 2 is connected to a first node N 1 . The resistor R 11 is connected between a source voltage VCC and the first node N 1 . The resistor R 12 is connected between the first node N 1 and ground. The resistor R 13 is connected between the source voltage VCC and a second node N 2 . The transistor T 11 is connected between the second node N 2 and ground and includes a gate electrode connected to the first node N 1 . The resistor R 14 is connected between the minimum error voltage LEV and a third node N 3 . The transistor T 12 is connected between the third node N 3 and ground and includes a gate electrode connected to the second node N 2 . The resistor R 15 is connected between the third node N 3 and a fourth node N 4 . The capacitor C 11 is connected between the fourth node N 4 and ground. The comparator 210 is configured to receive a first reference voltage REF 1 and a voltage of the fourth node N 4 and to output the voltage control signal CTRLV.

FIG. 5 is a waveform diagram showing signals generated by the voltage control signal generator to explain the voltage control signal generator shown in FIG. 4 .

Referring to FIGS. 4 and 5 , when the pulse width pb of the current control signal PWM 2 output from the current controller 138 is greater than the pulse width pa of the current control signal PWM 1 output from the current controller 136 , the current control signal provided through the diode D 2 is applied to the first node N 1 .

During the high level of the voltage at the first node N 1 , the transistor T 11 is turned on. When the transistor T 11 is turned on, the voltage of the second node N 2 is transited to the low level. Therefore, the voltage at the second node N 2 is set to the high level during the low level of the voltage at the first node N 1 . During the high level of the voltage at the second node N 2 , the transistor T 12 is turned on and the voltage of the third node N 3 is transited to the low level. The transistor T 12 is turned off during the low level of the voltage at the second node N 2 and the voltage at the third node N 3 is transited to a voltage level corresponding to the minimum error voltage LEV. The voltage at the third node N 3 is integrated by the resistor R 15 and the capacitor C 11 and the integrated voltage is input into a non-inverting input terminal (+) of the comparator 210 through the fourth node N 4 .

The comparator 210 is configured to compare the voltage at the fourth node N 4 and a first reference voltage REF 1 and to output the voltage control signal CTRLV. The first reference voltage REF 1 is a triangular wave or a sawtooth wave.

According to the voltage control signal generator 132 , the voltage control signal CTRLV corresponding to a voltage obtained by reducing the voltage level of the mirror error voltage LEV by a period of the low level of the current control signal of the current control signals PWM 1 and PWM 2 , which has a relatively wide pulse width, is output. For instance, the explanation that the low level period exists in the current control signal having the relatively wide pulse width among the current control signals PWM 1 and PWM 2 means that the voltage level of the light source driving voltage LVDD is too high. Therefore, when the pulse width of the voltage control signal CTRLV is controlled by the voltage level corresponding to the low level period of the current control signal having the relatively wide pulse width among the current control signals PWM 1 and PWM 2 , the voltage level of the light source driving voltage LVDD may be set to a minimum level.

FIG. 6 is a circuit diagram showing the current controllers 136 shown in FIG. 4 . FIG. 6 shows only the configuration of the current controller 136 , but the current controller 138 may have the same configuration as the current controller 136 .

Referring to FIG. 6 , the current controller 136 includes a resistor R 21 , a capacitor C 21 , and comparators 310 and 320 . The resistor R 21 is connected between the resistor R 1 and a fifth node N 5 . The capacitor C 21 is connected between the fifth node N 5 and a sixth node N 6 . The comparator 310 is configured to receive a voltage of the fifth node N 5 and a second reference voltage REF 2 and to output a feedback voltage FV 1 to the sixth node N 6 . The comparator 320 is configured to receive the feedback voltage FV 1 of the sixth node N 6 and a third reference voltage REF 3 and to output the current control signal PWM 1 .

FIG. 7 is a waveform diagram showing signals generated by the current controller shown in FIG. 6 .

Referring to FIG. 7 , the feedback signal FB 1 at the end of the resistor R 1 becomes a direct current voltage FBV 1 by the interaction of the capacitor C 21 and the resistor R 21 . The comparator 310 is configured to compare the second reference voltage REF 2 , which is a direct current voltage, and the direct current voltage FBV 1 to output the feedback voltage FV 1 . The comparator 320 is configured to compare the feedback voltage FV 1 and the third reference voltage REF 3 to output the current control signal PWM 1 . The third reference voltage REF 3 is a triangular wave or a sawtooth wave.

As the pulse width pa of the current control signal PWM 1 increases, the turn-on period of the transistor T 1 lengthens. Therefore, the amount of the current flowing through the LED string 111 is increased. As the pulse width pa of the current control signal PWM 1 decreases, the turn-on period of the transistor T 1 shortens. Therefore, the amount of the current flowing through the LED string 111 is decreased. As described above, the current flowing through the LED string 111 is controlled by changing the pulse width pa of the current control signal PWM 1 , and thus the brightness of the LED string 111 may be controlled.

FIG. 8 is a circuit diagram showing the minimum error voltage generator 134 shown in FIG. 4 .

Referring to FIG. 8 , the minimum error voltage generator 134 includes diodes D 31 and D 32 , resistors R 31 and R 32 , a capacitor C 31 , and a comparator 410 . The diode D 31 includes a cathode terminal connected to the end of the resistor R 1 and the diode D 32 includes a cathode terminal connected to the end of the resistor R 2 . Anode terminals of the diodes D 31 and D 32 are both connected to a seventh node N 7 . The resistor R 31 is connected between a source voltage VCC and the seventh node N 7 . The resistor R 32 is connected between the seventh node N 7 and an eighth node N 8 . The comparator 410 is configured to receive a voltage at the eighth node N 8 and the second reference voltage REF 2 and to output the minimum error voltage LEV. The capacitor C 31 is connected between the eighth node N 8 and an output terminal of the comparator 410 .

A voltage at the seventh node N 7 has a voltage level corresponding to a relatively lower voltage level of the feedback signals FB 1 and FB 2 at the ends of the resistors R 1 and R 2 . For example, when the voltage level of the feedback signal FB 1 is lower than the voltage level of the feedback signal FB 2 , a current path is formed through the resistor R 31 and the diode D 31 . Therefore, the voltage level of the voltage at the seventh node N 7 is set to the voltage level of the feedback signal FB 1 .

The voltage of the eighth node N 8 corresponds to a voltage obtained by integrating the voltage of the seventh node N 7 by using the resistor R 32 and the capacitor C 31 . A difference between the second reference voltage REF 2 , which is a direct current voltage, and the voltage of the eighth node N 8 is output as the minimum error voltage LEV. Therefore, the minimum error voltage generator 134 may generate the minimum error voltage LEV corresponding to the feedback signal having the relatively lower voltage level of the feedback signals FB 1 and FB 2 . The minimum error voltage LEV is applied to the end of the resistor R 14 is shown in FIG. 4 .

FIG. 9 is a block diagram showing a display device including the backlight unit according to an exemplary embodiment of the present disclosure. Hereinafter, a liquid crystal display will be described as the display device, but the display device is not limited to the liquid crystal display.

Referring to FIG. 9 , a display device 500 includes a display panel 510 , a timing controller 520 , a gate driver 530 , a data driver 540 , and a backlight unit 550 .

The display panel 510 includes a plurality of data lines D 1 to Dm, a plurality of gate lines G 1 to Gn crossing the data lines D 1 to Dm, and a plurality of pixels PX arranged in areas defined by the data lines D 1 to Dm and the gate lines G 1 to Gn. The data lines D 1 to Dm are insulated from the gate lines G 1 to Gn.

Each pixel PX includes a switching transistor TR connected to a corresponding data line of the data lines D 1 to Dm and a corresponding gate line of the gate lines G 1 to Gn, a liquid crystal capacitor CLC connected to the switching transistor TR, and a storage capacitor CST connected to the switching transistor TR.

The timing controller 520 , the gate driver 530 , and the data driver 540 are configured to operate as a driving circuit to control the display panel 510 , and thus the image is displayed on the display panel 510 .

The timing controller 520 is configured to receive image signals RGB and control signals CTRL used to control the image signals RGB, such as a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, etc., from an external device (not shown). The timing controller 520 is configured to process the image signals RGB appropriate to an operation condition of the display panel 510 on the basis of the control signals CTRL to output an image data signal DATA. The timing controller 520 is configured to apply the image data signal DATA and a first control signal CTRL 1 to the data driver 540 and to apply a second control signal CTRL 2 to the gate driver 530 . The first control signal CTRL 1 includes a start pulse signal, a clock signal, a polarity inverting signal, and a line latch signal (not shown) and the second control signal CTRL 2 includes a vertical synchronization start signal, an output enable signal, and a gate pulse signal (not shown).

The gate driver 530 is configured to drive the gate lines G 1 to Gn in response to the second control signal CTRL 2 from the timing controller 520 . The gate driver 530 is configured as a gate driver integrated circuit or as a circuit using oxide semiconductor, amorphous semiconductor, crystalline semiconductor, or polycrystalline semiconductor.

The data driver 540 is configured to output gray-scale voltages in response to the image data signal DATA and the first control signal CTRL 1 from the timing controller 520 to drive the data lines D 1 to Dm.

When a gate on voltage is applied to one gate line by the gate driver 530 , switching transistors TR arranged in one row and connected to the one gate line are turned on. In this case, the data driver 540 is configured to provide the gray-scale voltages corresponding to the image data signal DATA to the data lines D 1 to Dm. The gray-scale voltages applied to the data lines D 1 to Dm are applied to corresponding liquid crystal capacitors CLC and corresponding storage capacitors CST through the turned-on switching transistors TR.

The backlight unit 550 is configured to provide the light to the display panel 510 . The display panel 510 is configured to display the image using the light from the backlight unit 550 .

The backlight unit 550 is configured to be operated in response to a backlight control signal BLC from the timing controller 520 . The backlight unit 550 is configured to control the brightness in response to the backlight control signal BLC from the timing controller 520 and to change on and off periods thereof in response to the backlight control signal BLC from the timing controller 520 .

The backlight unit 550 included in the display device 500 is configured to control the voltage level of the light source driving voltage applied to the LED strings with reference to the LED string having lowest forward driving voltage among the LED strings. Because the voltage level of the light source driving voltage may be set to the minimum level required to drive the LED strings, the power consumption in the backlight unit 550 may be reduced. Consequently, the power consumption of the display device 500 may be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.