Device for providing a differential output signal and method for providing a differential output signal

This application claims priority to U.S. application No. 61/613,102 filed on Mar. 20, 2012. German patent application number DE 10 2012 2044 51.5 filed on Mar. 20, 2012, German patent application number DE 10 2012 2044 50.7 filed on Mar. 20, 2012, and German patent application number DE 10 2012 2044 48.5 filed on Mar. 20, 2012.

Exemplary embodiments of the present disclosure provide a device for providing a differential output signal having a first output signal component and a second output signal component based on a plurality of input signals. Further exemplary embodiments provide a method for providing a differential output signal. Exemplary embodiments of the present disclosure can be used in digital-to-analogue converters, for example. Further exemplary embodiments provide a mobile radio device.

In digital radio-frequency transmission architectures, different digitally controlled signal paths can be combined at a common output load. A typical example of such a transmission architecture is a digital direct modulator. On account of the overlap of I-Q clock signals or digital noise shaping, it can happen that part of the signal current is generated in both sides of the differential load, which leads to an undesired common-mode signal or self-cancellation of the signal. Since this portion of the signal does not generate a desired RF signal, the current consumption of the modulator increases and, furthermore, the efficiency is reduced by the current required for generating this undesired portion.

Therefore, it is an object of exemplary embodiments of the present disclosure to provide a concept which enables a differential output signal to be provided more efficiently.

Exemplary embodiments of the present disclosure provide a device for providing a differential output signal having a first output signal component and a second output signal component based on a plurality of input signals. The device comprises a pair of signal sources comprising a first activatable signal source for providing the first output signal component and a second activatable signal source for providing the second output signal component. Furthermore, the device has a controller, which is operably coupled to the pair of signal sources and is configured to activate either the first signal source or the second signal source of the pair of signal sources depending on the plurality of input signals.

Further exemplary embodiments of the present disclosure provide a mobile radio device. Further exemplary embodiments of the present disclosure provide a method for providing a differential output signal.

Exemplary embodiments of the present disclosure are described in detail hereinafter with reference to the accompanying figures, in which:

FIG. 1A shows a block diagram of a device in accordance with one exemplary embodiment of the present disclosure;

FIG. 1B shows an example of a drive table such as can be used in exemplary embodiments of the present disclosure in a controller for driving signal sources;

FIG. 1C shows a block diagram of one possible implementation of a controller such as can be used in exemplary embodiments of the present disclosure;

FIG. 2 shows diagrams for illustrating the generation of a common-mode signal;

FIG. 3 shows a block diagram of a device in accordance with a further exemplary embodiment of the present disclosure;

FIG. 4 shows a block diagram of a mobile radio device in accordance with one exemplary embodiment of the present disclosure; and

FIG. 5 shows a flow chart of a method in accordance with a further exemplary embodiment of the present disclosure.

Before exemplary embodiments of the present disclosure are described in detail hereinafter, it is pointed out that identical elements or elements having an identical function are provided with the same reference signs in the figures, and that descriptions of elements having the same reference signs are mutually interchangeable. Therefore, a repeated description of elements provided with the same reference signs will be dispensed with.

FIG. 1A shows a block diagram of a device 100 for providing a differential output signal 101 in accordance with one exemplary embodiment of the present disclosure. The differential output signal 101 has a first output signal component 101 a and a second output signal component 101 b . By way of example, the differential output signal 101 can be obtained by subtracting the first output signal component 101 a from the second output signal component 101 b . The device 100 is designed to provide the differential output signal 101 based on a plurality of input signals 103 a - 1 - 103 b - 1 . The device 100 comprises a pair 105 of signal sources 107 a - 1 , 107 b - 1 . The pair 105 of signal sources 107 a - 1 , 107 b - 1 comprises a first activatable signal source 107 a - 1 for providing the first output signal component 101 a and a second activatable signal source 107 b - 1 for providing the second output signal component 101 b . Furthermore, the device 100 comprises a controller 109 - 1 . The controller 109 - 1 is operably coupled to the pair 105 of signal sources 107 a - 1 , 107 b - 1 and is configured to activate either the first signal source 107 a - 1 or the second signal source 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 depending on the plurality of input signals 103 a - 1 , 103 b - 1 . In other words, the controller 109 - 1 can be designed, depending on the plurality of input signals 103 a - 1 , 103 b - 1 , to activate the signal sources 107 a - 1 , 107 b - 1 in such a way that (apart from at changeover instants) at an instant either none of the two signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 is active or a maximum of one of the two signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 is active.

The output signal components 101 a , 101 b can be provided by the signal sources 107 a - 1 , 107 b - 1 at a common load 111 coupled to the signal sources 107 a - 1 , 107 b - 1 . For example, in one case the output signal components 101 a , 101 b may be superposed (in a signed manner) at the common load 111 . In this case, in accordance with some exemplary embodiments, the common load 111 can be part of the device 100 , but can also be external to the device 100 .

Device 100 allows for a common-mode suppression to be achieved at the common load 111 if the controller 109 - 1 is designed such that, independently of the input signals 103 a - 1 , 103 b - 1 , the output signal components 101 a , 101 b provided by the signal sources 107 a - 1 , 107 b - 1 cannot be cancelled at the common load 111 . In exemplary embodiments of the present disclosure this is achieved by virtue of the fact that the controller 109 - 1 is designed to activate either the first signal source 107 a - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 or the second signal source 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 depending on the input signals 103 a - 1 , 103 b - 1 . This avoids the situation where both signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 are simultaneously active, which would have the effect that both signal sources 107 a - 1 , 107 b - 1 provide an output signal component 101 a , 101 b , which would cancel one another in the resulting differential output signal 101 (at the common load 111 ) and, therefore, would not contribute to the information content of the differential output signal 101 . In other words, the controller 109 - 1 can be designed, in the cases in which the input signals 103 a - 1 , 103 b - 1 have a value which would have the effect that both signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 are activated, to activate neither of the two signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 . This does not lead here to a loss of information in the resulting differential output signal 101 , since the two output signal components 101 a , 101 b provided simultaneously by the signal sources 107 a - 1 , 107 b - 1 would have cancelled one another anyway in the resulting differential output signal 101 , but rather leads, in contrast to conventional systems, to a significant reduction of the current consumption of the device 100 .

In accordance with some exemplary embodiments, the common load 111 can comprise or form an inductive load, a resistive load, and/or a capacitive load. In this case, the first signal source 107 a - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 can be connected to a first terminal 113 a of said inductive, capacitive or resistive load and the second signal source 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 can be connected to a second terminal 113 b of said inductive, capacitive or resistive load. An inductive load can be, for example, a differential inductive load or a differential transformer or a resonator.

In accordance with some exemplary embodiments, the signal sources 107 a - 1 , 107 b - 1 can be voltage sources or current sources. A pair of signal sources, such as the pair 105 of signal sources 107 a - 1 , 107 b - 1 as shown in FIG. 1 , can be distinguished by the fact that a magnitude of a current or of a voltage which is provided by the first signal source 107 a - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 in its activated state is (within a tolerance range of ±1%, ±5%, ±10% or ±20% of the current provided by the first signal source 107 a - 1 or of the voltage provided by the first signal source 107 a - 1 ) equal to a current or equal to a voltage which is provided by the second signal source 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 in its activated state.

To summarize, a current provided by the first signal source 107 a - 1 or a voltage provided by the first signal source 107 a - 1 can be (in terms of magnitude) equal to a current provided by the second signal source 107 b - 1 or a voltage provided by the second signal source 107 b - 1 .

In some cases, a sign of the current provided by the first signal source 107 a - 1 or of the voltage provided by the first signal source 107 a - 1 can differ from a sign of the current provided by the second signal source 107 b - 1 or of the voltage provided by the second signal source 107 b - 1 .

In accordance with some exemplary embodiments, the controller 109 - 1 can be designed to receive a first input signal 103 a - 1 (also designated as In, 1+) for the first signal source 107 a - 1 and to receive a second input signal 103 b - 1 (also designated as In, 1−) for the second signal source 107 b - 1 . Furthermore, the controller 109 - 1 can be designed, in a case in which a value (e.g., a digital value) of the first input signal 103 a - 1 corresponds to a value (e.g., a digital value) of the second input signal 103 b - 1 (e.g., is equal to the latter), independently of the value of the first input signal 103 a - 1 or of the second input signal 103 b - 1 , to activate none of the signal sources 107 a - 1 , 107 b - 1 of the pair 105 of signal sources 107 a - 1 , 107 b - 1 . In other words, the controller 109 - 1 can be designed, in the case in which the two input signals 103 a - 1 , 103 b - 1 have values which, in conventional systems, would have the effect that both signal sources 107 a - 1 , 107 b - 1 are activated simultaneously, to dispense with simultaneous activation of the signal sources 107 a - 1 , 107 b - 1 , in such a way that no superposition of the output signal components 101 a , 101 b provided by the signal sources 107 a - 1 , 107 b - 1 can occur at the common load 111 .

Within the meaning of the present application, a ‘value’ of the first input signal 103 a - 1 corresponds to a ‘value’ of the second input signal 103 b - 1 if the value of the first input signal 103 a - 1 forms a request for activating the first signal source 107 a - 1 and the value of the second input signal 103 b - 1 forms a request for activating the second signal source 107 b - 1 , or if the value of the first input signal 103 a - 1 forms a request for deactivating the first signal source 107 a - 1 and the value of the second input signal 103 b - 1 forms a request for deactivating the second signal source 107 b - 1 . In other words, the two mutually corresponding values of the input signals 103 a - 1 , 103 b - 1 can also differ from one another as long as the purpose that they are intended to have (namely an activation or a deactivation of the respective signal source 107 a - 1 , 107 b ) is identical.

In accordance with further exemplary embodiments, the controller 109 - 1 can be designed (on the basis both of the first input signal 103 a - 1 for the first signal source 107 a - 1 and of the second input signal 103 b - 1 for the second signal source 107 b - 1 ) to provide a first drive signal 115 a - 1 (also designated as Out, 1+) for the first signal source 107 a - 1 and (on the basis both of the first input signal 103 a - 1 for the first signal source 107 a - 1 and of the second input signal 103 b - 1 for the second signal source 107 b - 1 ) to provide a second drive signal 115 b - 1 (also designated as Out, 1−) for the second signal source 107 b - 1 . In this case, the first drive signal 115 a - 1 can serve to activate and deactivate the first signal source 107 a - 1 and the second drive signal 115 b - 1 can serve to activate and deactivate the second signal source 107 b - 1 .

In accordance with some exemplary embodiments, the first signal source 107 a - 1 can be designed to switch to its active state or to remain therein in reaction to a first value (for example a first digital value) of the first drive signal 115 a - 1 and to switch to its deactivated state or to remain therein in reaction to a second value (for example a value complementary to the first value) of the first drive signal 115 a - 1 . Furthermore, the second signal source 107 b - 1 can be designed to switch to its active state or to remain therein in reaction to a first value (for example a first digital value) of the second drive signal 115 b - 1 and to switch to its deactivated state or to remain therein in reaction to a second value (which is for example complementary to the first value) of the second drive signal 115 b - 1 .

In the present application, it is assumed for the sake of simplicity that the drivings for the first signal source 107 a - 1 and the second signal source 107 b - 1 are identical (i.e. that the same digital values of the input signals 103 a - 1 , 103 b - 1 and of the drive signals 115 a - 1 , 115 b - 1 of the two signal sources 107 a - 1 , 107 b - 1 lead to an activation or a deactivation of the signal sources 107 a - 1 , 107 b - 1 ). In accordance with further exemplary embodiments, however, the driving for the first signal source 107 a - 1 and the second signal source 107 b - 1 can also be different.

In accordance with some exemplary embodiments, the input signals 103 a - 1 , 103 b - 1 and/or the drive signals 115 a - 1 , 115 b - 1 can be digital signals. By way of example, the controller 109 - 1 can be designed to obtain the drive signals 115 a - 1 , 115 b - 1 for the pair 105 of signal sources 107 a - 1 , 107 b - 1 based on a logical (for example Boolean) combination of the input signals 103 a - 1 , 103 b - 1 . A digital signal can assume for example two possibly permissible values (logic 0 and logic 1).

Thus, in accordance with further exemplary embodiments, the controller 109 - 1 can be designed, in a case in which a value of the first input signal 103 a - 1 does not correspond to a value of the second input signal 103 b - 1 (e.g., such that one of the two signal sources 107 a - 1 , 107 b - 1 is intended to be activated) or in a case in which a value of the first input signal 103 a - 1 is not equal to a value of the second input signal 103 b - 1 (e.g., such that one of the two signal sources 107 a - 1 , 107 b - 1 is intended to be activated), to provide the first input signal 103 a - 1 as drive signal 115 a - 1 for the first signal source 107 a - 1 and to provide the second input signal 103 b - 1 as second drive signal for the second signal source 107 b - 1 . In other words, the controller 109 - 1 can be designed to switch the input signals 103 a - 1 , 103 b - 1 through to the signal sources 107 a - 1 , 107 b - 1 as the drive signals 115 a - 1 , 115 b - 1 , in cases in which, on account of the applied input signals 103 a - 1 , 103 b - 1 , only one of the two signal sources 107 a - 1 , 107 b - 1 is intended to be activated,

As already explained, the controller 109 - 1 can be designed to receive the input signals 103 a - 1 , 103 b - 1 as digital input signals 103 a - 1 , 103 b - 1 and, based on a logical combination of the received digital input signals 103 a - 1 , 103 b - 1 , to provide the first drive signal 115 a - 1 as a first digital drive signal for activating and deactivating the first signal source 107 a - 1 and to provide the second drive signal 115 b - 1 as a second digital drive signal for activating and deactivating the second signal source 107 b - 1 .

In this respect, FIG. 1B shows a truth table as to how the logical combination of the input signals 103 a - 1 , 103 b - 1 can be carried out by the controller 109 - 1 . It becomes apparent from FIG. 1B that, in the cases in which the input signals 103 a - 1 , 103 b - 1 have a same value (for example digital 0 or digital 1), the controller 109 - 1 provides the drive signals 115 a - 1 , 115 b - 1 in such a way that the signal sources 107 a - 1 , 107 b - 1 switch to their deactivated state or remain therein (it being assumed that, in the case of the digital value 0 of the associated drive signal 115 a - 1 , 115 b - 1 , the respective signal source 107 a - 1 , 107 b - 1 switches to its deactivated state or remains therein). Furthermore, it becomes apparent that, in the cases in which the input signals 103 a - 1 , 103 b - 1 have different values (for example complementary digital values), the values of the drive signals 115 a - 1 , 115 b - 1 are equal to the values of the associated input signals 103 a - 1 , 103 b - 1 .

Thus, the controller 109 - 1 is designed to provide the drive signals 115 a - 1 , 115 b - 1 such that, in the case in which the first input signal 103 a - 1 has the digital value 0 and the second input signal 103 b - 1 has the digital value 1, the first drive signal 115 a - 1 has a digital value which leads to the deactivation of the first signal source 107 a - 1 (digital value 0 in the example) and the second drive signal 115 b - 1 has a digital value which leads to the activation of the second signal source 107 b - 1 (digital value 1 in the example). Furthermore, the controller 109 - 1 is designed to provide the drive signals 115 a - 1 , 115 b - 1 such that, in the case in which the first input signal 103 a - 1 has the digital value 1 and the second input signal 103 b - 1 has the digital value 0, the first drive signal 115 a - 1 has a digital value which leads to the activation of the first signal source 107 a - 1 (digital value 1 in the example) and the second drive signal 115 b - 1 has a digital value which leads to the deactivation of the second signal source 107 b - 1 (digital value 0 in the example).

It will be appreciated that complementary realizations with respect to the realization shown in FIG. 1B are also possible in accordance with further exemplary embodiments. In such embodiments the complementary realizations ensure that in the case in which the input signals 103 a - 1 , 103 b - 1 have values which would have the effect that both signal sources 107 a - 1 , 107 b - 1 are activated simultaneously, instead of simultaneous activation of the two signal sources 107 a - 1 , 107 b - 1 , neither of the two signal sources 107 a - 1 , 107 b - 1 is activated, in order to avoid common-mode signals which do not contribute to the information content of the resulting differential output signal 101 .

To summarize, in the case of the controller 109 - 1 , the logical combination of the input signals 103 a - 1 , 103 b - 1 can be chosen in such a way that, for the cases in which a value of the first input signal 103 a - 1 corresponds to a value of the second input signal 103 b - 1 (for example is equal to the latter), the resulting drive signals 115 a - 1 , 115 b - 1 for the first signal source 107 a - 1 and the second signal source 107 b - 1 in each case have a value (for example digital value 0) for which the associated signal source 107 a - 1 , 107 b - 1 switches to its deactivated state or remains therein.

As described above, in some embodiments the logical combination of the input signals 103 a - 1 , 103 b - 1 can be chosen in such a way that, for the cases in which a value of the first input signal 103 a - 1 does not correspond to a value of the second input signal 103 b - 1 (for example if these values are complementary to one another), a value of the first drive signal 115 a - 1 is based on the value of the first input signal 103 a - 1 (for example corresponds to the latter) and a value of the second drive signal 115 b - 1 is based on the value of the second input signal 103 b - 1 (for example corresponds to the latter).

FIG. 1C shows a block diagram of one possible implementation of the controller 109 - 1 for the case of the use of digital input signals 103 a - 1 , 103 b - 1 and digital drive signals 115 a - 1 , 115 b - 1 . As is evident from FIG. 1C , the controller 109 - 1 can be designed to obtain the first drive signal 115 a - 1 based on a first NOR combination 121 a of a negated version 123 a of the first input signal 103 a - 1 and of a non-negated version of the second input signal 103 b - 1 . Furthermore, the controller 109 - 1 can be designed to obtain the second drive signal 115 b - 1 based on a second NOR combination 121 b of a negated version 123 b of the second input signal 103 b - 1 and of a non-negated version of the first input signal 103 a - 1 . The logical combination shown in FIG. 1C forms one possible implementation of the truth table shown in FIG. 1B , wherein, as already described, it is assumed that the implementation of the two signal sources 107 a - 1 , 107 b - 1 is chosen to be identical with regard to their driving, that is to say that the same digital values of the drive signals 115 a - 1 , 115 b - 1 lead to an activation or a deactivation of the respective signal source 107 a - 1 , 107 b - 1 .

In accordance with further exemplary embodiments, other logical combinations are, of course, also possible, which make it possible that, for the case in which the input signals 103 a - 1 , 103 b - 1 predefine an activation of both signal sources 107 a - 1 , 107 b - 1 , neither of the two signal sources 107 a - 1 , 107 b - 1 is activated. In this case the logical combination can furthermore be designed such that, in the cases in which the input signals 103 a - 1 , 103 b - 1 assume values for which one of the two signal sources 107 a - 1 , 107 b - 1 is intended to be activated, this respective signal source 107 a - 1 , 107 b - 1 is also activated.

Another possibility for implementing the controller 109 - 1 is a 2-bit multiplexer (e.g., between all positive and negative bits). The 2-bit multiplexer may generate a digital value 0 for the two drive signals 115 a - 1 , 115 b - 1 in the case in which the drive signals 115 a - 1 , 115 b - 1 would actually assume the digital value 1, which would lead to an activation of both signal sources 107 a - 1 , 107 b - 1 .

The presented implementation of the logical combination of the input signals 103 a - 1 , 103 b - 1 thus makes it possible to eliminate the common-mode component in the resulting differential output signal 101 . In other words, exemplary embodiments of the present disclosure make it possible to cancel digital bits (in the input signals 103 a - 1 , 103 b ), which would have the effect that signal portions (for example currents) would flow into both terminals 113 a , 113 b (for example also designated as positive side and negative side) of the common load 111 .

FIG. 2 shows, how in conventional vector modulators, a common-mode signal is generated on account of the overlap of the mutually phase-shifted clock signals for the I-portion and the Q-portion. LOI and LOIX are in this case the clock components of the differential clock signal for the I-component and LOQ and LOQX are the clock components of the differential clock signal for the Q-component. The differential clock signal for the I-component and the differential clock signal for the Q-component are phase-shifted by 90°. It becomes clear that common-mode portions arise in the resulting output signal components RF and RFX. The common-mode portions cancel one another in the resulting differential output signal (RFX−RF) and, therefore, do not contribute to the information content of the resulting output signal. Exemplary embodiments of the present disclosure (e.g., device 100 ) can be used in radio-frequency modulators, for example, in order to be able to avoid the disturbing common-mode signals shown in FIG. 2 .

In general, exemplary embodiments of the present disclosure can form differential digital amplifiers or be part thereof.

In this respect, FIG. 3 shows a block diagram of a device 300 in accordance with a further exemplary embodiment of the present disclosure. The device 300 may operate as a differential digital radio-frequency amplifier or digital-to-analogue converter with common-mode suppression.

The device 300 forms a possible extension of the device 100 shown in FIG. 1A with regard to the fact that the device 300 comprises a plurality of pairs of signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n instead of one pair of signal sources. Accordingly, a controller 309 of the device 300 is also designed to activate or deactivate the signal sources of the plurality of pairs of signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n depending on the plurality of input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n.

Each of the pairs of signal sources of the device 300 shown in FIG. 3 has a first activatable signal source 107 a - 1 to 107 a - n for providing a portion 301 a - 1 to 301 a - n of the first output signal component 101 . Furthermore, each pair of signal sources has a second activatable signal source 107 b - 1 to 107 b - n for providing a portion 301 b - 1 to 301 b - n of the second output signal component 101 b . The controller 309 is operably coupled to the plurality of pairs of signal sources and is configured to activate either the first signal source 107 a - 1 to 107 a - n or the second signal source 107 b - 1 to 107 b - n of a (or each) pair of signal sources depending on the plurality of input signals 103 a - 1 to 103 a - n and 103 b - 1 to 103 b - n . In other words, the device 300 shown in FIG. 3 differs from the device 100 shown in FIG. 1A in that the device 300 has a plurality of pairs of signal sources, wherein, as also already in the case of the device 100 in FIG. 1A , the controller 309 of the device 300 at an instant either activates none of the signal sources of a pair of signal sources or activates a maximum of one of the signal sources of a pair of signal sources. In this case, the first signal sources 107 a - 1 to 107 a - n of the pairs of signal sources can be connected to the first terminal 113 a of the common load 111 , such that the first output signal component 101 a is based on a superposition of the portions 301 a - 1 to 301 a - n provided by the first signal sources 107 a - 1 to 107 a - n . Furthermore, the second signal sources 107 b - 1 to 107 b - n of the pairs of signal sources can be connected to the second terminal 113 b of the common load 111 , such that the second output signal component 101 b is based on a superposition of the portions 301 b - 1 to 301 b - n provided by the second signal sources 107 b - 1 to 107 b - n.

In other words, the first signal sources 107 a - 1 to 107 a - n are coupled to a first common terminal 113 a , at which the first output signal component 101 a can be tapped off, and the second signal sources 107 b - 1 to 107 b - n are coupled to a second common terminal 113 b , at which the second output signal component 101 b can be tapped off.

The controller 309 can be designed to (simultaneously) activate a plurality of signal sources of the pairs of signal sources depending on the plurality of input signals 103 a - 1 to 103 a - n (for the first signal sources 107 a - 1 to 107 a - n ) and 103 b - 1 to 103 b - n (for the second signal sources 107 b - 1 to 107 b - n ), such that, apart from changeover instants, at an instant either no signal source or a maximum of one signal source of each pair of signal sources is activated. In other words, the device 300 can be designed in such a way that a plurality of the first signal sources 107 a - 1 to 107 a - n and also a plurality of the second signal sources 107 b - 1 to 107 b - n are simultaneously active at one point in time, but (apart from at changeover instants) at no point in time is more than one signal source of a pair of signal sources active.

This makes it possible that (apart from at changeover instants) at no point in time the both signal sources of a pair of signal sources provide a portion of the respective output signal component 101 a , 101 b , which would mutually cancel one another in the resulting differential output signal 101 and, therefore, would not contribute to the information content of the resulting differential output signal 101 . As can be seen from FIG. 3 , the controller 309 can be designed to receive a dedicated input signal 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n for each signal source of the pairs of signal sources and to provide, for each signal source of the pairs of signal sources, a dedicated drive signal 115 a - 1 to 115 a - n , 115 b - 1 to 115 b - n for driving the respective signal source.

In this case, the controller 309 can determine drive signals (e.g. the drive signals 115 a - 1 , 115 b - 1 ) for the signal sources of a pair of signal sources (e.g. for the signal sources 107 a - 1 , 107 b - 1 ) depending on the input signals (e.g. the input signals 103 a - 1 , 103 b - 1 ) for the signal sources of this pair of signal sources and, in particular, independently of input signals (e.g. the input signals 103 a - 2 to 103 a - n , 103 b - 2 to 103 b - n ) for the signal sources of the remaining pairs of signal sources (e.g. the signal sources 107 a - 2 to 107 a - n , 107 b - 2 to 107 b - n ).

The provision of the drive signals 115 a - 1 to 115 a - n , 115 b - 1 to 115 b - n based on the input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n can therefore be effected for each pair of signal sources independently of the other pairs of signal sources. Therefore, the controller 309 can have one controller 109 - 1 to 109 - n as shown in FIG. 1A for each pair of signal sources of the device 300 and can have, for example, for each pair of signal sources a logical combination corresponding to the true table shown in FIG. 1B and can be implemented, for example, as shown in FIG. 1C .

In other words, the controller 309 can have a plurality of individual controllers 109 - 1 to 109 - n , wherein each of the individual controllers 109 - 1 to 109 - n is designed like the controller 109 - 1 described in FIG. 1A . Therefore, the descriptions given for the controller 109 - 1 are also applicable to the individual controllers 109 - 1 to 109 - n.

To summarize, the controller 309 can be designed to receive, for each pair of signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n , an assigned pair of input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n and to activate and to deactivate the signal sources of each pair of signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n depending on its assigned pair of input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n , independently of the remaining pairs of input signals which are assigned to the remaining pairs of signal sources.

A pair of signal sources can be distinguished by the fact that magnitudes of the portions provided by the signal sources of this pair of signal sources are equal (for example within a tolerance range of ±1%, ±5%, ±10% or ±20% of the portion provided by a first signal source of the pair). Thus, by way of example, a magnitude of a first portion 301 a - 1 of the first output signal component 101 a which is provided by the first signal source 107 a - 1 of the first pair of signal sources 107 a - 1 , 107 b - 1 can be equal in magnitude to a first portion 301 b - 1 of the second output signal component 101 b which is provided by the second signal source 107 b - 1 of the first pair of signal sources 107 a - 1 , 107 b - 1 .

In accordance with some exemplary embodiments, the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n can be designed in such a way that the portions 301 a - 1 to 301 a - n , 301 b - 1 to 301 b - n provided by said signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n are equal at least in terms of magnitude (within a tolerance range). In this case, the tolerance range can be, for example, ±1%, ±5%, ±10% or ±20% of the first portion 301 a - 1 . Thus, the signal sources 107 a - 1 to 107 a - n and the signal sources 107 b - 1 to 107 b - n can be designed, for example, with a sole difference that a sign of the portions 301 a - 1 to 301 a - n provided by the first signal sources 107 a - 1 to 107 a - n differs from a sign of the portions 301 b - 1 to 301 b - n provided by the second signal sources 107 b - 1 to 107 b - n.

The configuration of the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n such that the portions 301 a - 1 to 301 a - n , 301 b - 1 to 301 b - n provided thereby are identical in terms of magnitude corresponds in this case to a thermal coder principle. In other words, in accordance with some exemplary embodiments, in order to generate a balanced differential output signal 101 , the respective bits can be implemented in a thermometer-coded fashion.

In accordance with further exemplary embodiments, a binary coding of the bits is also possible. Thus, by way of example, the first signal source 107 a - 1 of the first pair of signal sources 107 a - 1 , 107 b - 1 can be designed to provide a first basic signal (for example a first basic current I 1 ) as portion 301 a - 1 of the first output signal component 101 a and the first signal sources (for example signal sources 107 a - 2 to 107 a - n ) of the further pairs of signal sources can in this case be designed to provide the first basic signal multiplied with 2 m (m=1 . . . N) as portion 301 a - 1 to 301 a - n of the first output signal component 101 a . Thus, by way of example, a first signal source 107 a - 2 of a second pair of signal sources 107 a - 2 , 107 b - 2 can be designed to provide double the first basic signal (for example 2*I 1 ) as portion 301 a - 2 of the first output signal component 101 a.

Analogously thereto, a first signal source 107 a - n of an n-th pair of signal sources 107 a - n , 107 b - n can be designed to provide n times the first basic signal e.g., n*I 1 ) as portion 301 a - n of the first output signal component 101 a.

In this case, the binary scaling of the portions 301 a - 1 to 301 a - n , 301 b - 1 to 301 b - n provided by the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n can apply both to the portions 301 a - 1 to 301 a - n provided by the first signal sources 107 a - 1 to 107 a - n and to the portions 301 b - 1 to 301 b - n provided by the second signal sources 107 b - 1 to 107 b - n.

Thus, the second signal source 107 b - 1 of the first pair of signal sources 107 a - 1 , 107 b - 1 can be designed to provide a second basic signal (which, by way of example, can be equal in magnitude to the first basic signal) as portion of the second output signal component 101 b and the second signal sources 107 b - 1 to 107 b - n of the further pairs of signal sources can be designed to provide the second basic signal multiplied with 2 m (where m=1 . . . N) as portion 301 b - 2 to 301 b - n of the second output signal component 101 b . Thus, by way of example, a second signal source 107 b - 2 of the second pair of signal sources 107 a - 2 , 107 b - 2 can be designed to provide double the second basic signal (for example 2*I 2 ) as portion 301 b - 2 of the second output signal component 101 b . A second signal source 107 b - n of the n-th pair of signal sources 107 a - n , 107 b - n can be designed to provide n times the second basic signal (e.g., n*I 2 ) as portion 301 b - 1 of the second output signal component 101 b.

Although the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n are illustrated as transistors in a simplified manner in the exemplary embodiment shown in FIG. 3 , a different implementation of the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n is also possible in exemplary embodiments of the present disclosure.

In accordance with one exemplary embodiment of the present disclosure, the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n can be current sources. In accordance with further exemplary embodiments, however, the signal sources 107 a - 1 to 107 a - n , 107 b - 1 to 107 b - n can also be voltage sources.

In accordance with some exemplary embodiments, the device 300 shown in FIG. 3 can form a differential digital RF amplifier, for example, which can also be designated as a signal generator or radio-frequency digital-to-analogue converter. Use is made of n balanced bits in order to generate a differential signal current (the differential output signal 101 ) which is passed into the positive or negative input (the terminals 113 a , 113 b ) of a common load 111 comprising an inductive load having a differential inductance. In order to obtain a balanced differential output signal 101 , said n bits (as already described above) can be implemented, for example, either in a binary coating method or in a thermometer coding method. The device 300 described makes it possible to cancel common-mode portions in the differential digital input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n before the output signal components 101 a , 101 b are actually provided at the differential inductance (or a differential transformer). Therefore, exemplary embodiments of the present disclosure provide a circuit which is designed to carry out a common-mode suppression already in the digital domain of the amplifier, generator or radio-frequency analogue-to-digital converter.

In other words, the controller 309 performs (or more precisely the individual controllers 109 - 1 to 109 - n perform) a common-mode suppression already in the digital domain by logically combining the input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n . To put it more precisely, each of the individual controllers 109 - 1 to 109 - n carries out a common-mode suppression in the received digital input signals 103 a - 1 to 103 a - n , 103 b - 1 to 103 b - n for its respectively assigned pair of signal sources (independently of the other pairs of signal sources).

The device 300 shown in FIG. 3 therefore carries out a cancellation of digital bits which would lead to a current into both sides of the common load 111 comprising the inductive load, to be precise by means of a logical combination of the digital n-bit signals of the two arrays (having the first signal sources 107 a - 1 to 107 a - n and the second signal sources 107 b - 1 to 107 b - n ) which are used to generate the differential output signal 101 .

One advantage of exemplary embodiments of the present disclosure, and in particular of the switching logic illustrated in FIG. 3 , is that no DC and signal current which would be suppressed anyway by the inductive differential load (e.g., of common load 111 ) of the device 300 (e.g., the differential digital RF amplifier) is wasted as a result of the generation of a common-mode component.

Exemplary embodiments can be used for example in digital IQ radio-frequency digital-to-analogue converter architectures. Further exemplary embodiments can be applied to calibrated signals, to signals provided with an interference portion (so-called predistorted signals), or to signals which have been subjected to noise shaping, in which a common-mode component has been introduced in order to modify an original (common-mode-free) signal.

Further exemplary embodiments of the present disclosure can operate as a digital vector mixer (for example a digital IQ mixer).

Furthermore, exemplary embodiments of the present disclosure can be used for all types of differential loads (such as, for example, inductive loads, resistive loads and/or capacitive loads).

Furthermore, exemplary embodiments of the present disclosure can be used in digital phase modulator architectures in order to eliminate digital common-mode components.

Furthermore, exemplary embodiments of the present disclosure can also be used in so-called “mixed signal” digital-to-analogue converters.

Furthermore, further exemplary embodiments of the present disclosure can be used in multi-path digital power amplifier architectures, e.g. for so-called linear gain architectures with non-linear components (LING).

Therefore, exemplary embodiments of the present disclosure also provide a (differential and/or digital) amplifier.

Further exemplary embodiments of the present disclosure provide a radio-frequency modulator (for example comprising a device in accordance with one exemplary embodiment of the present disclosure).

FIG. 4 shows a block diagram of a mobile radio device 400 in accordance with a further exemplary embodiment of the present disclosure.

The mobile radio device 400 comprises a baseband processor 401 , which is designed to provide a digital baseband signal 403 . Furthermore, the mobile radio device 400 comprises a radio-frequency mobile radio modulator 405 . In some exemplary embodiments, the radio-frequency mobile radio modulator 405 comprises the device 100 . In accordance with further exemplary embodiments, the radio-frequency mobile radio modulator 405 can, however, also comprise another device in accordance with one exemplary embodiment of the present disclosure, such as the device 300 , for example.

The radio-frequency mobile radio modulator 405 is coupled to the baseband processor 401 and is designed to provide the plurality of input signals for the device 100 based on the received digital baseband signal 403 .

Furthermore, the mobile radio device 400 comprises an antenna 407 . The antenna 407 is coupled to the radio-frequency mobile radio modulator 405 and thus to the device 100 and is designed to forward or transmit the differential output signal 101 provided by the device 100 (for example via an air interface).

In accordance with some exemplary embodiments, the radio-frequency modulator 405 can be a vector modulator or a polar modulator.

In accordance with further exemplary embodiments, the mobile radio device 400 can be a portable mobile radio device 400 .

By way of example, the mobile radio device 400 can be designed for (wireless) voice communication and/or data communication (for example in accordance with a mobile radio communication standard) with a further (portable) mobile radio device and/or a mobile radio base station.

The mobile radio device 400 can be, for example, a mobile handheld device such as, for example, a mobile telephone (“cellphone”), a so-called smart phone, a tablet PC, a broadband modem, a notebook or a laptop, but also a router or a PC.

FIG. 5 shows a flow chart of a method 500 in accordance with one exemplary embodiment of the present disclosure.

The method 500 for providing a differential output signal having a first output signal component and a second output signal component comprises a step 501 of receiving a plurality of input signals.

Furthermore, the method 500 comprises a step 503 of activating, depending on the plurality of input signals, either a first signal source of a pair of signal sources in order to provide the first output signal component, or a second signal source of the pair of signal sources in order to provide the second output signal component.

In accordance with further exemplary embodiments, step 503 can be effected in such a way that, apart from at changeover instants, that any instant either none of the two signal sources is active or a maximum of one of the two signal sources of the pair of signal sources is active.

The method 500 can be extended by all features of the devices described herein.

Although some aspects have been described in connection with a device, it goes without saying that these aspects also constitute a description of the corresponding method, such that a block or a component of a device should also be understood as a corresponding method step or as a feature of a method step. Analogously to this, aspects which have been described in connection with or as a method step also constitute a description of a corresponding block or detail or feature of a corresponding device.

Depending on specific implementation requirements, exemplary embodiments of the disclosure can be implemented in hardware or in software. The implementation can be carried out using a digital storage medium, for example a floppy disk, a DVD, a Blu-ray disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or some other magnetic or optical storage unit, on which electronically readable control signals are stored which can interact or interact with a programmable computer system in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer-readable. Some exemplary embodiments according to the disclosure therefore comprise a data carrier having electronically readable control signals that are able to interact with a programmable computer system in such a way that one of the methods described herein is carried out.

Generally, exemplary embodiments of the present disclosure can be implemented as a computer program product comprising a program code, wherein the program code is effective to the extent of carrying out one of the methods when the computer program product runs on a computer. The program code can, for example, also be stored on a machine-readable carrier.

Other exemplary embodiments comprise the computer program for carrying out one of the methods described herein, wherein the computer program is stored on a machine-readable carrier.

In other words, one exemplary embodiment of the method according to the disclosure is therefore a computer program having a program code for carrying out one of the methods described herein when the computer program runs on a computer. A further exemplary embodiment of the methods according to the disclosure is therefore a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the methods described herein is recorded.

A further exemplary embodiment of the method according to the disclosure is therefore a data stream or a sequence of signals which represents or represent the computer program for carrying out one of the methods described herein. The data stream or the sequence of signals can be configured for example to the effect of being transferred via a data communication connection, for example via the Internet.

A further exemplary embodiment comprises a processing unit, for example a computer or a programmable logic component, which is configured or adapted to the effect of carrying out one of the methods described herein.

A further exemplary embodiment comprises a computer on which the computer program for carrying out one of the methods described herein is installed.

In some exemplary embodiments, a programmable logic component (for example a field programmable gate array, an FPGA) can be used to carry out some or all functionalities of the methods described herein. In some exemplary embodiments, a field programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein. Generally, the methods in some exemplary embodiments are carried out on the part of an arbitrary hardware device. The latter can be universally usable hardware such as a computer processor (CPU) or hardware specific to the method, such as an ASIC, for example.

The exemplary embodiments described above merely constitute an illustration of the principles of the present disclosure. It goes without saying that modifications and variations of the arrangements and details described herein will become apparent to other persons skilled in the art. Therefore, it is intended that the disclosure be restricted only by the scope of protection of the following patent claims and not by the specific details that have been presented based on the description and the explanation of the exemplary embodiments herein.