Differential signal correction circuit

This application claims priority to Taiwan Patent Application No. 101114413, filed on Apr. 23, 2012, the disclosure of which is hereby incorporated by reference in its entirety.

1. Field of the Disclosure

The present disclosure relates to a differential signal correction circuit.

2. Description of the Related Art

Conventionally, a mobile telephone, a wireless transmission system, and the like include a receiving device, which may use a single antenna to receive a signal. These receiving devices may often operate with harmonic distortion and common mode noise after signal processing via a chip, but these receiving devices are often plagued with bad signal to noise ratio (SNR).

Accordingly, there is a need for a differential signal correction circuit that has a good signal to noise ratio (SNR).

The present disclosure describes a differential signal correction circuit that, through simultaneous phase and amplitude correction, may suppress harmonics and improve the SNR value.

In an embodiment, the differential signal correction circuit may comprise a first single-ended-to-differential converter, a second single-ended-to-differential converter, a first load, and a second load. The first single-ended-to-differential converter may have a first input port, a first output port, and a second output port, wherein the first output port may be coupled with a first output node, the second output port may be coupled with a second output node, the first input port may be configured to receive a first input signal, the first single-ended-to-differential converter may be configured to convert the first input signal into a first current signal and a second current signal, the first current signal may be outputted from the first output port, and the second current signal may be outputted from the second output port. The second single-ended-to-differential converter may have a second input port, a third output port, and a fourth output port, wherein the third output port may be coupled with the first output node, the fourth output port may be coupled with the second output node, the second input port may be configured to receive a second input signal, the second input signal and the first input signal may be a differential signal pair, the second single-ended-to-differential converter may be configured to convert the second input signal into a third current signal and a fourth current signal, the third current signal may be outputted from the third output port, and the fourth current signal may be outputted from the fourth output port. The first load may be coupled between the first output node and a first power source, wherein the first load may be configured to convert a first output current signal collected from the first current signal and the third current signal at the first output node into a first output voltage signal, and the first output voltage signal may be fed back to the first single-ended-to-differential converter for phase and gain correction. The second load may be coupled between the second output node and a second power source, wherein the second load may be configured to convert a second output current signal collected from the second current signal and the fourth current signal at the second output node into a second output voltage signal, and the second output voltage signal may be fed back to the second single-ended-to-differential converter for phase and gain correction.

In another embodiment, the differential signal correction circuit may comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a first load, and a second load. A gate of the first transistor may be configured to receive a first input signal and a source of the first transistor is grounded. A source of the second transistor may be coupled with the gate of the first transistor, and a gate of the second transistor may be coupled with a drain of the first transistor. A source of the third transistor may be configured to receive a second input signal, wherein the first input signal and the second input signal are a differential signal pair. A drain of the third transistor may be coupled with the drain of the first transistor and a gate of the third transistor may be coupled with a drain of the second transistor. A gate of the fourth transistor may be coupled with the source of the third transistor, a drain of the fourth transistor may be coupled with the gate of the third transistor, and a source of the fourth transistor may be grounded. The first load may be coupled between the drain of the first transistor and a first power source. The second load may be coupled between the drain of the fourth transistor and a second power source. The first input signal and the second input signal may be phase corrected by the first transistor, the second transistor, the third transistor, and the fourth transistor. A first output current signal may be collected from a coupled node of the drain of the first transistor and the gate of the second transistor, a second output current signal may be collected from a coupled node of the gate of the third transistor and the drain of the fourth transistor, the first output current signal may be converted into a first output voltage signal by the first load, the second output current signal may be converted into a second output voltage signal by the second load, the first output voltage signal may be fed back to the first transistor and the second transistor via the coupled node of the drain of the first transistor and the gate of the second transistor, the second output voltage signal may be fed back to the third transistor and the fourth transistor via the coupled node of the gate of the third transistor and the drain of the fourth transistor for gain and secondary phase correction.

The present disclosure describes a correction circuit for correcting imperfect differential signal pairs by feeding back the primary corrected signal pair and performing phase and amplitude correction again. Accordingly, the present disclosure advantageously allows for an improved differential signal pair having the same amplitude but opposite phases to be obtained.

The foregoing is a summary and shall not be construed to limit the scope of the claims. The operations and devices disclosed herein may be implemented in a number of ways, and such changes and modifications may be made without departing from this disclosure and its broader aspects. Other aspects, inventive features, and advantages of the disclosure, as defined solely by the claims, are described in the non-limiting detailed description set forth below.

FIG. 1A depicts a conventional differential signal generating circuit.

FIG. 1B depicts a known phase correction circuit.

FIG. 1C depicts a vector diagram of a reference first output current signal and a second output current signal on a trigonometric coordinate system.

FIG. 2A depicts a block diagram of a correction circuit, in accordance with an embodiment of the present disclosure.

FIG. 2B depicts a block diagram of a differential signal correction circuit, in accordance with an embodiment of the present disclosure.

FIG. 2C depicts a vector diagram of a first voltage signal and a second voltage signal on a trigonometric coordinate system, in accordance with an embodiment of the present disclosure.

FIG. 3 depicts a circuit diagram of a correction circuit, in accordance with an embodiment of the present disclosure.

FIG. 4A depicts a character chart of a power factor, a gain error factor, and a gain error sensitivity of a differential signal correction circuit, in accordance with an embodiment of the present disclosure.

FIGS. 4 B(a)-(d) depict sequential waveforms of input signals and output signals of a differential signal correction circuit, in accordance with an embodiment of the present disclosure.

FIGS. 4 C(a)-(d) depict character charts of a gain error, a phase error, an input matching, and an output matching of a differential signal correction circuit, in accordance with an embodiment of the present disclosure.

Reference will be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1A depicts a known differential signal generating circuit used in low frequencies. The differential signal generating circuit 1 A may include a first amplifier A 1 and a second amplifier A 2 . A sine wave input signal S in may be inputted into both the non-inverting input port of the first amplifier A 1 and the inverting input port of the second amplifier A 2 . After the sine wave input signal S in passes through different paths, a first output signal S 1 and a second output signal S 2 are obtained. The first output signal S 1 and the second output signal S 2 may be a differential signal pair that has the same amplitude but a phase difference of 180 degrees. However, a phase error e p and an amplitude error (i.e. gain error) e g may occur in the actual output signals.

FIG. 1B depicts a known phase correction circuit. The phase correction circuit 1 B includes four transistors M 1 , M 2 , M 3 , and M 4 , wherein the first transistor M 1 and the fourth transistor M 4 are identical, and the second transistor M 2 and the third transistor M 3 are identical. The input signals V in1 and V in2 are inputted into the phase correction circuit 1 B through the first input node N I1 and the second input node N I2 , respectively. After the four transistors M 1 , M 2 , M 3 , and M 4 apply the phase correction to the input signals V in1 and V in2 , a first output current signal I out1 and a second output current signal I out2 are obtained from the first output node N O1 and the second output node N O2 , respectively.

One of ordinary skill in the art would appreciate that it may be assumed that the input signals V in1 and V in2 are the differential signal pair with phase error Δθ 1 . The phase error Δθ 2 may exist between the drain current signal I 2 of the second transistor M 2 and the drain current signal I 1 of the first transistor M 1 . The phase error Δθ 2 may also exist between the drain current signal I 3 of the third transistor M 3 and the drain current signal I 4 of the fourth transistor M 4 . If the drain current signal I 1 of the first transistor M 1 is equal to sin(ωt), the drain current signal I 2 of the second transistor M 2 is equal to −sin(ωt+Δθ 2 ), the drain current signal I 4 of the fourth transistor M 4 is equal to −sin(ωt+Δθ 1 ), and the drain current signal I 3 of the third transistor M 3 is equal to sin(ωt+Δθ 1 +Δθ 2 ), then the first output current signal I out1 is equal to I 1 +I 3 (i.e.

I out ⁢ ⁢ 1 = 2 ⁢ ⁢ cos ⁡ ( Δθ 1 + Δθ 2 2 ) * sin ⁡ ( ω ⁢ ⁢ t + Δθ 1 + Δθ 2 2 ) = g 1 * p )

and the second output current signal I out2 is equal to I 2 +I 4 (i.e.

FIG. 1C depicts the reference first output current signal I out1 and the second output current signal I out2 on a trigonometric coordinate system. One of ordinary skill in the art would appreciate that the phase components p of I out1 and I out2 may be substantially different by 180 degrees. Furthermore, the magnitude components g 1 and g 2 may be different from each other. As a result, the phase of the first output current signal I out1 may not be exactly opposite to the phase of the second output current signal I out2 , and the magnitude of the first output current signal I out1 may be different from the magnitude of the second output current signal I out2 .

The Federal Communications Commission (FCC) has adopted a Report & Order allocating and establishing service rules for the 70, 80 and 90 GHz spectrum bands for use by “millimeter wave” technologies. Such uses may include high-speed, point-to-point wireless local area networks and broadband Internet access. Because of the “pencil-beam” technologies that may be used in this band, no frequency coordination may be used. Instead, each path may be registered in a database which may entitle it to interference protection based upon the date of registration.

The 71-76 GHz and 81-86 GHz bands may each be divided into four unpaired 1.25 gigahertz segments for a total of eight segments. Aggregation of these bands may be permitted. The 92-95 GHz band may be divided into two segments. The FCC will issue an unlimited number of non-exclusive, nationwide licenses authorizing use of the entire 12.9 gigahertz of spectrum in these three bands.

Because of shorter wavelengths, the 71-76, 81-86, and 92-95 GHz bands may permit the use of smaller antennas that would be required in lower bands to achieve the same high directivity and high gain. One consequence of this high directivity, coupled with the high free space loss at these frequencies, may be the possibility of a more efficient use of the spectrum for point-to-multipoint applications. One of ordinary skill in the art would appreciate that since a greater number of high directive antennas can be placed than less directive antennas in a given area, the net result is a higher reuse of the spectrum and a higher density of users than in lower frequencies. One of ordinary skill in the art would further appreciate the affect of the phase error and magnitude error of the differential signal.

FIG. 2A depicts a block diagram of a correction circuit 2 in accordance with an embodiment of the present disclosure. The correction circuit 2 may comprise a differential signal correction circuit 2 a and a third single-ended-to-differential converter 25 coupled with the differential signal correction circuit 2 a . The differential signal correction circuit 2 a may comprise a first single-ended-to-differential converter 21 , a second single-ended-to-differential converter 23 , a first load 27 , and a second load 29 .

In an embodiment, the first single-ended-to-differential converter 21 and the second single-ended-to-differential converter 23 may be identical. As one of ordinary skill in the art would appreciate, the first single-ended-to-differential converter 21 and the second single-ended-to-differential converter 23 may comprise the same devices and the same connecting relationship between the devices. The first load 27 and the second load 28 may be identical, and the first load 27 and the second load 28 may be active devices or passive devices, such as transistors, resistors, capacitors, inductances, or transmission lines. The first single-ended-to-differential converter 21 may have a first input port n i1 , a first output port n o1 , a second output port n o2 and a first feedback port n f1 . The second single-ended-to-differential converter 23 may have a second input port n i2 , a third output port n o3 , a fourth output port n o4 , and a second feedback port n f2 . The first output port n o1 and the third output port n o3 may be coupled with a first output node N O1 , the second output port n o2 , and the fourth output port n o4 may be coupled with a second output node N O2 . The first feedback port n f1 may be coupled with the first output node N O1 and the second feedback port n f2 may be couple with the second output node N O2 . In practice, the first feedback port n f1 may be coupled with the first output port n o1 , and the second feedback port n f2 may be coupled with the fourth output port n o4 .

The first load 27 may be coupled between the first output node N O1 and a first power source V DD1 . The second load 29 may be coupled between the second output node N O2 and a second power source V DD2 . In practice, the first power source V DD1 and the second power source V DD2 may be the same power source.

The third single-ended-to-differential converter 25 may be configured to receive an input signal V in and convert the input signal V in into a first input signal V in1 and a second input signal V in2 . The first input signal V in1 and the second input signal V in2 may be a differential signal pair having phase error Δθ 1 and gain error G 1 . The first input signal V in1 from the third single-ended-to-differential converter 25 may be received by the first single-ended-to-differential converter 21 via the first input port n i1 . The second input signal V in2 from the third single-ended-to-differential converter 25 may be received by the second single-ended-to-differential converter 23 via the second input port n i2 .

The first single-ended-to-differential converter 21 may convert the first input signal V in1 into a first current signal I 1 and a second current signal I 2 , in which the first current signal I 1 and the second current signal I 2 may be a differential signal pair with phase error Δθ 2 and gain error G 2 . The first current signal I 1 may be outputted from the first output port n o1 to the first output node N O1 . The second current signal I 2 may be outputted from the second output port n o2 to the second output node N O2 .

The second single-ended-to-differential converter 23 may convert the second input signal V in2 into a third current signal I 3 and a fourth current signal I 4 , in which the third current signal I 3 and the fourth current signal I 4 may be a differential signal pair having phase error Δθ 2 and gain error G 2 . The third current signal I 3 may be outputted from the third output port n o3 to the first output node N O1 . The fourth current signal I 4 may be outputted from the fourth output port n o4 to the second output node N O2 .

A first output current signal I out1 may be collected from the first current signal I 1 and the third current signal I 3 at the first output node N O1 . The first output current signal I out1 may also be presented in an equation: I out1 =I 1 +I 3 . A second output current signal I out2 may be collected from the second current signal I 2 and the fourth current signal I 4 at the second output node N O2 . The second output current signal I out2 may also be presented in an equation: I out2 =I 2 +I 4 . Based on above-mentioned related art, the first output current signal I out1 and the second output current signal I out2 may be corrected signals of the first input signal V in1 that is phase corrected by the first single-ended-to-differential converter 21 , and the corrected signal of the second input signal V in2 that is phase corrected by the second single-ended-to-differential converter 23 , respectively.

The first load 27 may convert the first output current signal I out1 from the first output node N O1 into a first output voltage signal V out1 . The first output voltage signal V out1 may fed back to the first single-ended-to-differential converter 21 via the first feedback port n f1 (i.e. the first output port n o1 ). Accordingly, its amplitude and secondary phase may be corrected by the first single-ended-to-differential converter 21 . The second load 29 may convert the second output current signal I out2 from the second output node N O2 into a second output voltage signal V out2 . The second output voltage signal V out2 may be fed back to the second single-ended-to-differential converter 23 via the second feedback port n f2 (i.e. the fourth output port n o4 ). Accordingly, its amplitude and secondary phase may be corrected by the second single-ended-to-differential converter 23 . The amplitude and secondary phase correction will be described hereafter.

FIG. 2B depicts a block diagram of a differential signal correction circuit 2 a ′ in accordance with an embodiment of the present disclosure. One of ordinary skill in the art would appreciate that the differential signal correction circuit 2 a ′ as shown in FIG. 2B indicates the input and output of signals, which may not be entirely dependent on the connecting relationships of the devices. In an embodiment, the first single-ended-to-differential converter 21 may comprise a first amplifier 211 and a second amplifier 213 , and the second single-ended-to-differential converter 23 may comprise a third amplifier 231 and a fourth amplifier 233 . The first amplifier 211 , the second amplifier 213 , the third amplifier 231 and the fourth amplifier 233 may be devices having three terminals, such as N-channel metal-oxide semiconductor field-effect transistors, SiGe transistors, hetero-junction bipolar transistors (HBT), or bipolar junction transistors. One of ordinary skill in the art would appreciate that the amplifiers 211 , 213 , 231 and 233 are not restricted by the above-mentioned transistors.

The first amplifier 211 may be coupled between the first input port n i1 the first output port n o1 . The second amplifier 213 may be coupled between the first input port n i1 and the second output port n o2 . Further, the first amplifier 211 and the second amplifier 213 may be coupled with the first feedback port n f1 (i.e. the first output port n o1 ). The third amplifier 231 may be coupled between the second input port n i2 and the third output port n o3 . The fourth amplifier 233 may be coupled between the second input port n i2 and the fourth output port n o4 . Further, the third amplifier 231 and the fourth amplifier 233 may be coupled with the second feedback port n f2 (i.e. the fourth output port n o4 ).

One of ordinary skill in the art would appreciate that it may be assumed that an amplification of the first amplifier 211 may be equal to β n1 , an amplification of the second amplifier 213 may be equal to β p1 , an amplification of the third amplifier 231 may be equal to β p2 , an amplification of the fourth amplifier 233 may be equal to β n2 , a resistance of the first load 27 may be equal to A 1 , and an resistance of the second load 29 may be equal to A 2 . Because the first single-ended-to-differential converter 21 and the second single-ended-to-differential converter 23 are identical, the amplification of the first amplifier 211 may be equal to the amplification of the fourth amplifier 233 . It may also be presented in an equation: β n1 =β n2 =β n , in which β n is a first amplification. Also, the amplification of the second amplifier 213 may be equal to the amplification of the third amplifier 231 . It may also be presented in an equation: β p1 =β p2 =β p , in which β p is a second amplification. Because the first load 27 and the second load 29 are identical, the resistance may also be presented in an equation: A 1 =A 2 =A. The corrected signals comprising the first output voltage signal V out1 and the second output voltage signal V out2 may be presented as follows:

The first output voltage signal V out1 and the second output voltage signal V out2 may be presented with respect to the first output current signal I out1 and the second output current signal I out2 by the equation (1) and the equation (2) as follows:

Based on equation (3) and equation (4), if the first amplification β n and the second amplification β p are set up as

β p = ( 1 A + β n ) ,

then the first output voltage signal V out1 and the second output voltage signal V out2 may be presented as V out1 =−V out2 . As a result, the first output voltage signal V out1 and the second output voltage signal V out2 are a differential signal pair having opposite phases but the same amplitude. In practice, the first amplification β n and the second amplification β p may be designated as

β p ≤ ( 1 A + β n ) .

Accordingly, the first output voltage signal V out1 and the second output voltage signal V out2 may be an acceptable differential signal pair.

FIG. 2C depicts a vector diagram of the first voltage signal V out1 and the second voltage signal V out2 on a trigonometric coordinate system. As shown in FIG. 2C , the vector γV out1 and the vector γV out2 have the same amplitude but opposite directions. The coefficient γ may be presented as

In a traditional circuit, the first output voltage signal V out1 and the second output voltage signal V out2 are not fed back into the first single-ended-to-differential converter 21 and the second single-ended-to-differential converter 23 , respectively. The first output voltage signal V out1 and the second output voltage signal V out2 may be presented with respect to the first output current signal I out1 and the second output current signal I out2 as V out1 +V out2 =A(I out1 +I out2 ). Compared with traditional circuits without feedback, the first output voltage signal V out1 and the second output voltage signal V out2 are fed back and corrected by the differential signal correction circuit 2 a ′ again. The corrected first output voltage signal V out1 and the corrected second output voltage signal V out2 may be presented by the following equation (5):

Accordingly, the gain error of the output voltage signals may be reduced from A to

1 ( 1 A + β n + β p )

after correction via the differential signal correction circuit 2 a ′. Therefore, the gain error factor G F may be presented as

FIG. 3 depicts a circuit diagram of a correction circuit 3 in accordance with an embodiment of the present disclosure. The correction circuit 3 of FIG. 3 shows the devices in the differential signal correction circuit 3 a and the third single-ended-to-differential converter 35 . The first single-ended-to-differential converter 31 may comprise a first transistor M 1 regarded as the first amplifier, and a second transistor M 2 regarded as the second amplifier. The second single-ended-to-differential converter 33 may comprise a third transistor regarded M 3 as the third amplifier, and a fourth transistor M 4 regarded as the fourth amplifier. The third single-ended-to-differential converter 35 may comprise a fifth transistor M 5 and a sixth transistor M 6 .

An input signal V in may be inputted into the third single-ended-to-differential converter 35 via the gate of the fifth transistor M 5 . The source of the fifth transistor M 5 and the source of the sixth transistor M 6 may be grounded. The gate of the sixth transistor M 6 may be coupled with the drain of the fifth transistor M 5 . The differential signal pair may comprise a first input signal V IN1 and a second input signal V in2 . The differential signal pair may be obtained after the input signal V in is amplified by the fifth transistor M 5 and the sixth transistor M 6 . The first input signal V in1 may be outputted from the drain of the fifth transistor M 5 to a first input port n i1 of the differential signal correction circuit 3 a . The second input signal V in2 may be outputted from the drain of the sixth transistor M 6 to a second input port n i2 of the differential signal correction circuit 3 a.

The gate of the first transistor M 1 and the source of the second transistor M 2 may be connected to the first input port n i1 . The drain of the first transistor M 1 and the gate of the second transistor M 2 may be connected to the first output port n o1 . The drain of the second transistor M 2 may be connected to the second output port n o2 . The first output port n o1 may be connected to the first output node N O1 . The second output port n o2 may be connected to the second output node N O2 .

The gate of the fourth transistor M 4 and the source of the third transistor M 3 may be connected to the second input port n i2 . The drain of the fourth transistor M 4 and the gate of the third transistor M 3 may be connected to the fourth output port n o4 . The drain of the third transistor M 3 may be connected to the third output port n o3 . The fourth output port n o4 may be connected to the second output node N O2 . The third output port n o3 may be connected to the first output node N O1 . The first load 37 may be connected between the first output node N O1 and a power source. The second load 39 may be connected between the second output node N O2 and a power source.

A first current signal I 1 and a second current signal I 2 may be obtained after the first input signal V in1 is amplified by the first transistor M 1 and the second transistor M 2 . A third current signal I 3 and a fourth current signal I 4 may be obtained after the second input signal V in2 is amplified by the third transistor M 3 and the fourth transistor M 4 . A first output current signal I out1 may be collected from the first current signal I 1 and the third current signal I 3 at the first output node N O1 . A second output current signal I out2 may be collected from the second current signal I 2 and the fourth current signal I 4 at the second output node N O2 . Accordingly, the first input signal V in1 may be phase corrected by the first transistor M 1 and the second transistor M 2 , and the second input signal V in2 may be phase corrected by the third transistor M 3 and the fourth transistor M 4 .

One of ordinary skill in the art would appreciate that one technical feature of an embodiment of the present disclosure lies in the connecting relationship and the parameter design of the of the transistors M 1 , M 2 , M 3 , and M 4 . The parameters may be the bias levels and the amplifications of the transistors M 1 , M 2 , M 3 , and M 4 . In particular, the amplification of the first transistor M 1 and the fourth transistor M 4 may be designed to be equal to a first amplification β n , and the amplification of the second transistor M 2 and the third transistor M 3 may be designed to be equal to a second amplification β p , in which the relationship of the first amplification β n , the second amplification β p and the resistance A of the first load 34 and the second load 39 may be presented as

β p ≤ ( 1 A + β n ) ⁢ :

for well phase and gain (amplitude) correction.

The first output current signal I out1 may be converted into a first output voltage signal V out1 by the first load 37 . The second output current signal I out2 may be converted into a second output voltage signal V out2 by the second load 39 . The first output voltage signal V out1 may be fed back to the first single-ended-to-differential converter 31 via the first output node N O1 . The second output voltage signal V out2 may be fed back to the second single-ended-to-differential converter 33 via the second output node N O2 .

The first output voltage signal V out1 may be amplified by the second transistor M 2 and outputted to the second output node N O2 along a positive feedback path {circle around (3)}, in the meantime, the first output voltage signal V out1 may be amplified by the first transistor M 1 and outputted to the first output node N O1 along a negative feedback path {circle around (1)}. The second output voltage signal V out2 may be amplified by the fourth transistor M 4 and outputted to the second output node N O2 along a negative feedback path {circle around (2)}, in the meantime, the second output voltage signal V out2 may be amplified by the third transistor M 3 and outputted to the first output node N O1 along a positive feedback path {circle around (4)}. A differential signal pair having the same amplitude but a phase difference of 180 degrees may be obtained after the first output voltage signal V out1 and the second output voltage signal V out2 are phase and gain corrected during feedback.

In an embodiment, the differential signal correction circuit 3 a may further comprise a third load 37 and a fourth load 34 . The third load 32 and the fourth load 34 may be active devices or passive devices, such as transistors, resistors, capacitors, inductances or transmission lines. The third load 32 may be connected between the first input port n i1 and the source of the second transistor M 2 . The fourth load 34 may be connected between the second input port n i2 and the source of the third transistor M 3 . Accordingly, the transistors M 1 , M 2 , M 3 , and M 4 may be operated with well impedance matching at high frequency.

FIG. 4A depicts a simulated character chart of a power factor P F , a gain error factor G F and a gain error sensitivity G S of a differential signal correction circuit in accordance with an embodiment of the present disclosure. As shown in FIG. 4A , the power factor P F increases with increasing of the reciprocal of the gain error factor (1+Aβ n +Aβ p ). In particular, when the reciprocal of the gain error factor (1+Aβ n +Aβ p ) is equal to 5˜6 approximately, the gain error factor G F and the gain error sensitivity G S may be substantially low.

FIG. 4 B(a)-(d) are simulated sequential waveforms of input signals V in1 and V in2 and output signals V out1 and V out2 of a differential signal correction circuit in accordance with an embodiment of the present disclosure. As depicted in FIG. 4 B(a), the first input signal and the second input signal have a phase error of 25 degrees (i.e. Δθ 1 =±25° and a gain error of 2 dB (i.e. G 1 =±2 dB). FIG. 4 B(b) depicts the output voltages V out1 and V out2 corresponding to the input signals V in1 and V in2 of FIG. 4 B(a). The output voltages V out1 and V out2 may have the same amplitude but opposite phases.

As depicted in FIG. 4 B(c), the first input signal and the second input signal have a phase error of 60 degrees (i.e. Δθ 1 =)±60° and a gain error of 3 dB (i.e. G 1 =±3 dB). FIG. 4 B(d) depicts the output voltages V out1 and V out2 corresponding to the input signals V in1 and V in2 of FIG. 4 B(c). The output voltages V out1 and V out2 have the same amplitude but opposite phases.

FIG. 4 C(a)-(d) depict simulated character charts of a gain error, a phase error, an input matching, and an output matching of a differential signal correction circuit in accordance with an embodiment of the present disclosure. As depicted in FIG. 4 C(a), when the differential signal correction circuit is operated at frequency of about 83 GHz, the gain may be approximately equal to 4.246 dB. As shown in FIG. 4 C(b), when the differential signal correction circuit is operated at frequency of about 83 GHz, the phase error may be approximately equal to 0.32 degrees and the gain error may be approximately equal to 0.034 dB. As shown in FIG. 4 C(c), when the differential signal correction circuit is operated at frequency of about 83 GHz, the input matching may be about 24.134 dB. As shown in FIG. 4 C(d), when the differential signal correction circuit is operated at frequency of about 83 GHz, the output matching may be about 14.821 dB and 21.217 dB.

At least one advantage of the correction circuit described herein is to allow a differential signal correction circuit to use fewer transistors to accomplish simultaneous phase and gain correction while occupying a small area. Moreover, the differential signal correction circuit may be accepted for correcting differential signals at any frequency band, even at W-band frequency, which still has well correcting effects. As a result, the differential signal correction circuit of the present disclosure may be suitable for RF circuit system and may be capable of raising system performance.

Realizations in accordance with the present disclosure have been described in the context of particular embodiments. These embodiments are meant to be illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Accordingly, plural instances may be provided for components described herein as a single instance. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. These and other variations, modifications, additions, and improvements may fall within the scope of the disclosure as defined in the claims that follow.