Chopped oscillator

This application claims the benefit of priority afforded by U.S. Provisional Application Ser. No. 61/694,381, filed Aug. 29, 2012 the entirety of which is incorporated by reference herein.

The subject matter of this application is directed to a relaxation oscillator, and more particularly to a chopped relaxation oscillator with local comparator biasing.

FIG. 1 illustrates processes involved in a signal sampling system 100 that includes a signal source 110 and a sample and hold (“S/H”) circuit 120 . The signal source 110 generates a continuous time signal such as the signal illustrated in FIG. 1( b ). The S/H circuit 120 may sample the input signal at times as determined by a driving clock signal CLK. Typically, the sampling times are determined by rising and/or falling edges of the CLK signal. The S/H circuit 120 holds the sampled signal value for processing by other circuits within the system, for example, an analog-to-digital converter 130 , until the CLK signal defines another sampling instant. For the input signal shown in FIG. 1( b ), the S/H circuit 120 might generate an output signal as shown in FIG. 1( c ).

Ideally, the CLK signal defines sampling events that occur at precisely defined intervals that are uniformly spaced. The CLK signal may be generated by an oscillator (e.g., a relaxation oscillator that uses charge and discharge time of a capacitor). However, random processes that exist within practical implementations will move these sampling instances. This error is referred to as phase noise.

The uncertainty in the absolute time of any edge coming out of a clock source is the sum of all the uncertainties in the clock periods that provide this edge. Any error source that modifies a period of the clock source will be integrated when considering the absolute timebase accuracy. If a sinusoid is sampled with the signal sampling system 100 , then in the frequency domain the sampled signal will be smeared by the uncertainty of the timebase. While most of the smeared energy will be found near the ideal location of the energy, some of the smeared energy will be further away from the ideal location. Error sources having more energy at low frequencies, will introduce more uncertainty in the timebase at low frequencies and will increase the sinusoidal smearing. Reducing these low frequency error sources would provide better on chip clock sources.

Accordingly, there is a need in the art for relaxation oscillators that reduce the phase noise.

So that features of the present invention can be understood, a number of drawings are described below. It is to be noted, however, that the drawings illustrate only particular embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the invention may encompass other equally effective embodiments.

FIG. 1 illustrates processes involved in a signal sampling system that includes a signal source and a sample and hold (“S/H”) circuit.

FIGS. 2( a )- 2 ( c ) illustrate structure and operation of a relaxation oscillator.

FIG. 3 illustrates a relaxation oscillator according to another embodiment of the present invention.

FIG. 4 illustrates a relaxation oscillator according to another embodiment of the present invention.

FIG. 5 illustrates a chopped amplifier according to an embodiment of the present invention.

FIG. 6 illustrates a relaxation oscillator according to another embodiment of the present invention.

Embodiments of the present disclosure may provide a relaxation oscillator with improved performance against phase noise error and reduce the smearing seen in the sampled signal. In particular, the phase noise error may be reduced from sources whose power is greater at lower frequencies. To reduce the phase noise error and/or smearing in the sampled signal, the relaxation oscillator may include chopping in the charging current driver, chopping in the trigger level generator, and/or chopping in the currents that feed the cells. A chopped amplifier may be provided to perform chopping of the input signals.

FIG. 2 illustrates structure and operation of a relaxation oscillator 200 that may include one or more chopping circuits. The relaxation oscillator 200 may use the charge and discharge times of a capacitor to generate a clock signal CLK. The relaxation oscillator 200 may include a capacitor C 1 that is charged and discharged during operation, a comparator 210 that compares an input oscillation signal V OSC from the capacitor C 1 to a threshold voltage V TH , a trigger voltage generator 230 to provide the threshold voltage V TH , and a current generator 220 that provides current to the capacitor C 1 to charge and discharge the capacitor C 1 . The relaxation oscillator 200 may perform chopping in the current generator 220 , in the trigger voltage generator 230 and/or the currents that feed the current generator 220 and the trigger voltage generator 230 . The chopping may interrupt and/or switch currents provided by the current source or signals generated within the circuits.

The current generator 220 may include a pair of current sources I 1 , I 2 connected to the capacitor C 1 by respective coupling switches SW 1 , SW 2 . When SW 1 is closed, current source I 1 charges the capacitor C 1 at a predetermined rate. When SW 2 is closed, current source I 2 discharges the capacitor C 1 at a predetermined rate (ideally, equal but opposite to the rate at which I 1 charges the capacitor C 1 ). Including two current sources I 1 and I 2 in the current generator 220 provides two switchable paths that may reduce the noise components. While FIG. 2( a ) illustrates the current generator 220 including two current sources I 1 , I 2 , other arrangements of one or more current sources may be used to charge and discharge the capacitor C 1 . For example, a single current source (e.g., current source 12 ) may be used to charge and discharge the capacitor C 1 .

The trigger voltage generator 230 may provide a threshold voltage to the comparator 210 . The trigger voltage generator 230 may include a voltage divider network formed by a plurality of resistors (e.g., three resistors R 1 , R 2 , R 3 ) that is coupled to the comparator 210 by coupling switches SW 3 , SW 4 . When switch SW 3 is closed, the comparator's input is coupled to a high voltage level (V TH =V HI ) generated within the voltage divider network. When switch SW 4 is closed, the comparator's V TH input is coupled to a low voltage level (V TH =V LO ) generated within the voltage divider network.

FIGS. 2( b )-( c ) illustrate signals generated by the relaxation oscillator. Voltages V OSC , V HI and V LO are illustrated in FIG. 2( b ). The CLK output is shown in FIG. 2( c ). Ideal operation is shown in phantom lines and one possible variant of actual operation in the presence of noise is shown in solid lines.

Ideally, the capacitor voltage would be compared directly to the V HI and V LO thresholds, which would generate a 50% duty cycle clock at a predetermined clock period. In practice, however, the resistor devices within the voltage divider network generate frequency dependent noise, which causes the V HI and V LO voltages as used by the comparator 210 to vary from ideal levels. FIG. 2( b ) illustrates such errors schematically.

If the noise causes the V HI voltage as input to the comparator to exceed the ideal level of V HI , then, working from a common starting point, the capacitor voltage V OSC would toggle the comparator 210 at a time later than is ideal. If the noise causes the V LO voltage, as input to the comparator to be lower than the ideal level of V LO , then the capacitor voltage V OSC would toggle the comparator 210 at a time later than is ideal.

FIG. 2( b ) illustrates only one possible scenario involving noise effects. In one instance noise effects can cause the V TH as used by the comparator 210 to be lower than the ideal V TH and/or can cause the V LO as used by the comparator 210 to be higher than the ideal V LO . Thus, noise effects can cause the CLK signal to run either faster or slower than the ideal case. Because the phase error continually accumulates this source of error, then a 1/f^n noise process would result in a phase error whose magnitude varies with frequency with a 1/f^(n+2) characteristic.

To reduce the noise effects, embodiments of the present disclosure include providing a chopping circuit (not shown in FIG. 2( a )) in one or more of the current generator 220 , the trigger voltage generator 230 , and/or currents that feed the current generator 220 and/or the trigger voltage generator 230 . The chopping circuit may interrupt and/or switch the signals generated within the current generator 220 or the trigger voltage generator 230 . Inverting the effects of different noise sources via the chopping circuit within the current generator 220 and/or the trigger voltage generator 230 for half the time may cancel their effect on the final sampled system. The chopping circuit may invert the effect of the noise sources for each phase of a CHOP signal.

FIG. 3 illustrates a relaxation oscillator 300 according to an embodiment of the present invention. To reduce the noise effects in the relaxation oscillator 300 , chopping may be performed in the current generator 320 . The chopping may be performed in the circuit supplying the current to the capacitor C 1 and/or the circuit draining the current from the capacitor C 1 .

The relaxation oscillator 300 may include a capacitor C 1 that is charged and discharged during operation, a comparator 310 that receives a V OSC signal from the capacitor C 1 and a V TH voltage, a trigger voltage generator 330 that supplies V TH voltage in response to a CLK signal, and a current generator 320 that selectively supplies current to the capacitor C 1 or drains current from the capacitor C 1 in response to a CLK signal output from the comparator 310 . The relaxation oscillator 300 may include a clock divider 350 that divides the CLK signal by half to generate a CHOP signal. The CHOP signal may be used to control the chopping in the current generator 320 .

The trigger voltage generator 330 may be formed by three resistors R 1 , R 2 , R 3 that is coupled to the comparator 310 by coupling switches SW 1 , SW 2 . When switch SW 1 is closed, the V TH input is coupled to a high voltage level (V TH =V HI ) generated within the voltage divider. When switch SW 2 is closed, the V TH input is coupled to a low voltage level (V TH =V LO ) generated within the voltage divider.

The current generator 320 may supply current to the capacitor C 1 during a charging phase of operation and may drain current from the capacitor C 1 during a draining phase of operation. The current generator 320 may include a first chopped current mirror configuration 320 A to supply current to the capacitor C 1 and a second chopped current source 320 B to drain current from the capacitor C 1 .

The first chopped current mirror configuration 320 A may include a pair of transistors TR 1 , TR 2 and a plurality of switches (e.g., switches SW 3 , SW 4 , SW 5 , SW 6 , SW 7 and SW 9 ) controlling the supply of current via the transistors TR 1 , TR 2 . Each transistor TR 1 , TR 2 can be configured to supply current to the capacitor C 1 in a separate phase of the CHOP signal. The gate of each transistor TR 1 , TR 2 may be connected to its drain via a respective connecting switch SW 3 , SW 4 . The drain of each transistor TR 1 , TR 2 may be coupled to the capacitor C 1 via a respective connecting switch SW 5 , SW 6 . The current used to charge the timing capacitor C 1 is coupled through SW 7 when needed.

The switches can be driven by CHOP and CHOP control signals such that, in a first phase of operation (e.g., when CHOP=1), a first transistor (TR 1 ) outputs current to the capacitor C 1 (via switch SW 5 ) while the gate of the other transistor (TR 2 ) is connected to its own drain via switch SW 4 , thus setting the gate voltage of the first transistor (TR 1 ). In a second phase of operation (e.g., when CHOP=0), the second transistor (TR 2 ) outputs current to the capacitor C 1 (via switch SW 6 ) while the gate of the first transistor (TR 1 ) is connected to its own drain via switch SW 3 . The error produced may cancel when seen in average because in the first phase of operation (e.g., when CHOP=1) the output will see a negative version of the errors that are seen in the second phase of operations (e.g., when CHOP=0). The first chopped current mirror may be connected to the charging capacitor C 1 via switch SW 7 during a predetermined phase of the CLK signal ( CLK ).

The second chopped current source 320 B may drain current from the capacitor C 1 during a second phase of the CLK signal. The second chopped current source 320 B may be connected to the charging capacitor C 1 via a connecting switch SW 8 during a predetermined phase of the CLK signal (CLK). The second chopped current source 320 B may include a transistor TR 3 , a resistor R 4 , an amplifier 332 , a chop circuit 334 . 1 , 334 . 2 , a current source I 1 and biased resistor R 5 .

The transistor TR 3 may have a source to drain path that connects the capacitor C 1 to ground (via a resistor R 4 ). The voltage at an intermediate node N 1 between transistor TR 3 and resistor R 4 may vary based on the gate voltage of the transistor TR 3 and the voltage on the capacitor C 1 . The current source 11 and the biased resistor R 5 may generate a reference voltage at an intermediate node N 2 between them. The amplifier 332 may generate a control signal to the transistor TR 3 based on a comparison of voltages present on the N 1 , N 2 nodes. The amplifier 332 , which may be a differential in, differential out amplifier, may provide a differential output based on the comparison of voltages present on the N 1 , N 2 nodes. The current used to discharge the timing capacitor C 1 is coupled to it through SW 8 when needed. The chop circuit 334 . 1 may change the orientation of the N 1 , N 2 voltages as input to the amplifier 332 based on the CHOP signal, along with reversing the input terminals of the amplifier 332 . The chop circuit 334 . 2 may receive the differential output of the amplifier 332 and provide a single ended stage to the transistor TR 3 . The chop circuit 334 . 2 may switch the orientation of the differential output provided by the amplifier 332 . The closed high gain loop may cause any noise sources to be dropped across the linear resistor R 4 . By inverting these each chop cycle, the linear nature of R 4 may cause the low frequency source to cancel on average. The amplifier 332 and the chop circuit 334 . 1 , 334 . 2 provide the second chopped current mirror 320 B with a reference current through SW 9 while C 1 is being charged, so that the current pulling up capacitor C 1 is fully chopped without requiring a further mirror. While a differential in, differential out amplifier is shown in FIG. 3 , an amplifier with a single ended output may be directly used as a control signal to the transistor TR 3 . A differential to single ended stage may be provided at the outputs of the amplifier 332 .

Either the CLK signal or the CHOP control signals can be used as a clock source, the chopping being invisible on the CHOP control signal. The CLK signal may be used for clocking lower frequencies.

FIG. 4 illustrates a relaxation oscillator 400 according to another embodiment of the present invention. To reduce the noise effects in the relaxation oscillator 400 , chopping may be performed in the trigger voltage generator 430 . The chopping may be included in the circuit supplying the reference voltage V TH to the comparator 410 .

The relaxation oscillator 400 may include a capacitor C 1 that is charged and discharged during operation, a comparator 410 that receives a V OSC signal from the capacitor C 1 and a V TH voltage, a trigger voltage generator 430 that supplies V TH voltage in response to a CLK signal, and a current source 420 that selectively supplies current to the capacitor C 1 or drains current from the capacitor C 1 in response to a CLK signal output from the comparator 410 . The relaxation oscillator 400 may include a clock divider 450 that divides the CLK signal by half to generate a CHOP signal. The CHOP signal may be used to control the chopping in the trigger voltage generator 430 .

The current generator 420 may include a pair of current sources I 1 , I 2 connected to the capacitor C 1 by respective coupling switches SW 1 , SW 2 . When SW 1 is closed, current source I 1 may charge the capacitor C 1 at a predetermined rate. When SW 2 is closed, current source I 2 may discharge the capacitor C 2 at a predetermined rate (ideally, equal but opposite to the rate at which I 1 charges the capacitor C 1 ).

The trigger voltage generator 430 may supply the V TH voltage in response to a CLK signal. The trigger voltage generator 430 may provide a plurality of different voltage values to the comparator 410 in response to a CLK signal. For example, during each cycle or phase of the clock a different voltage value may be provided to the comparator 410 .

The trigger voltage generator 430 may include a voltage source V 1 to provide a V HI threshold to the comparator 410 , and a chopped resistive mirror to supply a V LO threshold to the comparator 410 . The voltage source V 1 may provide the V HI threshold to the comparator 410 when switch SW 3 is closed in response to a control signal (e.g., CLK signal). The chopped resistive mirror may supply the V LO threshold to the comparator 410 when switch SW 4 is closed and switch SW 3 is open. A resistor R 1 may be provided between the voltage source V 1 and the chopped resistive mirror.

The chopped resistive mirror may include a transistor TR 4 , a resistor R 2 , an amplifier 432 , a current source I 3 and a resistor R 3 . The switch SW 4 may connect the chopped resistive mirror to the comparator 410 during a predetermined phase of the CLK signal (CLK). The transistor TR 4 may have a source to drain path that connects the comparator 410 to ground (via a resistor R 2 ). The current source I 3 and biased resistor R 3 may generate a reference voltage at an intermediate node N 2 . The amplifier 432 may generate a control signal to the transistor TR 4 based on a comparison of voltages present on the N 1 , N 2 nodes. The amplifier may include a chop circuit (not shown in FIG. 4 ) to change the orientation of the voltage at nodes N 1 , N 2 as input to the amplifier 432 based on the CHOP signal. Changing the orientation of the voltage at nodes N 1 , N 2 within the amplifier 423 may provide the error source on opposite terminals of the amplifier 432 when the CHOP signal changes. The configuration of the chop circuit 334 . 1 and 334 . 2 may be used for the chop circuit of the amplifier 432 . The amplifier 432 may be a differential in, differential out amplifier.

The current source I 3 applied across biased resistor R 3 generates a reference voltage at the intermediate node N 2 . The amplifier 432 and transistor TR 4 can be used to force the reference voltage at node N 2 to the node N 1 . The low frequency amplifier 432 noise can be reduced by changing the orientation of the N 1 , N 2 voltages as input to the amplifier 432 based on the CHOP signal. The low frequency noise in the voltage source V 1 may be ignored because the voltage source V 1 noise does not affect the difference in trigger levels. Only the common mode voltage may not alter the clock frequency.

FIG. 5 illustrates a chopped amplifier 500 according to an embodiment of the present invention. The chopped amplifier 500 may be included in the current generator 220 , 320 , 420 and/or the trigger voltage generator 230 , 330 , 430 , shown in FIGS. 2( a ), 3 and 4 . The chopped amplifier 500 may include a chopped differential amplifier 510 and a source follower circuit 520 .

The chopped differential amplifier 510 may include a chop circuit to swap the input devices TR 1 and TR 2 that connect to the inputs Vin 1 and Vin 2 based on a CHOP signal. To maintain the same ideal behavior the load presented to the differential current coming out of TR 1 and TR 2 is also reconfigured with the CHOP signal such that the transfer function from the differential signal Vin 1 -Vin 2 to the single ended signal at the gate of TR 5 is the same when CHOP=0 and CHOP=1. The chopped amplifier 500 may be driven by CHOP and CHOP control signals to operate various switches in the chopped amplifier 500 to change the devices that will be seen by the inputs Vin 1 and Vin 2 . The chopped amplifier 500 may generate a control signal (VOUT) based on a comparison of the voltages (Vin 1 and Vin 2 ) input into the chopped amplifier 500 . The voltages (Vin 1 and Vin 2 ) input into the chopped amplifier 500 may be compared via different transistors and current paths in each phase of the CHOP control signal.

The chopped differential amplifier 510 may include switches SW 1 , SW 3 , SW 5 and SW 7 to provide a path in normal mode (first phase of operation) and switches SW 2 , SW 4 , SW 6 and SW 8 to provide a path in chopped mode (second phase of operation). In each phase of operation, different switches may be activated to switch the inputs signals being provided to the respective transistors (e.g., TR 1 and TR 2 ) in the amplifier 500 . A current source provides current to the sources of the input transistors TR 1 , TR 2 . The input transistors TR 1 , TR 2 may be coupled to a pair of load transistors TR 3 , TR 4 having their gates coupled together. The drain of one of the load transistors TR 3 , TR 4 may be coupled to the source follower circuit 520 .

The switches in the chopped amplifier 500 may be driven by CHOP and CHOP control signals such that, in a first phase of operation, the input Vin 1 is provided to transistor TR 1 and the input Vin 2 is provided to transistor TR 2 and in the second phase of operation the input Vin 1 is provided to transistor TR 2 and the input Vin 2 is provided to transistor TR 1 . In the first phase of operation switches SW 1 , SW 3 , SW 5 and SW 7 can be turned on and switches SW 2 , SW 4 , SW 6 and SW 8 can be turned off. In the second phase of operation switches SW 2 , SW 4 , SW 6 and SW 8 can be turned on and switches SW 1 , SW 3 , SW 5 and SW 7 can be turned off. Including the chopped circuit in the amplifier 500 allows for the mismatch and low frequency errors in the first stage when referred to the inputs Vin 1 and Vin 2 of the chopped amplifier 500 to be changed so that they cancel in average with the second phase of the CHOP signal. The gain of the first stage causes any errors in the second stage to be greatly attenuated when referred to the input so it would not benefit from chopping.

As shown in FIG. 5 , the drains of TR 1 and TR 3 are always connected as are the drains of TR 2 and TR 4 such that the error sources in TR 3 can always be referred to the gate of TR 1 and similarly for TR 4 and TR 2 . This means that reconfiguring the load does not detract from the chopping action when related to the error sources in TR 3 and TR 4 .

Switches SW 7 , SW 8 may couple one of the drains of the load transistors TR 3 , TR 4 to the source follower circuit 520 , based on the CHOP signal. In one phase of the CHOP signal, the switch SW 7 may couple the drain of the transistor TR 4 to the source follower circuit 520 and in the next phase of the CHOP signal, the switch SW 7 may couple the drain of the transistor TR 3 to the source follower circuit 520 .

The source follower circuit 520 may include a transistor TR 5 and a current source I 2 and may receive an input signal at the gate of the transistor TR 5 and provide an output signal VOUT at the source of the transistor TR 5 . The transistor TR 5 may receive the input signal from one of the drains of transistors TR 3 or TR 4 via switch SW 7 or SW 8 . The input signal received at the gate of the transistor TR 5 may be switched between the drains the drains of transistors TR 3 or TR 4 in each phase of the CHOP signal.

FIG. 6 illustrates a relaxation oscillator 600 according to another embodiment of the present invention. To reduce the noise effects in the relaxation oscillator 600 , chopping may be performed in the currents that feed the current generator 620 and the trigger voltage generator 630 . The chopping circuit may switch the current sources that provide current to the current generator 620 and the trigger voltage generator 630 in response to a CHOP control signal. In one phase of the CHOP signal, a first current source may be coupled to the current generator 620 , while a second current source is coupled to the trigger voltage generator 630 . In the next phase of the CHOP signal, the first current source may be coupled to the trigger voltage generator 630 , while the second current source is coupled to the current generator 620 .

The relaxation oscillator 600 may include a capacitor C 1 that is charged and discharged during operation, a comparator 610 that receives a V OSC signal from the capacitor C 1 and a V TH voltage, a current generator 620 that supplied and drains current to the capacitor C 1 , a trigger voltage generator 630 that supplies V TH voltage to the comparator 610 , and a current controller 640 to provide currents to the current generator 620 and the trigger voltage generator 630 . The relaxation oscillator 600 may include a clock divider 650 that divides the CLK signal by half to generate a CHOP signal. The CHOP signal may be used to control the chopping in the current controller 640 .

The current generator 620 may selectively supply current to the capacitor C 1 or drain current from the capacitor C 1 in response to a CLK signal output from the comparator 610 . The current generator 620 may include a pair of current sources I 1 , I 2 connected to the capacitor C 1 by respective coupling switches SW 1 , SW 2 . When SW 1 is closed, current source 11 charges the capacitor C 1 at a predetermined rate. When SW 2 is closed, current source I 2 discharges the capacitor C 2 at a predetermined rate (ideally, equal but opposite to the rate at which I 1 charges the capacitor C 1 ).

The trigger voltage generator 630 may supply V TH voltage in response to a CLK signal. The trigger voltage generator 630 may provide a plurality of different voltage values to the comparator 610 in response to a CLK signal. The trigger voltage generator 630 may include a voltage source V 1 to provide a V HI threshold to the comparator 610 when switch SW 3 is closed in response to a control signal, a resistor R to provide a voltage drop, and a current source I 3 to force a current across resistor R and provide V LO threshold to the comparator 610 when switch SW 4 is closed in response to a control signal.

The current controller 640 may provide currents to the current generator 620 and the trigger voltage generator 630 based on the CHOP signal provided by the clock divider 650 . The current controller 640 may provide a plurality of different currents to the current generator 620 and the trigger voltage generator 630 and switch the current provided to these circuits using a chopping circuit 642 . The current controller 640 may include a current source I A , a current source I B and a chop circuit 642 that changes orientation of the current provided by the current source I A and the current provided by the current source I B . The currents provided by the current source I A and the current source I B can be changed over each chop cycle between the current generator 620 and the trigger voltage generator 630 . For example, in the first phase of the CHOP signal, the current source I A may be coupled to the current generator 620 , while the current source I B is coupled to the trigger voltage generator 630 . In the second phase of the CHOP signal, the current source I A may be coupled to the trigger voltage generator 630 , while the current source I B is coupled to the current generator 620 .

The chop circuit 642 contributes to noise cancellation caused by current sources which can achieve improved immunity to noise error. By inverting the effects of the noise components of the current sources I A and I B in alternating phases of the CHOP signal, embodiments of the present invention achieve an output CLK signal that provides improved matching to an ideal CLK signal. The CHOP signal can eliminate or reduce the error in the CLK signal due to deviations of the current sources I A and I B from ideal current sources.

For example, the chop circuit 642 may compensate for error due to one of the current sources I A and I B providing a high current, by switching between the current sources I A and I B . The clock provided by the relaxation oscillator 600 will be fast if the high current is supplied to the current generator 620 . However, the clock provided by the relaxation oscillator 600 will be slow if the high current is supplied to the trigger voltage generator 630 . The chop circuit 642 switches the currents provided to the current generator 620 and the trigger voltage generator 630 to remove the effect of the low frequency noise in the current sources I A and I B on the clock generated by the current generator 620 , as the error will average to zero.

In the above description, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the inventive concepts. As part of this description, some structures and devices may have been shown in block diagram form in order to avoid obscuring the invention. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, and multiple references to “one embodiment” or “an embodiment” should not be understood as necessarily all referring to the same embodiment.

One or a plurality of the above illustrated operations may be implemented in a computer program that may be stored on a storage medium having instructions to program a system to perform the operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software modules executed by a programmable control device.

As used in any embodiment in the present disclosure, “circuitry” may comprise, for example, singly or in any combination, analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. Also, in any embodiment herein, circuitry may be embodied as, and/or form part of, one or more integrated circuits.

Although the methods illustrated and described herein include series of steps, it will be appreciated that the different embodiments of the present disclosure are not limited by the illustrated ordering of steps, as some steps may occur in different orders, some concurrently with other steps apart from that shown and described herein. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Moreover, it will be appreciated that the processes may be implemented in association with the apparatus and systems illustrated and described herein as well as in association with other systems not illustrated.

It will be appreciated that in the development of any actual implementation (as in any development project), numerous decisions must be made to achieve the developers' specific goals (e.g., compliance with system and business related constraints), and that these goals will vary from one implementation to another. It will also be appreciated that such development efforts might be complex and time consuming, but would nevertheless be a routine undertaking for those of ordinary skill in art having the benefit of this disclosure.