Skip mode method and system for a current mode switching converter

1. Field of the Invention

This invention relates generally to switching power converters, and more particularly to current mode switching converters that employ a ‘skip’ mode to prevent inductor current runaway during start-up.

2. Description of the Related Art

One method of controlling a switching converter is referred to as “current mode” control, in which the inductor current is used to regulate the output voltage. To prevent the noise generated by an ‘off’ to ‘on’ transition of the converter's high side switching element from corrupting the sensing of the inductor current, such a converter typically employs a “blanking time” at the transition point, which prevents the high side switching element from being switched off due to the noise. The duration of the “blanking time” is referred to as the converter's “minimum on-time”.

However, since the high side switching element cannot be turned off during the blanking time, the inductor current will continue to increase throughout this interval. This may result in the inductor current becoming excessively high when the converter is first started up (sometimes referred to as ‘soft-start’) and the regulation loop is not yet in full operation, especially when the switching frequency is high.

One conventional solution for this problem is to introduce a pulsed-frequency mode (PFM) of operation during start-up, which under certain conditions causes a ‘skip mode’ to be triggered during which the operation of the switching elements is temporarily suspended. An example of such a converter is shown in FIG. 1 . High and low side switching elements 10 and 12 are driven by pulse-width modulated (PWM) drive signals received from a gate driver 14 , which is driven with a PWM signal 16 provided by an SR latch 18 to regulate the converter's output voltage Vout. An oscillator 20 provides a clock signal Clk_shot which is applied to the SET input of latch 18 such that, in normal operation, the latch is set and high side switching element 10 is turned on each time the Clk_shot signal pulses.

An error amplifier 22 produces an output V COMP which varies with the difference between a voltage V FB that varies with Vout and a reference voltage V REF . V COMP is summed with a slope compensation signal V RAMP to provide a voltage V C . Voltage V C and a signal I DETECT — PEAK , which varies with the current conducted by high side switching element 10 , are provided to a PWM comparator 24 , the output 26 of which is used to reset latch 18 in normal operation.

To prevent inductor current runaway during start-up, voltage V C is provided to a pulsed-frequency modulated (PFM) comparator 28 , which also receives a predetermined PFM threshold voltage V PFM . When V C is less than V PFM , the output ‘skip’ of comparator 28 goes high. An OR gate 32 receives the output 26 from comparator 24 and output ‘skip’ from comparator 28 at respective inputs, and produces an output 34 which is applied to the RESET input of SR latch 18 .

The operation of the converter of FIG. 1 is illustrated with the timing diagram shown in FIG. 2 . When V C is less than V PFM , this indicates that the control loop is calling for very little inductor current (I L ), which is an indication that I L is too high. During these periods, the ‘skip’ output and thus the RESET input of latch 18 are high, and the converter operates in skip mode; this prevents the latch from being set and thus no new PWM pulses are delivered to switching elements 10 and 12 . However, when V C is greater than V PFM , this indicates that the inductor current is at an acceptable level, and thus PWM pulses which regulate Vout are provided to switching elements 10 and 12 .

This approach has a drawback, however, due to the fact that there is a phase lag in which V COMP and V C lag behind inductor current I L ; this is due to the effects of the converter's output capacitor C out and the compensation components 35 typically found in such converters. Thus, at start-up when Vout is close to zero, several minimum on-time pulses 34 can be generated before skip mode can be triggered. This may result in an unacceptably high inductor current 36 , especially when the switching frequency is high. Moreover, transitions between skip mode and the normal PWM mode can cause output voltage Vout to dip and recover as it increases from zero, resulting in a large output ripple.

A skip mode method and system for a current mode switching converter are presented which address the problems discussed above.

The present method is used to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. The method requires:

comparing a current I C that varies with the difference between a reference voltage and a voltage proportional to Vout and a current I DETECT — PEAK which varies with the current conducted by the high side switching element; using the result of the comparison of I C and I DETECT — PEAK to control the regulation of the output voltage during normal operation; comparing the current I C and a current I DETECT — VALLEY which varies with the current conducted by the low side switching element; and triggering a ‘skip mode’ during which the switching signals are inhibited when I DETECT — VALLEY >I C .

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and claims.

FIG. 1 is a block/schematic diagram of a known current mode switching converter.

FIG. 2 is a timing diagram illustrating the operation of the converter of FIG. 1 .

FIG. 3 is a block/schematic diagram of a current mode switching converter per the present invention.

FIG. 4 is a timing diagram illustrating the operation of the converter of FIG. 3 .

FIG. 5 is a timing diagram illustrating the performance of the converter of FIG. 3 .

FIG. 6 is a block/schematic diagram of another embodiment of a current mode switching converter per the present invention.

One possible embodiment of a current mode switching converter which implements the present ‘skip mode’ method is shown in FIG. 3 . The method is for use with a current mode switching converter having high and low side switching elements 40 , 42 coupled to an output inductor L 1 , the other end of which is coupled to an output node, and operated with respective modulated switching signals 44 , 46 to regulate an output voltage Vout produced at the output node.

The present converter comprises a first current comparator 50 which receives a current I C that varies with the difference between a reference voltage V REF and a voltage V FB proportional to Vout at a first input, and a current I DETECT — PEAK which varies with the current conducted by high side switching element 40 at a second input, and which produces an output 52 arranged to control the regulation of Vout during ‘normal’ operation.

The converter also includes a second current comparator 54 which receives the current I C at a first input and a current I DETECT — VALLEY which varies with the current conducted by low side switching element 42 at a second input, and which produces an output 56 which toggles when I DETECT — VALLEY >I C . When the output of second current comparator 54 indicates that I DETECT — VALLEY >I C , the converter is arranged to trigger a ‘skip mode’ during which switching signals 44 , 46 are inhibited. Note that as used herein, the term ‘normal operation’ is meant to refer to the operation of the converter when it is not in skip mode.

Thus, both peak and valley inductor currents are monitored cycle-by-cycle, with both currents used to limit inductor current. By so doing, the level reached by the inductor current during start-up is likely to be less than it would have been if switching elements 40 , 42 had continued to be switched when I DETECT — VALLEY >I C , with the increase of voltage Vout from zero to its desired level likely to occur more smoothly than it would otherwise.

To generate current I C , the converter would typically employ an error amplifier 60 which produces an output V COMP that varies with the difference between V REF and V FB ; compensation components 61 would typically be used with the error amplifier. A voltage-to-current (V-to-I) converter 62 —typically a transconductance amplifier—is then used to convert V COMP to a current I COMP . A summing circuit 64 is arranged to sum I COMP with a slope compensation signal I RAMP to produce current I C .

The converter typically has an oscillator 66 which provides the timing signals needed to operate the converter; one output of oscillator 66 is a periodic pulse Min_off. A flip-flop 68 is arranged to receive the output 56 of second current comparator 54 at a data input and periodic pulse Min_off at a clock input, and is arranged such that the flip-flop is ‘set’ and toggles an output signal referred to as ‘skip’ to an ‘on’ state if output 56 indicates that I DETECT — VALLEY >I C at the time that periodic pulse Min_off pulses. Similarly, the flip-flop is reset and toggles the ‘skip’ signal ‘off’ if output 56 indicates that I DETECT — VALLEY <I C at the time that periodic pulse Min_off pulses. The flip-flop would typically operate on the rising edge of the Min_off pulse, though in some implementations the flip-flop output might be toggled on a falling edge. In the exemplary embodiment shown in FIG. 3 , ‘skip’ is taken at the ‘Q’ output of D flip-flop 68 , which goes high when the flip-flop is set. Note, however, that ‘skip’ might alternatively have the opposite polarity, depending on the specific circuit arrangement used.

The converter preferably also includes an SR latch 70 . Oscillator 66 also provides a periodic clock signal Clk_shot, which is applied to the SET input of latch 70 . A logic gate such as an OR gate 72 is then connected to receive the output 52 of first current comparator 50 at a first input (preferably via an AND gate 73 , discussed below) and the ‘skip’ output of flip-flop 68 at a second input, with the output of OR gate 72 coupled to the RESET input of SR latch 70 .

During ‘normal’ operation, ‘skip’ is low, and thus the output 52 of first current comparator 50 determines when SR latch 70 is reset. When I DETECT — PEAK >I C , output 52 goes ‘high’; the logic ‘high’ is passed through OR gate 72 and resets the SR latch. The output of SR latch 70 is a pulse-width modulated (PWM) signal 74 ; a gate driver circuit 76 receives PWM signal 74 and generates PWM switching signals 44 , 46 derived from PWM signal 74 .

However, if the output 56 of second current comparator 54 indicates that I DETECT — VALLEY is greater than I C at the time that periodic pulse Min_off pulses, indicating that the inductor current may be nearing an excessive level, ‘skip’ goes ‘high’ and skip mode is initiated. This ‘high’ passes through OR gate 72 and is applied to the RESET input of SR latch 70 . As long as ‘skip’ is high, the output of latch 70 will remain ‘low’, such that PWM signal 74 and switching signals 44 , 46 stop toggling regardless of the output 52 of first current comparator 50 . In this way, PWM pulses that would otherwise be applied to high and low side switching elements 40 , 42 are adaptively ‘skipped’.

The converter continues to operate in skip mode until such time that I DETECT — VALLEY is again below I C at the time that periodic pulse Min_off pulses. This causes ‘skip’ to fall, which returns control of SR latch 70 to the output 52 of current comparator 50 , thus resuming ‘normal’ operation.

Oscillator 66 may be further arranged to produce a periodic pulse Min_on, the rising edge of which is preferably aligned with the rising edge of periodic clock signal Clk_shot. The Min-on signal is arranged to ensure that high side switching element 40 is turned on for a minimum amount of time during each switching cycle (unless the converter is in skip mode). As noted above, this “minimum on-time” (also known as “blanking time”) is employed to prevent noise generated by an ‘off’ to ‘on’ transition of high side switching element 40 from corrupting the sensing of the inductor current. To accommodate the Min_on signal, the converter might further include an AND gate 73 which receives the output 52 of current comparator 50 at a first input and the inverse of the Min_on signal at a second input (via an inverter 81 if needed), with the output 82 of the AND gate applied to the first input of OR gate 72 . In this way, the Min-on pulse prevents a reset signal from being applied to the RESET input of SR latch 70 until the Min_on pulse falls. The falling edge of the Min_off pulse is preferably aligned with the rising edge of the Min_on pulse.

The operation of the converter shown in FIG. 3 is illustrated with the timing diagram shown in FIG. 4 , which shows the Clk_shot, Min_on, Min_off, I C and ‘skip’ signals described above. Also shown is a signal which represents the detected (sensed) inductor current; this signal is essentially the sum of both the I DETECT — PEAK and I DETECT — VALLEY signals. When the detected inductor current exceeds I C and the Min_off pulse occurs ( 90 ), the ‘skip’ signal is set to ‘on’ and skip mode is initiated. This results in subsequent PWM signals being skipped, causing I C to start to fall. When the detected inductor current falls back below I C and the Min_off pulse occurs ( 92 ), the ‘skip’ signal is reset to ‘off’, thereby allowing PWM signals to be sent to switching elements 40 , 42 and ‘normal’ operation to resume.

An example of the reduction in inductor current runaway when using the present system and method is illustrated in FIG. 5 . Inductor current I L is well-controlled at start-up, with the initial spike being <0.25 A while driving a heavy load—much less than the nearly 4 A spike shown in FIG. 2 for the prior art method. Output voltage Vout also increases smoothly using the present method.

Another possible embodiment of a current mode switching converter which implements the present ‘skip mode’ method is shown in FIG. 6 . This embodiment is similar to that shown in FIG. 3 , except that the I DETECT — PEAK and I DETECT — VALLEY signals are converted to voltages V DETECT — PEAK and V DETECT — VALLEY by current-to-voltage (I-to-V) converters 100 and 102 , respectively. This allows current comparators 50 and 54 in FIG. 3 to be replaced by voltage comparators 104 and 106 in FIG. 6 . In addition, V-to-I converter 62 can be eliminated, and V COMP can be summed with a slope compensation voltage V RAMP to produce a voltage V C instead of summing I COMP and I RAMP to produce I C as in FIG. 3 . Operation of this embodiment would be similar to that of the FIG. 3 embodiment.

The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.