Compensation scheme to improve the stability of the operational amplifiers

This invention pertains generally to the field of operational amplifiers and, more particularly, to improving the stability of circuits using operational amplifiers.

Operational amplifiers (op-amps) are key analog blocks used in various high accuracy and high performance applications, such as cell phones, digital cameras, and MP3 players, to name a few. Op-amps also find use in memory products, such as flash memory, where unlike other applications memory analog design uses op-amps in both high voltage and low voltage domains. An important design challenge in these applications is the stability of the amplifiers across process and temperature. A number of prior art circuits have looked to improve the stability of these amplifiers; however, there is still an on-going need for the improvement of such circuit elements.

According to a first set of general aspects, a voltage supply circuit includes an output transistor connected between a supply level and an output node of the voltage supply circuit and an operational amplifier having a first input connected to a reference level and a second input connected to receive feedback derived from the level on the output node of the voltage supply circuit. A first transistor is connected between the supply level and ground and having a gate connected to the output of the operational amplifier, where the first transistor is connected through a resistor to the first supply level and the gate of the output transistor is connected to a node between the resistor and the first transistor. A capacitance and a second transistor are connected in series between the output of the operational amplifier and the node between the resistor and the first transistor, where the gate of the second transistor is connected to receive a first voltage level. A bias circuit having first and second legs provides the first voltage level. The first leg has a current bias dependent upon the current at the output node of the voltage supply circuit. The second leg uses the bias level of the first leg and has one or more diode connected transistors connected in series though which the current of the second leg runs to ground, where the first voltage level is taken from a node of the second leg above the one or more diode connected transistors.

Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, whose description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

FIG. 1 is an example of an op-amp circuit using a transistor to cancel the RHP zero.

FIG. 2 is an example of an op-amp circuit using a resistor to cancel the RHP zero.

FIGS. 3 and 4 illustrate an exemplary embodiment of a regulator circuit providing improved stability of the op-amp.

The following looks at techniques for improving the stability of op-amps used in memory products by using a transistor-based compensation scheme to cancel the right-half plane (RHP) zero. Also, a simple biasing scheme is proposed to reduce the variation of phase margin across process and temperature.

Considering some alternate approaches to this problem first, one approach is to use source-follower feedback to eliminate right-half plane (RHP) zero; although this can remove the feed-forward current, it limits the output voltage headroom. Another approach is using a current-buffer compensation to cancel the RHP zero, which, while removing the feed-forward current, does not track well with process and temperature variations. Yet another approach is to use a nulling resistor to cancel the RHP zero: although simple, this approach also does not track well with process and temperature variations. In another alternative, a transistor operated in the triode region is used as a nulling resistor, which is also simple and does track well with process and temperature variations.

FIG. 1 looks at the last of these approaches, namely using a transistor to cancel the RHP zero, in more detail. In FIG. 1 , an output node VOUT for the circuit is connected to a load represented by R LOAD 141 and C LOAD 143 and is supplied by the transistor M 2 103 . The transistor M 2 103 is connected between a supply level of VPUMP 12 and, through a divider, to ground. In applications such as on memory devices, as indicated by its labeling the supply level VPUMP 12 can be a fairly high voltage, say 12V, as supplied from a charge pump. Here the divider is a resistor R F1 107 in parallel with a capacitor C F1 109 that are both in series with another resistor R F2 111 , but other arrangements can be used. An op-amp A 101 has it inputs connected to receive a reference level VREF and feedback PMON from the output level, here taken from the node between R F1 107 and R F2 111 , and provides an output NDRVI. NDRVI is connected to the control gate of transistor M 1 105 that is connected between ground and, through a current source transistor 113 , to the supply level. The current source transistor 113 is controlled by a level V BIAS to provide a current I BIAS . The node GATE between M 1 105 and current source transistor 113 is then connected to the gate of the supply transistor M 2 103 .

In FIG. 1 , a transistor M Z 117 is introduce to cancel the RHP zero, where this is connected in series with the capacitance C Z 115 between the node GATE controlling the supply transistor M 2 103 and the output NDRVI of the op-amp 101 . The transistor M Z 103 operates in the triode region to provide an equivalent resistance. The I BIAS is generated from the current source transistor 113 is mirrored to the bias circuit to give a V B generation to bias M Z 103 . The biasing circuitry for generating V B is formed of another current source transistor 121 connected in series with a pair of diode connected transistors 123 and 125 between a supply level VX 2 and ground. The gate of 121 is connected to the same level as the gate of 113 and the level V B is then taken from a node between 121 and the upper diode 123 ,

Although the circuit of FIG. 1 can provide cancellation for the right-half plane (RHP) zero, it has some shortcomings. An important one of these has to do with the applications, in which such circuits are used, specifically in applications such as in flash memory where the supply level VPUMP 12 can be 10V or more, placing a large amount of stress across the current source transistor 113 . Because of this, the device 113 , and consequently the circuit as a whole, will not have level performance over time as the transistor will break down over time.

To get around this problem, an arrangement such as in FIG. 2 can be used. In FIG. 2 , many of the elements are the same as in FIG. 1 and similarly numbered (i.e., M 2 is 103 in FIG. 1 and 203 in FIG. 2 ). To avoid the electronic design rule (EDR) concerns of FIG. 1 , I BIAS is generated in FIG. 2 using a resistor R BIAS 213 instead of the transistor 113 . Although R BIAS 213 can handle the higher supply voltages, this does not allow for I BIAS to mirrored as in FIG. 1 and be used to generate a control gate voltage for M Z 217 . FIG. 2 instead uses R Z 217 to cancel the RHP zero; and although this provides for a reactively simple implementation that can take the high supply levels, it also has some undesirable features. One of these concerns phase margin variations. These occur due to feed-forward zero movement as R Z 217 and g M1 , the gain of M 1 205 , change due to process and temperature variations, so that different output levels change g M1 and, hence, the zero location. To counteract this and ensure stability, the bandwidth of the amplifier may need to be reduced by design.

FIGS. 3 and 4 illustrate an exemplary embodiment for overcoming the sort of problems found in the circuits of FIGS. 1 and 2 , where corresponding elements in FIG. 3 are again numbered similarly to those in FIGS. 1 and 2 . As in FIG. 1 , the resistance R Z is implemented by a transistor M Z 317 . This has the advantages that M Z 317 tracks the process variations of M 1 305 to achieve better stability, so that bandwidth reduction to ensure stability is not required. So that the circuit can also deal well with high supply voltage levels, FIG. 3 retains a resistor R BIAS 313 above M 1 305 . Although use of the R BIAS 313 above M 1 305 solves the breakdown problems of the current source transistor 113 in FIG. 1 , this means that another way is need to generate the gate voltage V B for M Z 317 as this previous current source is not available.

FIG. 4 is an exemplary embodiment for a circuit to generate V B using a local bias circuit. I BIAS is generated by using a mirroring arrangement to equal the voltage at the source node of M Z 317 . On the left leg of FIG. 4 , a diode connected PFET 351 is in series with the transistor 353 is connected between the supply level VX 2 and ground. The gate of transistor 353 is connected to take the output NDRVI of the op-amp A 303 , generating the current level I BIAS . This current is then used to generate I BIAS in the right leg through the PFET 361 whose gate is connected to that of 351 . The current then flows through the diode connected transistors 363 and 365 to ground. The level V B0 , above 365 will be ≈NDRVI, the output of the op-amp 303 . A level-shift of V TH is achieved using the diode 363 is then used to generate V B for the gate of M Z 317 .

The voltage supply level for the supply circuit of FIG. 3 , VPUMP 12 , is a high voltage supply generated from a charge pump. As noted above, it can be 10V or more. In the exemplary embodiment, VPUMP 12 is around 12V and is used to provide bias voltages during READ and PROGRAM operations. The bias circuit section of FIG. 4 uses a lower level, VX 2 . VX 2 is generated from a pump and is around 4V and can be used as a power supply for many level shifters, which convert signals from low voltage (<4V) to high voltage domains (≧4V). Also, VX 2 can be used to bias switches that provide EDR protection for low voltage circuit blocks.

Note that under the arrangement of FIGS. 3 and 4 , the level V B on the right leg of FIG. 4 will depend on the output level NDRVI of the op-amp 303 being used in the right leg and, consequently, through the feedback level PMON on the output level V OUT of the circuit. Because of this arrangement, level on the gate of M Z 317 will track changes in the level of the load, here represented by R LOAD 341 and C LOAD 343 , and variations in the feedback divider circuit providing PMON.

Consequently, the exemplary embodiment of FIGS. 3 and 4 can provide an improved compensation scheme to cancel the right-half plane (RHP) zero that can used over a wide range of supply levels. Although the additional elements increase power consumption slightly (a few tens of μW for a typical implementation), the described scheme reduces variations in phase margin across process and temperature corners (over a 50% reduction in the variation of phase margin relative to the embodiment of FIG. 2 for a typical implementation). As such, it has the advantages of improving the stability of the amplifiers and enhancing their overall performance and accuracy, as well as improving the overall bandwidth of operation without a trade-off requirement for stability.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.