Current mirror with low headroom and linear response

This application is a divisional of and claims priority to U.S. patent application Ser. No. 13/042,057 to Sandro Herrera, filed Mar. 7, 2011, which is a divisional of U.S. patent application Ser. No. 12/255,326, filed Oct. 21, 2008, entitled “Current Mirror With Low Headroom And Linear Response,” both of which are herein incorporated by reference in their entireties.

The present invention relates to a current mirror circuit that provides linear output with low headroom requirements.

Current mirrors are well known but they suffer from known disadvantages. Two basic current mirrors are shown in FIGS. 1 and 2 . The current mirror of FIG. 1 is called a diode current mirror. It includes a pair of transistors Q 1 and Q 2 in which the input transistor Q 1 is connected as a diode. The base and collector of Q 1 are connected to the base of Q 2 . The input current signal is fed at an input node N 1.1 which creates an input potential drop of V 1.1 =V BE1 +V RE1 . The base-to-emitter voltages of each transistor Q 1 , Q 2 (V BE1 and V BE2 ) vary together with the input current signal; thus, V BE non-linearities tend to cancel out. The input current I IN generates a corresponding output current I OUT at the same level. Although the diode current mirror provides an output current that has a linear response to a changing input current (I IN =I IN (t)), it imposes an input headroom requirement of V BE1 +V RE1 . In practice, this can be as high as 1V.

The current mirror of FIG. 2 is called an emitter follower mirror. The circuit also includes a pair of transistors Q 1 , Q 2 . This circuit requires a bias current (I BIAS ) provided at node N 2.2 . The input current I IN is fed directly to the resistor RE 1 , creating a voltage at the input terminal of V 2.1 =I IN *R (assume RE 1 =RE 2 =R). At node N 2.2 , the input and bias currents create a voltage V 2.2 =V IN +V BE1 . At the emitter of Q 2 , the current mirror generates a voltage V 2.3 =V IN +V BE1 −V BE2 , which results in an output current of I OUT =V 2.3 /R=1/R*(I IN *R+V BE1 −V BE2 ) if base current errors are ignored. In all known emitter follower mirrors, the bias current I BIAS is provided as a constant current.

The emitter follower mirror possesses a disadvantage because I OUT varies non-linearly with I IN . The input current to the mirror I IN is a time varying signal (I IN =I IN (t)), which causes V BE2 to vary over time (V BE2 =V BE2 (t)). V BE1 does not vary, due to the constant bias current I BIAS . This configuration generates an output current as follows:

I OUT =V 2.3 /R= 1 /R *( I IN *R+V BE1 −V BE2 ( t ))

Although the V BE1 −V BE2 term in I OUT ideally would cancel out, it does not over most conditions. This leads to the non-linear response of the emitter follower mirror.

By way of example, consider a use case in which the input current I IN doubles over time. The voltage at node N 2.1 will double, and the voltage across RE 2 will roughly double. As a result, the output current will roughly double which causes a change in V BE2 of about 18 mv. Since I BIAS does not change, V BE1 will not change. This behavior would induce an error in the output current I OUT of about 18 mv/RE 2 =18 mV/R.

There is no known current mirror circuit that provides a linear output while requiring low input headroom requirements for the input current signal.

FIG. 1 is a circuit diagram of a known current mirror.

FIG. 2 is a circuit diagram of another known current mirror.

FIG. 3 is a circuit diagram of a current mirror according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of another current mirror according to an embodiment of the present invention.

FIG. 5 is a diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 7 is a diagram of a differential amplifier according to an embodiment of the present invention.

FIG. 8 is a circuit diagram of a differential amplifier according to an embodiment of the present invention.

The disadvantages of the prior art are overcome by a current mirror circuit that provides a low headroom input requirement and provides a linear output current. The current mirror is configured as an emitter follower mirror that accepts a first input current signal I IN (t) at an input and also receives a replica of I IN (t) used as a bias current. The replica bias current provides a linear output response of the proposed current mirror.

FIG. 3 is a circuit diagram of a current mirror 300 according to an embodiment of the present invention. The current mirror 300 may include a pair of transistors Q 1 , Q 2 and a pair of resistors RE 1 , RE 2 . A first transistor Q 1 is coupled to an input current source I IN1 (t) at its base which also is connected to the first resistor RE 1 . An emitter of the first transistor Q 1 may be coupled to a replica of the input current I IN2 (t).

A base of the second transistor Q 2 also may be connected to the replica input current I IN2 (t). An emitter of the second transistor Q 2 may be coupled to the second resistor RE 2 . A collector of the second transistor Q 2 may be coupled to an output terminal of the current mirror. The first and second resistors RE 1 , RE 2 and a collector of the first transistor Q 1 may be connected to a common node, commonly ground or a power rail.

The current mirror 300 of FIG. 3 uses the replica input current I IN2 (t) as a bias current to the first transistor Q 1 . During operation, the input current I IN1 (t) generates a voltage at node N 3.1 as V 3.3 =I IN1 (t)*RE 1 . The input headroom limitation is the voltage drop across resistor RE 1 which is much lower than the limitations incurred by the current mirror of FIG. 1 . The voltage at node N 3.2 is I IN1 (t)*RE 1 +V BE1 . Finally, the voltage at node N 3.3 is I IN1 (t)*RE 1 +V BE1 −V BE2 . Because the bias current I IN2 (t) to this circuit is a replica of the input current I IN1 (t), the base-to-emitter voltages of transistors Q 1 and Q 2 will be equal and will vary together, therefore, cancel each other. Thus, the current mirror achieves linear operation.

The circuit of FIG. 3 finds application in complementary circuits in which it is common to generate input current pairs, in which one current comes from a source and a complementary current comes from a sink. To accommodate this circuit in such designs, the circuit also may include a secondary mirror that is responsive to a sinking input current I IN3 (t), which is equal in magnitude to I IN1 (t), in this case a sourcing input current. This secondary mirror generates an output current in the same direction as I IN1 (t). Thus, in this embodiment, current I IN3 (t) generates a second current, I IN2 (t), which is equal to and in the same direction as I IN1 (t) and the second current I IN2 (t) may be input to the primary current mirror of FIG. 3 as a bias current to Q 1 .

FIG. 4 illustrates a current mirror system according to another embodiment of the present invention. This embodiment finds application in a complementary system where complementary input currents I IN1 (t) and I IN2 (t) are available. The circuit may include three or, optionally, four copies of the current mirror of FIG. 3 .

A first mirror, shown as mirror 1 , may include a first pair of transistors Q 1 , Q 2 and a first pair of resistors RE 1 , RE 2 configured as described in FIG. 3 . Input current I IN1 (t) is the input to the mirror. A bias current I BIAS1 (t) is input to the mirror at node N 4.2 . Mirror 1 may generate an output current I OUT1.1 (t).

A second mirror, shown as mirror 2 , may include a pair of transistors Q 1 , Q 3 and a pair of resistors RE 1 , RE 3 . Transistor Q 1 and resistor RE 1 are shared among mirrors 1 and 2 . Mirror 2 accepts an input current I IN1 (t) and a bias current I BIAS1 (t), which are shared among mirrors 1 and 2 . Mirror 2 may generate an output current I OUT1.2 (t).

A third mirror, shown as mirror 3 , may include a pair of transistor Q 4 and Q 6 and a pair of resistors RE 4 , RE 6 . Input current I IN2 (t) is input to the mirror, which is sink version of I IN1 (t). A bias current I BIAS2 (t) may be input to the mirror at node N 4.6 . Mirror 3 may generate an output current I OUT2.1 (t).

A fourth mirror, which is optional, may include transistors Q 4 , Q 5 and resistors RE 4 , RE 5 . Transistor Q 4 and resistor RE 4 may be shared among mirrors 3 and 4 . Input current I IN2 (t) and bias current I BIAS2 (t) are shared among mirrors 3 and 4 . Mirror 4 may generate an output current I OUT2.2 (t).

In the circuit of FIG. 4 , mirror 1 may receive an output current from mirror 3 as a bias current (I OUT2.1 (t) becomes I BIAS1 (t)). This maintains linear operation on mirror 1 , ensuring I OUT1.1 (t)=I IN1 (t). The response of mirror 3 will be kept linear if mirror 3 receives a bias current which also matches the input current. Mirror 3 receives an output current from mirror 2 as a bias current (I OUT1.2 (t) becomes I BIAS2 (t). This maintains linear operation on mirror 3 , ensuring I OUT2.1 (t)=I IN2 (t). Thus, mirrors 2 and 3 keep each other in balance. They receive the output currents of their counterpart mirror as bias currents and, since these are equal to the input current, a linear response is ensured over the mirror system 400 as a whole.

The current mirror of FIG. 3 finds application in a variety of circuit systems. FIG. 5 illustrates application of the current mirror in an operational amplifier (op amp), according to an embodiment of the present invention. FIG. 5( a ) illustrates an op amp symbolically. An op amp is a known circuit that generates an output voltage based on a difference between two input voltages V P , V N as V OUT =A*(V P −V N ), where A is a gain factor provided by the op amp.

FIG. 5( b ) provides a block diagram for a single stage operational amplifier. In this model, a transconductance cell G M 500 generates a current I OUT1 in response to a difference between the input voltages (I OUT1 =G M *(V P −V N )). Signal current mirrors 510 generate an output current I OUT2 corresponding to the current received from the transconductance cell G M 500 . The I OUT2 current is passed through a large impedance Z, which creates a voltage G M *Z*(V P −V N ). Another amplifier buffer 530 is shown (with a gain of 1) which generates the output voltage V OUT =G M *Z*(V P −V N ), where the op amp gain A=G M *Z.

FIG. 5( c ) illustrates application of the current mirror to an op amp input stage. A complementary transconductance cell G M 500 generates currents in response to a difference among inputs V P and V N . These transconductance stages 500 are well known; typically, they generate two pairs of differential output currents each having magnitude I OUT /2. A pair of the current mirrors shown in FIG. 3 can be used as mirrors 510 . 1 , 510 . 2 . In response to the respective currents I OUT /2, the current mirrors 510 . 1 , 510 . 2 may generate corresponding currents I OUT /2 on their outputs, which are summed at an output node to generate I OUT . The output current I OUT of FIG. 5( c ) can be used as current I OUT2 of FIG. 5( b ).

The second current pair 540 . 1 , 540 . 2 from the transconductance stage 500 can be shunted to the supply rails of the system (not shown). Alternatively, the second current pair 540 . 1 , 540 . 2 may be input respectively to the current mirrors 510 , 520 as sources for the bias current (shown as I BIAS , in phantom).

FIG. 6 illustrates a circuit diagram of the model shown in FIG. 5( c ) according to an embodiment of the present invention. The circuit 600 of FIG. 6 may include six current mirrors. Mirrors 1 , 2 generate the main output currents for the stage. Mirrors 3 and 4 generate bias currents for use by mirrors 1 and 2 (also mirrors 5 and 6 ). Mirrors 5 and 6 generate bias currents for use by mirrors 3 and 4 . FIG. 6 identifies the bias currents input to each mirror and the transistors that generate them.

FIG. 7 illustrates application of the current mirror in a differential amplifier (diff amp), according to an embodiment of the present invention. FIG. 7( a ) illustrates a differential amplifier symbolically. A differential amplifier is a known circuit that generates a pair of output voltages V OUT+ , V OUT− based on a difference between two input voltages V P , V N (V OUT+ −V OUT− =A*(V P −V N )). The value A is a gain factor provided by the amplifier, which is quite large.

FIG. 7( b ) provides a block diagram for a single stage differential amplifier. In this model, a transconductance cell G M 700 generates differential output currents I OUT1+ , I OUT1− in response to a difference between the input voltages (I OUT1+ −I OUT1− =G M *(V P −V N )). Signal current mirrors 710 may generate output currents I OUT2+ , I OUT2− corresponding to the currents received from the transconductance cell G M 700 . The I OUT2+ , I OUT2− current may pass through impedance blocks 720 . 1 , 720 . 2 which create corresponding output voltages having magnitude G M *Z*(V P −V N ). Another amplifier buffers 730 . 1 , 730 . 2 may generate output voltages V OUT+ =−V OUT− =G M *Z*(V P −V N ).

FIG. 7( c ) illustrates application of the current mirror to a diff amp input stage. A complementary transconductance cell G M 700 may generate two pairs of currents each having magnitude I OUT /2 in response to a difference among inputs V P and V N . In the diff amp system, the current mirrors shown in FIG. 3 can be provided as mirrors 710 . 1 - 710 . 4 . In response to the respective currents I OUT /2, the current mirrors 710 . 1 - 710 . 4 each may generate corresponding currents I OUT /2. A first pair of output currents may be summed at an output node to generate a first output current I OUT+ and a second pair of output currents, which are oriented opposite to the orientation of the first pair of currents, may be summed to generate the second output current I OUT− . The output currents I OUT+ , I OUT− of FIG. 7( c ) can be used as currents I OUT2+ , I OUT2− of FIG. 7( b ).

FIG. 8 illustrates a circuit diagram of the differential amplifier case, in which there are eight current mirrors. Mirrors 1 - 4 generate the main output currents. Four other mirrors (which are not labeled to retain clarity in the figure) generate bias currents for mirrors 1 - 4 . FIG. 8 identifies the bias currents input to each mirror and the transistors that generates them.

Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.