Apparatus and method for controlling inductor current in a switch mode power supply

The present application claims priority to U.S. Provisional Patent Application No. 61/715,083, filed on Oct. 17, 2012 which is hereby incorporated herein by reference in its entirety.

A switch-mode power supply (SMPS) is an electronic circuit that converts an input direct current (DC) supply voltage into one or more DC output voltages that are higher or lower in magnitude than the input DC supply voltage. An SMPS that generates an output voltage lower than the input voltage is termed a buck or step-down converter. An SMPS that generates an output voltage higher than the input voltage is termed a boost or step-up converter.

A typical SMPS includes a switch for alternately opening and closing a current path through an inductor in response to a switching signal. In operation, a DC voltage is applied across the inductor. Electrical energy is transferred to a load connected to the inductor by alternately opening and closing the switch as a function of the switching signal. The amount of electrical energy transferred to the load is a function of the duty cycle of the switch and the frequency of the switching signal. Switch-mode power supplies are widely used to power electronic devices, particularly battery-powered devices, such as portable cellular phones, laptop computers, and other electronic systems in which efficient use of power is desirable.

Apparatus and method for controlling inductor current in a switch mode power supply are disclosed herein. In one embodiment, a switch mode power supply includes an inductor, a high-side switch coupled to the inductor, a low-side switch coupled to the inductor, and a controller. The controller is coupled to at least one of the high-side switch and the low-side switch. The controller includes a first capacitor and a current source. The controller is configured to control timing of current switching to the inductor by enabling current flow through the at least one of the high-side switch and the low-side switch based on time to charge the first capacitor via the current source. The time is a function of voltage across the inductor.

In another embodiment, a controller for a switch mode power supply includes a current source; and switch timing circuitry. The switch timing circuitry is configured to control the switch timing of at least one of a high side transistor and a low side transistor that switch current in an inductor of the switch mode power supply. The timing circuitry includes a first charging node and transistor driver circuitry. The transistor driver circuitry is coupled to the current source. The transistor driver circuitry is configured to generate the timing based on time to change, via a current provided by the current source, a voltage at the charging node between voltages that are proportional to an input voltage of the inductor and an output voltage of the inductor. The timing provides at least one of a peak current in the inductor and a prediction of current zero crossing in the inductor.

In a further embodiment, a method for controlling current in an inductor of a switch mode power supply includes charging a first capacitor from a first voltage to a second voltage. The first and second voltages are proportional to the voltages at one of an input and an output of the inductor. One of a high side switch and a low side switch coupled to the inductor is enabled for the duration of the charging. At least one of peak current in the inductor and a prediction of current zero crossing in the inductor is provided based on the duration of the charging.

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a schematic diagram of a switch mode power supply arranged as a buck converter in accordance with various embodiments;

FIG. 2 shows a schematic diagram of a peak current controller for controlling peak current in an inductor of a switch mode power supply arranged as a buck converter in accordance with various embodiments;

FIG. 3 shows a schematic diagram of a switch mode power supply arranged as a boost converter in accordance with various embodiments;

FIG. 4 shows a schematic diagram of a peak current controller for controlling peak current in an inductor of a switch mode power supply arranged as a boost converter in accordance with various embodiments; and

FIG. 5 shows a flow diagram for a method for controlling peak current in a switch mode power supply in accordance with various embodiments.

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be based on Y and any number of other factors.

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

In a switch mode power supply (SMPS), such as a buck converter, current in the inductor of the SMPS is driven to a peak value every cycle. The peak current determines the amount of energy that is transferred each cycle, and is therefore important to the efficiency of the SMPS. Setting the peak current high increases conduction losses, while setting the peak current low increases switching loss. Consequently, controlling peak current in the inductor is important for optimizing SMPS performance.

Conventional SMPS designs attempt to determine the current in the inductor by measuring the voltage drop across a switching transistor through which current is provided to the inductor. The measured voltage drop across the transistor is compared to a predetermined threshold value. When the voltage drop exceeds the threshold value, the peak current is assumed to have been reached and the flow of current through the transistor is disabled. Unfortunately, controlling peak inductor current in this manner is subject to various errors. For example, minute variations in resistance across switching transistors can result in substantial inaccuracies (e.g., ±50%) in peak current determination.

Embodiments of the present disclosure provide accurate control of peak current in the inductor of an SMPS without requiring switching transistor voltage drop measurements. Thus, embodiments are not subject to errors in peak current determination induced by transistor variations as in conventional SMPS architectures. Embodiment of the SMPS disclosed herein control the switching times of transistors driving the inductor, and in turn control the peak current in the inductor, as a function of input and output voltages of the inductor corresponding to peak inductor current.

FIG. 1 shows a schematic diagram of an SMPS 100 arranged as a buck converter in accordance with various embodiments. The SMPS 100 includes an inductor L 1 coupled on one side to a capacitor C L1 and a load 114 , and coupled on the other side to drive transistors S H1 and S L1 . Transistor S H1 is a high side switch that when closed connects the inductor L 1 to voltage V i causing current to rise in the inductor L 1 . Transistor S L1 is a low side switch that when closed connects the inductor L 1 to ground.

The timing of transistor S H1 and S L1 activation and deactivation is controlled by a peak current controller 102 . Assertion of high side switch control signal 116 by the peak current controller 102 , buffered by the buffer 104 , activates transistor S H1 . Negation of high side switch control signal 116 by the peak current controller 102 , sets flip/flop 110 , after delay 108 . The output of flip/flop 110 , buffered by buffer 106 , activates transistor S L1 . Comparator 112 resets flip/flop 110 based on the voltage at the input side of the inductor L 1 .

For the SMPS 100 , the peak current in the inductor L 1 is a function of the time that the switch S H1 is closed. The voltage across the inductor L 1 may be expressed as a function of inductance, current, and time:

V = L ⁢ ⅆ i ⅆ t ( 1 )

Correspondingly, when the voltage drop across the high-side switch S H1 is small, the relationship of the peak current in the inductor L 1 to the switch S H1 active (i.e., closed) time may be expressed as:

T H ⁢ ⁢ 1 = LI P ( V i - V O ) ( 2 ) I P = T H ⁢ ⁢ 1 ⁡ ( V i - V O ) L ( 3 )

where:

I P is the peak current in the inductor L 1 ; L is the inductance of the inductor L 1 ; V i is the voltage at the input side of the inductor L 1 (i.e., the voltage sourced through the high side switch S H1 . V O is the voltage at the output side of the inductor L 1 ; and T H1 is the time during which the high side switch S H1 is closed.

In accordance with the above, embodiments of the peak current controller 102 , control the peak current in the inductor L 1 by generating high side switch activation timing T H1 that is inversely proportional to V i −V O . FIG. 2 shows a schematic diagram of the peak current controller 102 in accordance with various embodiments. The peak current controller 102 includes a current source 202 , a switch timing generator 204 , and initialization circuitry 210 . The current source 202 generates a current that is proportional to V i −V O . The current source includes transistors S 21 and S 22 , and resistor R 21 . The gate of transistor S 21 is coupled to the resistor R 21 and to the drain of transistor S 21 . The source of transistor S 21 is coupled to V O , the voltage at the output of the inductor L 1 . The value of resistor R 21 is large (e.g., in the range of mega-ohms), causing node 212 to settle at a voltage of V O −V T , where V T is the threshold voltage of transistor S 21 . The drain of transistor S 21 is coupled to the gate of transistor S 22 . The source of transistor S 22 is coupled to V i , the voltage provided at the input side of inductor L 1 when switch S H1 is closed. Consequently, the gate-source voltage at transistor S 22 is V i −V O +V T , which in accordance with the metal oxide semiconductor (MOS) current equation:

I=K ( V gs −V t ) 2   (4)

produces current through transistor S 22 of:

I=K ( V i −V O ) 2 .  (5)

Thus, the current source 202 generates a current that is proportional to the square of the difference of voltages at the input side and output side of the inductor L 1 (V i −V O ).

The switch timing generator 204 is coupled to the current source 202 , and applies the current provided by the current source 202 to generate a high side switch timing signal 116 that is inversely proportional to V i −V O . The switch timing circuitry 204 includes a capacitor C 1 , a switching transistor S 23 , a comparator 206 , and a flip/flop 208 . The capacitor 208 forms charging node that is charged to

V O 2

by the initialization circuit 210 . When the flip/flop 208 is set by transition of signal EN, the switch S 23 is closed and current provided by the current source 202 flows through the switch S 23 to charge the capacitor C 1 . When the voltage across the capacitor C 1 increases from

V O 2 ⁢ ⁢ to ⁢ ⁢ V i 2

the comparator 206 resets the flip/flop 208 and the switch C 23 is opened. The signal 116 is provided to the high side switch S H1 via the buffer 104 as shown in FIG. 1 .

The current provided to the capacitor C 1 , may be expressed as:

I = C ⁢ ⅆ V ⅆ t , ( 6 )

and the charging time may be expressed as:

T = C ⁡ ( V i - V O ) I ( 7 )

Because the current (I) provided by the current source 202 is proportional to (V i −V O ) 2 , the time for which the flip/flop 208 is set, and the time for which the high side switch S H1 is closed are proportional to

1 ( V i - V O ) .

As noted above, holding the high side switch S H1 active for a time inversely proportional to (V i −V O ) produces optimal peak current in the inductor L 1 . Thus, the peak current controller 102 produces peak current in the inductor L 1 .

When the flip/flop 208 is reset by the comparator 206 , the flip/flop 110 is set after delay 108 , and low side transistor S L1 is activated until flip/flop 110 is reset by comparator 112 . While the flip/flop 208 is reset, the capacitor C 1 is discharged to

V O 2 .

The initialization circuit 210 generates

V O 2 .

The initialization circuit 210 includes transistors S 24 and S 25 arranged as diodes to form a voltage divider producing

V O 2 . V O 2

is switched to the capacitor C 1 , via switch S 26 , while the flip/flop 208 is reset is to precharge the capacitor C 1 to

V O 2

in preparation for the next cycle of charging from

V O 2

to

V i 2 .

The initialization circuit may include buffers or other circuitry to isolate the transistors S 24 and S 25 from the switch timing generator 204 and inhibit alteration of the

V O 2

voltage generated by the initialization circuit 210 while precharging the capacitor C 1 .

The current control techniques explained above are also applicable to predicting a zero crossing of inductor current in boost converters. By providing zero crossing prediction, embodiments allow for fabrication of boost converters using lower voltage processes than would be required for zero crossing detection methods used in conventional boost converters. FIG. 3 shows a schematic diagram of an SMPS 300 arranged as a boost converter in accordance with various embodiments. The SMPS 300 includes an inductor L 2 , switching transistors SL 2 and SH 2 arranged as high side and low side switches respectively, capacitor CL 2 , load 312 , buffers 304 and 306 , and current controller 302 .

The current controller 302 closes the low side switch SL 2 to induce current flow through the inductor L 2 from input voltage source Vi. When low side switch SL 2 is open, the current controller 302 may close the high side switch SH 2 to charge the capacitor CL 2 to the boosted voltage present at the output of the inductor L 2 . The current controller 302 generates the signals 308 and 310 that control the timing of the switching transistors SL 2 and SH 2 such that the timing of inductor current zero crossing is predicted.

As per equation (1) above:

V = L ⁢ ⅆ i ⅆ t . ( 8 )

Accordingly, active time for the low side switch SL 2 is:

T L ⁢ ⁢ 2 = LI P V i , ( 9 )

and active time for the high side switch SH 2 is:

T H ⁢ ⁢ 2 = LI P ( V O - V i ) , ( 10 )

where:

I P is the peak current in the inductor L 2 ; L is the inductance of the inductor L 2 ; V i is the voltage at the input side of the inductor L 2 ; V O is the voltage at the output side of the inductor L 2 ; T L2 is the time during which the low side switch S L2 is closed; and T H2 is the time during which the high side switch S H2 is closed.

Thus, the relative active times of transistors SL 2 and SH 2 may be expressed as:

T L ⁢ ⁢ 2 T H ⁢ ⁢ 2 = ( V O - V i ) V i ( 11 )

Embodiments of the current controller 302 provide low side switch activation timing that is proportional to V O −V i , and high side switch activation timing that is proportional to V i to predict the current zero crossing in the inductor L 2 :

FIG. 4 shows a schematic diagram of the current controller 302 in accordance with various embodiments. The current controller 302 includes a low side timing generator 402 and a high side timing generator 404 . The low side timing generator 402 provides timing signal 308 that controls activation of the low side switch SL 2 . The high side timing generator 404 provides timing signal 310 that controls activation of the high side switch SH 2 .

The low side timing generator 402 includes a constant current source 416 , a switching transistor S 42 , a capacitor C 42 , a flop/flop 410 , a comparator 408 , and an initialization circuit 406 . The capacitor C 42 forms charging node that is precharged to

V i 2

by the initialization circuit 406 . When the flip/flop 410 is reset by a pulse from the pulse generator 418 , the switch S 42 is closed and constant current provided by the current source 416 charges the capacitor C 42 . When the voltage across the capacitor C 42 reaches

V O 2

the comparator 408 sets the flip/flop 410 . The signal 308 generated by the flip/flop 410 controls the low side switch S L2 via the buffer 304 as shown in FIG. 3 .

Because the capacitor C 42 is precharged to

V i 2 ,

and the current source 416 provides a constant current, the time to charge the capacitor C 42 from

V i 2

to

V O 2

is:

T = C I ⁢ ( V O - V i ) 2 . ( 12 )

Accordingly, the time that the low side switch S L2 is closed via signal 308 is proportional to V O −V i .

While the flip/flop 410 is set, the capacitor C 42 is discharged to

V i 2 .

The initialization circuit 406 generates

V i 2 .

The initialization circuit 406 includes transistors S 46 and S 48 arranged as diodes to form a voltage divider producing

V i 2 . ⁢ V i 2

is routed to the capacitor C 42 , via switch S 50 , while the flip/flop 410 is set to precharge the capacitor C 42 to

V i 2

in preparation for the next cycle of charging from

V i 2

to

V O 2 .

The initialization circuit 406 may include buffers or other circuitry to isolate the transistors S 46 and S 48 from the low side timing generator 402 and inhibit alteration of the

V i 2

voltage generated by the initialization circuit 406 while precharging the capacitor C 42 .

The high side timing generator 404 is coupled to the low side timing generator 402 , and triggered when flip/flop 410 of the high side timing generator is set and the low side switch SL 2 is deactivated. The high side timing generator 404 includes a constant current source 416 , a switching transistor S 44 , a capacitor C 44 , a flop/flop 414 , a comparator 412 , and an initialization switch S 52 . The current source 416 of the high side timing generator 404 produces a current equivalent to that produced by the current source 416 of the low side timing generator 402 . Because constant current need be provided to only one of the low side timing generator 402 and the high side timing generator 404 at a time, some embodiments of the current controller 302 may share an instance of the current source 416 between the timing generators 402 and 404 .

The capacitor C 44 forms charging node that is discharged to ground voltage by the initialization switch S 52 . When the flip/flop 414 is reset by a pulse from the pulse generator 420 , the switch S 44 is closed and constant current provided by the current source 416 charges the capacitor C 44 . When the voltage across the capacitor C 44 reaches

V i 2

the comparator 412 sets the flip/flop 414 . The signal 310 generated by the flip/flop 414 controls the high side switch S H2 via the buffer 306 as shown in FIG. 3 . While the flip/flop 414 is set, the initialization switch S 52 is closed to discharge the capacitor C 44 to ground voltage in preparation for the next cycle of charging from ground to

V

i

2

.

Because the capacitor C 44 is precharged to ground voltage, and the current source 416 provides a constant current, the time to charge the capacitor C 42 is proportional to V i . Thus, the low side timing generator 402 and the high side timing generator 404 conjunctively provide control timing for the switches S L2 and S H2 such the active time for the switches S L2 and S H2 is proportional to

FIG. 5 shows a flow diagram for a method 500 for controlling current in an inductor of an SMPS in accordance with various embodiments. The method 500 is applicable to controlling peak current in the inductor and/or to predicting a zero crossing of current in the inductor. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown.

In block 502 , a current is generated. The current may be proportional to V i −V O in some embodiments. For example, the current may be K(V i −V O ) 2 as generated by the current source 202 for use in buck converter timing generation. In some embodiments, the current may be a predetermined constant current.

In block 504 , a capacitor is precharged to a first voltage. For a buck converter, the capacitor may be precharged to

V O 2 .

For a boost converter, a first capacitor may be precharged to

V i 2 ,

and a second capacitor may be precharged to ground voltage.

In block 506 , the capacitor is charged from the first voltage to a second voltage via the current generated in block 502 . In a buck converter, the capacitor may be charged from

V o 2

to

V i 2 .

In a boost converter, the first capacitor may be charged from

V i 2

to

V 0 2 ,

and the second capacitor may subsequently be charged from ground voltage to

V

i

2

.

In block 508 , a switch coupled to an inductor of the SMPS is closed for the duration of capacitor charging performed in block 506 . In a buck converter, a high side switch is closed while charging the capacitor from

V o 2

to

V i 2 .

In a boost converter, a low side switch is closed while charging the first capacitor from

V i 2

to

V o 2 ,

and a high side switch is closed while charging the second capacitor from ground voltage to

V

i

2

.

In block 510 , when the capacitor has been charged from the first voltage to the second voltage, the switch controlled via the capacitor is opened. In the buck converter, the high side switch is opened when the charging raises the capacitor voltage to

V i 2 .

In the boost converter, the low side switch is opened when the charging raises first capacitor voltage from

V i 2

to

V o 2 ,

and the high side switch is opened when the charging raises the second capacitor voltage from ground voltage to

V

i

2

.

The above discussion is meant to be illustrative of the principles and various implementations of the present disclosure. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, various flip/flop signal polarities generated by the embodiments described herein may differ in other embodiments while producing equivalent switch control signals, the fractional portion of V i and V O may differ, etc. It is intended that the following claims be interpreted to embrace all such variations and modifications.