Control circuit, control method used in PFC circuit and power source system thereof

This application claims priority to Chinese Application Serial Number 201210284439.2, filed Aug. 6, 2012, which is herein incorporated by reference.

1. Field of Invention

The present invention relates to the technical field of power electronics. More particularly, the present invention relates to a control circuit, control method used in a PFC circuit and the power source system including the control circuit.

2. Description of Related Art

Currently, in order to reduce the serious harmonic pollution to a power grid caused by frequently-used power electronic devices, generally there is a need to introduce a power factor correction (PFC) circuit, so as to make the input current harmonic meet the requirements of a predetermined harmonic through the PFC circuit. Additionally, the development trend of the PFC circuit is towards the direction of high efficiency and high power density, just as most of the power source products.

Taking a bridgeless PFC circuit topology as an example, the circuit has many advantages, such as low conduction losses, low common-mode interfere and high utilization ratio of components. For example, the bridgeless PFC circuit includes a first bridge arm and a second bridge arm connected with each other in parallel. The first bridge arm is formed by a first MOSFET and a second MOSFET. The second bridge arm is formed by a first diode D 1 and a second diode D 2 .

When the second MOSFET is off and the first MOSFET is on in the first bridge arm, the inductor releases energy through the first MOSFET and a fourth MOSFET. Accordingly, the inductor current decreases. Afterwards, the inductor current decreases to zero at a certain moment and after the moment the direction of the current is reversed. When the first MOSFET is off, a voltage (V DS ) across two ends of the drain electrode and the source electrode of the second MOSFET starts to decrease. If the second MOSFET is controlled to be turned on when the voltage decreases to zero, it is realized to turn on the second MOSFET under a zero voltage, so as to reduce the switch loss. However, it is a subject for related technicians to solve which control mechanism is used to realize the above-mentioned turn-on under the zero voltage so as to reduce the switch loss of the circuit. Additionally, it is a task for designers to solve how the zero-crossing point of the inductor current is automatically detected in a simple and effective way.

For the above-mentioned defects of a bridgeless PFC circuit of the conventional art in terms of reducing the switch loss, the present invention provides a control circuit, control method used in a PFC circuit and the power source system including the control circuit.

According to a technical aspect of the present invention, a control circuit used in a PFC circuit is provided. The PFC circuit includes an inductor, a first bridge arm and a second bridge arm connected to the first bridge arm in parallel. The first bridge arm has a first switch and a second switch connected with each other in series. The common node of the first switch and the second switch is coupled to an input voltage through the inductor.

The control circuit includes a zero current detection circuit, a feedback circuit and a pulse distribution circuit. The zero current detection circuit includes a polarity detection circuit and a signal conversion circuit. The polarity detection circuit is used to receive an input voltage and output a first digital signal and a second digital signal indicating a polarity of the input voltage. A potential of the first digital signal is opposite to that of the second digital signal. The signal conversion circuit receives at least one inductive signal reflecting an inductive voltage of the inductor, the first digital signal and the second digital signal and generates an analog signal. The feedback circuit is used to receive the analog signal and a predetermined pulse signal and generate a driving pulse signal. The pulse distribution circuit is used to distribute the driving pulse signal to the first switch and the second switch of the first bridge arm according to the first digital signal and the second digital signal so that one of the first switch and the second switch performs an ON operation. After a switch cycle, one of the first switch and the second switch performs the ON operation for the next switch cycle when the current flowing through the inductor decreases to a predetermined threshold value, wherein an ON time of the first switch is equal in each switch cycle, and an ON time of the second switch is equal in each switch cycle.

According to another technical aspect of the present invention, a power source system is provided. The power source system includes a PFC circuit and a control circuit. The PFC circuit includes: a first bridge arm and a second bridge arm. The first bridge arm includes a first switch and a second switch connected with each other in series. The common node of the first switch and the second switch is coupled to one end of an input voltage through an inductor. The second bridge arm includes a third switch and a fourth switch connected with each other in series. The common node of the third switch and the fourth switch is coupled to the other end of the input voltage. The control circuit includes: a zero current detection circuit having a polarity detection circuit and a signal conversion circuit, a feedback circuit and a pulse distribution circuit. The polarity detection circuit is used to receive the input voltage and output a first digital signal and a second digital signal indicating the polarity of the input voltage. A potential of the first digital signal is opposite to that of the second digital signal. The signal conversion circuit receives at least one inductive signal reflecting an inductive voltage of the inductor, the first digital signal and the second digital signal and generates an analog signal. The feedback circuit is used to receive the analog signal and a predetermined pulse signal and generate a driving pulse signal. The pulse distribution circuit is used to distribute the driving pulse signal to the first switch and the second switch of the first bridge arm according to the first digital signal and the second digital signal, so that the first switch or the second switch performs an ON operation. After a switch cycle, one of the first switch and the second switch performs an ON operation for the next switch cycle when the current flowing through the inductor decreases to a predetermined threshold value, wherein an ON time of the first switch is equal in each switch cycle, and an ON time of the second switch is equal in each switch cycle.

According to a further technical aspect of the present invention, a control method used for a PFC circuit is provided. The PFC circuit includes an inductor, a first bridge arm and a second bridge arm connected to the first bridge arm in parallel. The first bridge arm has a first switch and a second switch connected with each other in series. The common node of the first switch and the second switch is coupled to an input voltage through the inductor. The control method includes the following steps: (a) detecting a polarity of the input voltage so as to output a first digital signal and a second digital signal indicating the polarity of the input voltage; (b) generating an analog signal through the signal conversion processing according to at least one inductive signal reflecting an inductive voltage of the inductor, the first digital signal and the second digital signal; (c) providing a predetermined pulse signal and generating a driving pulse signal according to the analog signal and the predetermined pulse signal; and (d) distributing the driving pulse signal to the first switch and the second switch according to the first digital signal and the second digital signal so that one of the first switch and the second switch performs an ON operation.

According to yet a further technical aspect of the present invention, a control circuit used for the PFC circuit is provided. The PFC circuit includes an inductor, a first bridge arm and a second bridge arm connected to the first bridge arm in parallel. The first bridge arm has a first switch and a second switch connected with each other in series. The common node of the first switch and the second switch is coupled to an input voltage through the inductor. The control circuit includes a zero current detection circuit, a feedback circuit and a pulse distribution circuit. The zero current detection circuit includes an edge detection circuit which is used to receive at least one inductive signal reflecting an inductive voltage of the inductor and detect and output a rising edge or a falling edge in the inductive signal; and an enabling circuit which is used to filter the detected rising edge or the detected falling edge and output a zero current detection signal. The feedback circuit is used to receive the zero current detection signal and a predetermined pulse signal and generate a driving pulse signal. The pulse distribution circuit includes a polarity detection circuit. The polarity detection circuit receives the input voltage and outputs a first digital signal and a second digital signal indicating a polarity of the input voltage. A potential of the first digital signal is opposite to that of the second digital signal. The pulse distribution circuit distributes the received driving pulse signal to the first switch and the second switch of the first bridge arm according to the first digital signal and the second digital signal so that one of the first switch and the second switch performs an ON operation. After a switch cycle, one of the first switch and the second switch performs the ON operation for the next switch cycle when the current flowing through the inductor decreases to a predetermined threshold value, and an ON time of the first switch is equal in each switch cycle, and an ON time of the second switch is equal in each switch cycle.

According to still yet a further technical aspect of the present invention, a power source system is provided, including a PFC circuit and a control circuit. The PFC circuit includes: a first bridge arm and a second bridge arm. The first bridge arm includes a first switch and a second switch connected with each other in series. A common node of the first switch and the second switch is coupled to one end of an input voltage through an inductor. The second bridge arm includes a third switch and a fourth switch connected with each other in series. A common node of the third switch and the fourth switch is coupled to the other end of the input voltage. The control circuit includes: a zero current detection circuit, a feedback circuit and a pulse distribution circuit. The zero current detection circuit has an edge detection circuit and an enabling circuit. The edge detection circuit is used to receive at least one inductive signal reflecting the inductive voltage of the inductor, and detect and output a rising edge or a falling edge in the inductive signal. The enabling circuit is used to filter the detected rising edge or the detected falling edge so as to output a zero current detection signal. The feedback circuit is used to receive the zero current detection signal and a predetermined pulse signal and generate a driving pulse signal. The pulse distribution circuit includes a polarity detection circuit. The polarity detection circuit receives the input voltage and outputs a first digital signal and a second digital signal indicating a polarity of the input voltage. A potential of the first digital signal is opposite to that of the second digital signal. The pulse distribution circuit distributes the received driving pulse signal to the first switch and the second switch of the first bridge arm according to the first digital signal and the second digital signal so that one of the first switch and the second switch performs an ON operation. After a switch cycle, one of the first switch and the second switch performs the ON operation for the next switch cycle when the current flowing through the inductor decreases to a predetermined threshold value, and an ON time of the first switch is equal in each switch cycle, and an ON time of the second switch is equal in each switch cycle.

According to a technical aspect of the present invention, a control method used for a PFC circuit is provided. The PFC circuit includes an inductor, a first bridge arm and a second bridge arm connected to the first bridge arm in parallel. The first bridge arm has a first switch and a second switch connected with each other in series. A common node of the first switch and the second switch is coupled to an input voltage through the inductor. The control method includes the following steps: (a) receiving at least one inductive signal reflecting an inductive voltage of the inductor and generating a zero current detection signal through an edge detection and filtering processing; (b) providing a predetermined pulse signal and generating a driving pulse signal according to the zero current detection signal and the predetermined pulse signal; (c) detecting a polarity of the input voltage to output a first digital signal and a second digital signal indicating the polarity of the input voltage; and (d) distributing the driving pulse signal to the first switch and the second switch according to the first digital signal and the second digital signal so that one of the first switch and the second switch performs an ON operation.

The current zero-crossing point detection is realized by using the control circuit, control method and power source system used in the bridgeless PFC circuit of the present invention and through the combination of the polarity detection of the input voltage and the voltage detection of the auxiliary winding. Accordingly, the bridgeless PFC circuit is enabled to work in the critical conduction control mode, so that it is realized to turn on the switch in the first bridge arm under a zero voltage, thereby reducing the switch loss. Furthermore, the combination of the driving pulse signal and the edge detection circuit is used to realize the zero-crossing detection of the inductor current, without detecting the phase/polarity of the input voltage. In this way, the bridgeless PFC circuit is also enabled to work in the critical conduction control mode. The circuit design is simple and the zero-crossing detection of the inductor current is more reliable.

In order to make the foregoing as well as other aspects, features, advantages, and embodiments of the present invention more apparent, the accompanying drawings are described as follows:

FIG. 1A illustrates a circuit structure diagram of a bridgeless PFC circuit;

FIG. 1B illustrates a circuit structure diagram of a bridgeless PFC circuit according to another one embodiment of the present disclosure;

FIG. 2 illustrates a schematic view of an inductor current waveform, a peak inductor current waveform, an average inductor current waveform and a driving signal waveform of the switch when the bridgeless PFC circuit in FIG. 1A works in the critical conduction mode (CRM);

FIG. 3( a ) illustrates a schematic view of a current path when the second switch is on while the AC input voltage in FIG. 1 is a positive voltage, and FIG. 3( b ) illustrates a schematic view of a current path when the second switch is off and the current is continued through the body diode of the first switch while the AC input voltage in FIG. 1A is a positive voltage;

FIG. 3( c ) illustrates a schematic view of a current path when the first switch is on while the AC input voltage in FIG. 1A is a negative voltage, and FIG. 3 ( d ) illustrates a schematic view of a current path when the first switch is off and the current is continued through the body diode of the second switch while the AC input voltage in FIG. 1A is a negative voltage;

FIG. 4 illustrates a structure diagram of a control circuit for a PFC circuit according to an embodiment of the present invention;

FIG. 5 illustrates a first embodiment of the signal conversion circuit in the control circuit in FIG. 4 ;

FIG. 6 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 5 ;

FIG. 7 illustrates a second embodiment of the signal conversion circuit in the control circuit in FIG. 4 ;

FIG. 8 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 7 ;

FIG. 9 illustrates a third embodiment of the signal conversion circuit in the control circuit in FIG. 4 ;

FIG. 10 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 9 ;

FIG. 11 illustrates a structure diagram of a control circuit for a PFC circuit according to another embodiment of the present invention;

FIG. 12 illustrates a first embodiment of the edge detection circuit in the control circuit in FIG. 11 ;

FIG. 13 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 12 ;

FIG. 14 illustrates a second embodiment of the edge detection circuit in the control circuit in FIG. 12 ;

FIG. 15 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 14 ;

FIG. 16 illustrates a third embodiment of the edge detection circuit in the control circuit in FIG. 12 ;

FIG. 17 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 16 ;

FIG. 18 illustrates a fourth embodiment of the edge detection circuit in the control circuit in FIG. 12 ; and

FIG. 19 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 18 .

In order to make the description of the present invention more detailed and more comprehensive, various embodiments of the present invention are described below with reference to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. On the other hand, well-known elements and steps are not described in embodiments so as to avoid the unnecessary limitation to the present invention.

In the embodiments and claims, the description involving “electrical connection” may generally mean that an element is indirectly connected to another element through other electrical elements or an element is directly connected to another element without through other electrical elements.

In the embodiments and claims, the articles “a”, “an” and “the” refer to one or more, unless expressly specified otherwise.

As used herein, the terms “about”, “approximately”, “subsequently” or “near” are used to modify any micro-variable quantity, but these micro-variations do not change the nature of the quantity. In the embodiments the error of the quantity modified by terms “about”, “approximately”, “subsequently” or “near” is in a range of 20%, preferably in a range of 10%, and more preferably in a range of 5%, unless expressly specified otherwise.

FIG. 1A illustrates a circuit structure diagram of a bridgeless PFC circuit. Referring to FIG. 1A , the bridgeless PFC (Power Factor Correction) circuit includes a first bridge arm and a second bridge arm. The first bridge arm includes a first switch Q 1 and a second switch Q 2 connected with each other in series (e.g., MOSFET). A common node of the first switch Q 1 and the second switch Q 2 is coupled to one end of an input voltage through an inductor L 1 . The second bridge arm includes a third switch and a fourth switch connected with each other in series. A common node of the third switch and the fourth switch is coupled to the other end of the input voltage.

In an embodiment, each of the third switch and the fourth switch is a slow-recovery diode, as shown by D 1 and D 2 in FIG. 1A .

FIG. 1B illustrates a circuit structure diagram of a bridgeless PFC circuit accroding to another one embodiment of the present disclosure.

In some other embodiments, as shown in FIG. 1B , each of the first switch Q 1 and the second switch Q 2 is a fast-recovery MOSFET. Each of the third switch and the fourth switch is a slow-recovery MOSFET, as shown by Q 3 and Q 4 in FIG. 1B . For example, the fast-recovery MOSFET is a wide band gap semiconductor component, such as silicon carbide (SiC) or gallium nitride (GaN).

FIG. 2 illustrates a schematic view of an inductor current waveform, a peak inductor current waveform, an average inductor current waveform and a driving signal waveform of the switch when the bridgeless PFC circuit in FIG. 1A works in the critical conduction mode (CRM).

Referring to FIG. 2 , when the bridgeless PFC circuit works in the CR the end of each switch cycle (or at the start of the next switch cycle), the inductor current just decreases to zero. It can be known from the figure that when one of the switches Q 1 and Q 2 in the first bridge arm receives a driving signal, from the ON time of the switch, the inductor current gradually increases and reaches the peak current (the period corresponds to the ON time). Thereafter, the switch is off and the inductor current gradually decreases from the peak current to zero (the period corresponds to the OFF time). Since each switch cycle includes the rising period and the falling period of the inductor current, the common point of the rising period and the falling period is connected (i.e. a point corresponding to the peak current) to form the peak current curve in FIG. 2 . Additionally, according to the inductor current curve and the peak current curve, the corresponding average current curve also can be obtained.

FIG. 3( a ) illustrates a schematic view of a current path when the second switch is on while the AC input voltage in FIG. 1A is a positive voltage. FIG. 3( b ) illustrates a schematic view of a current path when the second switch is off and the current is continued through the body diode of the first switch while the AC input voltage in FIG. 1A is a positive voltage.

Referring to FIGS. 3( a ) and 3 ( b ), in view of the condition that the input voltage is a positive voltage, if the switch Q 2 is on and the switch Q 1 is off, the current path is formed by the inductor L, the switch Q 2 and the diode D 2 . If the switch Q 1 and the switch Q 2 are both off, the current path is formed by the inductor L, the body diode of the switch Q 1 , the capacitor and the diode D 2 .

FIG. 3( c ) illustrates a schematic view of a current path when the first switch is on while the AC input voltage in FIG. 1A is a negative voltage. FIG. 3( d ) illustrates a schematic view of a current path when the first switch is off and the current is continued through the body diode of the second switch while the AC input voltage in FIG. 1A is a negative voltage.

Referring to FIGS. 3( c ) and 3 ( d ), in view of the condition that the input voltage is a negative voltage, if the switch Q 1 is on and the switch Q 2 is off, the current path is formed by the inductor L, the switch Q 1 and the diode D 1 If the switch Q 1 and the switch Q 2 are both off, the current path is formed by the inductor L, the body diode of the switch Q 2 , the capacitor and the diode D 1 .

FIG. 4 illustrates a structure diagram of a control circuit for a PFC circuit according to an embodiment of the present invention.

Referring to FIG. 4 , the control circuit for the bridgeless PFC circuit includes a zero current detection circuit, a feedback circuit and a pulse distribution circuit.

The zero current detection circuit includes a polarity detection circuit and a signal conversion circuit. The polarity detection circuit receives the input voltage of the AC power source and outputs a first digital signal and a second digital signal indicating the polarity of the input voltage. Herein, the potential polarity of the first digital signal is always opposite to that of the second digital signal. When the first digital signal is at a high potential, the second digital signal is at a low potential. When the first digital signal is at a low potential, the second digital signal is at a high potential. The signal conversion circuit receives at least one inductive signal reflecting the inductive voltage of the inductor L 1 , the above-mentioned first digital signal and second digital signal and generates an analog signal.

It should be understood that the control circuit can output an inductive signal reflecting the inductive voltage of the inductor through two auxiliary windings or through a single auxiliary winding. For example, one of two auxiliary windings is used to output the inductive signal when the polarity of the voltage is positive. The other auxiliary winding is used to output the inductive signal when the polarity of the voltage is negative. Also for example, one end of a single auxiliary winding is used to output the inductive signal when the polarity of the voltage is positive. The other end of the single auxiliary winding is used to output the inductive signal when the polarity of the voltage is negative.

The feedback circuit is used to receive the analog signal from the signal conversion circuit and a predetermined pulse signal and generate a driving pulse signal according to the analog signal and the predetermined pulse signal. The pulse distribution circuit is electrically coupled to the polarity detection circuit and the feedback circuit. The pulse distribution circuit is used to distribute the driving pulse signal outputted by the feedback circuit to the first switch Q 1 and the second switch Q 2 of the first bridge arm according to the first digital signal and the second digital signal from the polarity detection circuit. Accordingly, one of the first switch Q 1 and the second switch Q 2 performs an ON operation. After a switch cycle, one of the first switch Q 1 and the second switch Q 2 performs the ON operation for the next switch cycle when the current flowing through the inductor L 1 decreases to a predetermined threshold value, and an ON time of the first switch Q 1 is equal in each switch cycle and an ON time of the second switch Q 2 is equal in each switch cycle.

In an embodiment, the polarity detection circuit includes a first operational amplifier 100 , a first comparator 102 and a first inverter 104 .

The first operational amplifier 100 has a first input end (such as a positive-phase input end), a second input end (such as a negative-phase input end) and an output end. The first input end and the second input end of the first operational amplifier 100 are connected to two ends of the input voltage respectively. The output end of the first operational amplifier 100 is used to output a voltage signal reflecting the polarity of the input voltage. The first comparator 102 has a first input end, a second input end and an output end. The first input end of the first comparator 102 is coupled to the output end of the first operational amplifier 100 . The second input end of the first comparator 102 is coupled to a first reference voltage (such as a ground voltage). The output end of the first comparator 102 is used to output the first digital signal. The first inverter 104 is used to convert the first digital signal into a second digital signal. Therefore, the polarity detection circuit outputs the first digital signal and the second digital signal. The potential polarity of the first digital signal is always opposite to that of the second digital signal.

In an embodiment, the feedback circuit includes a second operational amplifier 200 , a second comparator 202 and a RS trigger 204 .

The second operational amplifier 200 has a first input end (such as a negative-phase input end), a second input end (such as a positive-phase input end) and an output end. The first input end of the second operational amplifier 200 is used to receive the output voltage of the power factor control circuit (i.e., a load voltage across two ends of a capacitor). The second input end of the second operational amplifier 200 is coupled to a second reference voltage (such as V ref ). The output end of the second operational amplifier 200 outputs a difference amplification signal. The second comparator 202 has a first input end, a second input end and an output end. The first input end of the second comparator 202 is coupled to the output end of the second operational amplifier 200 . The second input end of the second comparator 202 is used to receive a saw-tooth wave voltage signal. The output end of the second comparator 202 outputs the predetermined pulse signal. The RS trigger 204 has a preset end S, a reset end R and an output end Q. The preset end S of the RS trigger 204 is used to receive the analog signal V ZCD from the signal conversion circuit. The reset end R of the RS trigger 204 is used to receive the predetermined pulse signal from the second comparator 202 . The output end of the RS trigger 204 is used to output the driving pulse signal.

Additionally, the feedback circuit further includes a delay circuit 206 arranged between the signal conversion circuit and the RS trigger 204 . The delay circuit 206 is used to delay the analog signal V ZCD and send the delayed analog signal to the preset end S of the RS trigger 204 . Furthermore, the feedback circuit further includes a comparing unit (not shown) arranged between the delay circuit 206 and the RS trigger 204 . The comparing unit is used to convert the delayed analog signal into a corresponding digital delay signal and send it to the preset end S of the RS trigger 204 .

In an embodiment, the pulse distribution circuit includes a first AND gate circuit 300 and a second AND gate circuit 302 .

The first AND gate circuit 300 has a first input end, a second input end and an output end. The first input end of the first AND gate circuit 300 is used to receive the first digital signal from the polarity detection circuit. The second input end of the first AND gate circuit 300 is used to receive the driving pulse signal from the feedback circuit. The output end of the first AND gate circuit 300 outputs a first control signal to the first switch Q 1 of the first bridge arm.

The second AND gate circuit 302 has a first input end, a second input end and an output end. The first input end of the second AND gate circuit 302 is used to receive the second digital signal from the polarity detection circuit. The second input end of the second AND gate circuit 302 is used to receive the driving pulse signal from the feedback circuit. The output end of the second AND gate circuit 302 outputs a second control signal to the second switch Q 2 of the first bridge arm. Since the driving pulse signal received by the second AND gate circuit 302 is the same as the driving pulse signal received by the first AND gate circuit 300 and the potential polarity of the second digital signal is always opposite to that of the first digital signal, only one of the first switch Q 1 and the second switch Q 2 in the first bridge arm is on and the other switch is off at any moment.

For example, when the polarity of the input voltage is positive, the first digital signal is at a low potential and the second digital signal is at a high potential. When the polarity of the input voltage is negative, the first digital signal is at a high potential and the second digital signal is at a low potential.

Those of skills in the art should understand that FIG. 4 not only can be used to describe the control circuit for the bridgeless PFC circuit but also can be used to describe the power source system including the bridgeless PFC circuit and the control circuit and the control method corresponding to the control circuit.

Taking a control method for the bridgeless PFC circuit as an example, in this control method, firstly the polarity of the input voltage is detected so as to output a first digital signal and a second digital signal indicating the polarity of the input voltage; subsequently an analog signal V ZCD is generated through the signal conversion processing according to at least one inductive signal reflecting the inductive voltage of the inductor, the first digital signal and the second digital signal; thereafter a predetermined pulse signal is provided and a driving pulse signal is generated according to the analog V ZCD and the predetermined pulse signal; and finally the driving pulse signal is distributed to the first switch Q 1 and the second switch Q 2 according to the first digital signal and the second digital signal, so that one of the first switch Q 1 and the second switch Q 2 performs the ON operation.

FIG. 5 illustrates a first embodiment of the signal conversion circuit in the control circuit in FIG. 4 . FIG. 6 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 5 .

Referring to FIG. 5 , the control circuit includes a first auxiliary winding AUX 1 and a second auxiliary winding AUX 2 which are both coupled to the inductor L 1 . A polarity of a first inductive signal generated by the first auxiliary winding AUX 1 is opposite to that of a second inductive signal generated by the second auxiliary winding AUX 2 .

In an embodiment, the signal conversion circuit includes a first analog switch and a second analog switch. The first analog switch is formed by a first resistor R 1 , a third diode D 3 and a first switch MOS 1 . The second analog switch is formed by a second resistor R 2 , a fourth diode D 4 and a second switch MOS 2 .

One end of the first resistor R 1 is connected to the first end of the first auxiliary winding AUX 1 . The anode of the third diode D 3 is connected to the other end of the first resistor R 1 . The cathode of the third diode D 3 is connected to the output end of the signal conversion circuit so as to output the analog signal V ZCD . The first end of the first switch MOS 1 is connected to the other end of the first resistor R 1 and the anode of the third diode D 3 . The second end of the first switch MOS 1 is connected to the ground end. The control end of the first switch MOS 1 is used to receive the second digital signal V pos .

One end of the second resistor R 2 is connected to the first end of the second auxiliary winding AUX 2 . The second ends of the second auxiliary winding AUX 2 and the first auxiliary winding AUX 1 are connected to the ground end respectively. The anode of the fourth diode D 4 is connected to the other end of the second resistor R 2 . The cathode of the fourth diode D 4 is connected to the output end of the signal conversion circuit so as to output the analog signal V ZCD . The first end of the second switch. MOS 2 is connected to the other end of the second resistor R 2 and the anode of the fourth diode D 4 . The second end of the second switch MOS 2 is connected to the ground end. The control end of the second switch MOS 2 is used to receive the first digital signal V neg .

It can be known from FIG. 6 that in an input voltage cycle, the waveform of the voltage V AUX1 across two ends of the first auxiliary winding is always opposite to that of the voltage V AUX2 across two ends of the second auxiliary winding. Furthermore, the waveform of the potential V a at the common node of the resistor R 1 and the diode D 3 in the first analog switch is just opposite to that of the potential V b at the common node of the resistor R 2 and the diode D 4 in the second analog switch in the first half cycle and the second half cycle of the input voltage. For example, in the first half cycle of the input voltage, the potential V a is a low potential and the potential V b varies along with the voltage waveform of the second auxiliary winding. Correspondingly, the waveform of the analog signal V ZCD outputted by the signal conversion circuit is the same as that of the potential V b . Also for example, in the second half cycle of the input voltage, the potential V b is a low potential and the potential V a varies along with the voltage waveform of the first auxiliary winding. Correspondingly, the waveform of the analog signal V ZCD outputted by the signal conversion circuit is the same as that of the potential V a .

Additionally, in the waveform of the analog signal V ZCD , the period from t 1 to t 2 represents a stage that the inductor current decreases from the positive peak to zero. The period from t 2 to t 3 represents a stage that the inductor current varies from zero to the negative peak. The period from t 3 to t 4 represents a stage that the inductor current recovers from the negative peak to the zero current. Similarly, the period from t 5 to t 6 represents a stage that the inductor current varies from the negative peak to the zero current. The period from t 6 to t 7 represents a stage that the inductor current varies from zero to the positive peak. The period from t 7 to t 8 represents a stage that the inductor current decreases from the positive peak to zero.

FIG. 7 illustrates a second embodiment of the signal conversion circuit in the control circuit in FIG. 4 . FIG. 8 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 7 .

Referring to FIG. 7 , the control circuit includes a first auxiliary winding AUX 1 and a second auxiliary winding AUX 2 which are both coupled to the inductor L 1 . A polarity of a first inductive signal generated by the first auxiliary winding AUX 1 is opposite to that of a second inductive signal generated by the second auxiliary winding AUX 2 .

In an embodiment, the signal conversion circuit includes a first analog switch and a second analog switch. The first analog switch is formed by a fifth resistor R 5 , a third switch MOS 3 and a fifth switch MOS 5 . The second analog switch is formed by a sixth resistor RS, a fourth switch MOS 4 and a sixth switch MOS 6 .

One end of the fifth resistor R 5 is connected to the first end of the first auxiliary winding AUX 1 . The first end of the third switch MOS 3 is connected to the first end of the first auxiliary winding AUX 1 . The second end of the third switch MOS 3 is connected to the anode of a seventh diode D 7 . The control end of the third switch MOS 3 is connected to the other end of the fifth resistor R 5 . The first end of the fifth switch MOS 5 is connected to the other end of the fifth resistor R 5 and the control end of the third switch MOS 3 . The second end of the fifth switch MOS 5 is connected to the ground end. The control end of the fifth switch MOS 5 is used to receive the first digital signal V neg .

One end of the sixth resistor R 6 is connected to the first end of the second auxiliary winding AUX 2 . The second ends of the second auxiliary winding AUX 2 and the first auxiliary winding AUX 1 are connected to the ground end respectively. The first end of the fourth switch MOS 4 is connected to the first end of the second auxiliary winding AUX 2 . The second end of the fourth switch MOS 4 is connected to the anode of an eighth diode D 8 . The control end of the fourth switch MOS 4 is connected to the other end of the sixth resistor R 6 . The first end of the sixth switch MOS 6 is connected to the other end of the sixth resistor R 6 and the control end of the fourth switch MOS 4 . The second end of the sixth switch MOS 6 is connected to the ground end. The control end of the sixth switch MOS 6 is used to receive the second digital signal V pos . The cathodes of the seventh diode D 7 and the eighth diode D 8 are connected to the output end of the signal conversion circuit respectively so as to output the analog signal V ZCD .

The respective waveforms of the first auxiliary winding AUX 1 , the second auxiliary winding AUX 2 and the analog signal V ZCD in FIG. 8 are the same as or similar to FIG. 6 , and it is not illustrated any more for purpose of convenience.

FIG. 9 illustrates a third embodiment of the signal conversion circuit in the control circuit in FIG. 4 . FIG. 10 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the signal conversion circuit in FIG. 9 .

Referring to FIG. 9 , the control circuit includes the single auxiliary winding AUX 1 coupled to the inductor L 1 . The analog signal V ZCD is generated by a third inductive signal generated by the auxiliary winding AUX 1 , the first digital signal and the second digital signal.

In an embodiment, the signal conversion circuit includes a first analog switch and a second analog switch. The first analog switch is formed by a seventh resistor R 7 , a ninth diode D 9 and a seventh switch MOS 7 . The second analog switch is formed by an eighth resistor R 8 , a tenth diode D 10 and an eighth switch MOS 8 .

One end of the seventh resistor R 7 is connected to the first end of the auxiliary winding AUX 1 . The anode of the ninth diode D 9 is connected to the other end of the seventh resistor R 7 . The cathode of the ninth diode D 9 is connected to the output end of the signal conversion circuit so as to output the analog signal V ZCD . The first end of the seventh switch MOS 7 is connected to the other end of the seventh resistor R 7 and the anode of the ninth diode D 9 . The second end of the seventh switch MOS 7 is connected to the ground end. The control end of the seventh switch MOS 7 is used to receive the second digital signal V pos .

One end of the eighth resistor R 8 is connected to the second end of the auxiliary winding AUX 1 . The anode of the tenth diode D 10 is connected to the other end of the eighth resistor R 8 . The cathode of the tenth diode D 10 is connected to the output end of the signal conversion circuit so as to output the analog signal V ZCD . The first end of the eighth switch MOS 8 is connected to the other end of the eighth resistor R 8 and the anode of the tenth diode D 10 . The second end of the eighth switch MOS 8 is connected to the ground end. The control end of the eighth switch MOS 8 is used to receive the first digital signal V neg .

Referring to FIGS. 9 and 10 , in the first half cycle of the input voltage, the first digital signal V neg is at a low potential and the second digital signal V pos is at a high potential. At this time the seventh switch MOS 7 is on and the eighth switch MOS 8 is off. Therefore, the potential of V a3 is maintained as the ground voltage, and at this time the potential of V b3 varies along with the voltage waveform of the negative terminal of the auxiliary winding AUX 1 (opposite to the variation trend of voltage waveform V AUX1 of the auxiliary winding). Similarly, in the second half cycle of the input voltage, the first digital signal V neg is at a high potential and the second digital signal V pos is at a low potential. At this time the seventh switch MOS 7 is of and the eighth witch MOS 8 is on. Therefore, the potential of V b3 is maintained as the ground voltage, and at this time the potential of V a3 varies along with the voltage waveform of the positive terminal of the auxiliary winding AUX 1 (the same as the variation trend of voltage waveform V AUX1 of the auxiliary winding).

FIG. 11 illustrates a structure diagram of a control circuit for a PFC circuit according to another embodiment of the present invention.

Referring to FIG. 11 , the control circuit for the bridgeless PFC circuit includes a zero current detection circuit, a feedback circuit and a pulse distribution circuit.

The zero current detection circuit includes an edge detection circuit 406 and an enabling circuit. The edge detection circuit 406 receives at least one inductive signal reflecting the inductive voltage of the inductor L 1 and detects and outputs the rising edge or the falling edge in the inductive signal. The enabling circuit filters the detected rising edge or the detected falling edge and outputs a zero current detection signal V ZCD .

The feedback circuit is used to receive the zero current detection signal V ZCD and a predetermined pulse signal and generates a driving pulse signal according to the analog signal and the predetermined pulse signal. The pulse distribution circuit includes a polarity detection circuit. The polarity detection circuit receives the input voltage and outputs a first digital signal and a second digital signal indicating the polarity of the input voltage. The potential of the first digital signal is opposite to that of the second digital signal. The pulse distribution circuit distributes the received driving pulse signal to the first switch Q 1 and the second switch Q 2 of the first bridge arm according to the first digital signal and the second digital signal so that one of the first switch Q 1 and the second switch Q 2 performs the ON operation. After a switch cycle, one of the first switch Q 1 and the second switch Q 2 performs the ON operation for the next switch cycle when the current flowing through the inductor L 1 decreases to a predetermined threshold value, and an ON time of the first switch Q 1 is equal in each switch cycle and an ON time of the second switch Q 2 is equal in each switch cycle.

Comparing FIG. 11 with FIG. 4 , the main difference is that the polarity detection circuit in FIG. 11 does not detect the zero-crossing point of the inductor current waveform any longer and is instead used to distribute the driving pulse signal to the switch Q 1 or the switch Q. That is, the first digital signal and the second digital signal outputted by the polarity detection circuit in FIG. 11 , indicating the polarity of the input voltage, act on the driving pulse signal so as to control the ON operation of switch Q 1 or the switch Q 2 . By comparison, the polarity detection circuit in FIG. 4 needs to send the first digital signal and the second digital signal into the signal conversion circuit so that the signal conversion circuit makes use of the first digital signal, the second digital signal and the inductive signal to output the analog signal V ZCD , i.e., the analog signal for the zero current detection (ZCD).

In an embodiment, the polarity detection circuit includes a first operational amplifier 604 , a first comparator 606 and a first inverter 608 . The first operational amplifier 604 , the first comparator 606 and the first inverter 608 have the same or similar connection manner with the first operational amplifier 100 , the first comparator 102 and the first inverter 104 in FIG. 4 , and thus it is not illustrated any more for purpose of convenience.

In another embodiment, the feedback circuit includes a second operational amplifier 500 , a second comparator 502 and a RS trigger 504 The second operational amplifier 500 , the second comparator 502 and the RS trigger 504 have the same or similar connection manner with the second operational amplifier 200 , the second comparator 202 and the RS trigger 204 in FIG. 4 , and thus it is not illustrated any more for purpose of convenience.

Additionally, the zero current detection circuit further includes a delay circuit 408 arranged between the enabling circuit and the RS trigger 504 . The delay circuit 408 is used to delay the zero current detection signal V ZCD and send the delayed zero current detection signal to the preset end S of the RS trigger 504 . As shown in FIG. 11 , the enabling circuit is formed by the switch MOS 1 , the resistor R 1 and the capacitor C 2 . The enabling circuit is used to select a correct edge signal and avoid generating a wrong current zero-crossing detection signal. Further details are described below with reference to FIGS. 12 and 13 .

In an embodiment, the zero current detection circuit further includes a comparing unit (not shown) arranged between the delay circuit 408 and the RS trigger 504 . The comparing unit is used to convert the delayed zero current detection signal into a corresponding digital delay signal and send it to the preset end S of the RS trigger 504 .

In another embodiment, the pulse distribution circuit includes a first AND gate circuit 600 and a second AND gate circuit 602 .

The first AND gate circuit 600 has a first input end, a second input end and an output end. The first input end of the first AND gate circuit 600 is used to receive the first digital signal from the polarity detection circuit. The second input end of the first AND gate circuit 600 is used to receive the driving pulse signal from the feedback circuit. The output end of the first AND gate circuit 600 outputs a first control signal to the first switch Q 1 of the first bridge arm.

The second AND gate circuit 602 has a first input end, a second input end and an output end. The first input end of the second AND gate circuit 602 is used to receive the second digital signal from the polarity detection circuit. The second input end of the second AND gate circuit 602 is used to receive the driving pulse signal from the feedback circuit. The output end of the second AND gate circuit 602 outputs a second control signal to the second switch. Q 2 of the first bridge arm. Since the driving pulse signal received by the second AND gate circuit 602 is the same as the driving pulse signal received by the first AND gate circuit 600 and the potential polarity of the second digital signal is always opposite to that of the first digital signal, only one of the first switch Q 1 and the second switch Q 2 in the first bridge arm is on and the other switch is off at any moment.

For example, when the polarity of the input voltage is positive, the first digital signal is at a low potential and the second digital signal is at a high potential. When the polarity of the input voltage is negative, the first digital signal is at a high potential and the second digital signal is at a low potential.

In an embodiment, the enabling circuit includes the switch MOS 1 , the resistor R 1 and the capacitor C 2 . In particular, the first end of the switch MOS 1 is electrically connected to the first end of the resistor R 1 . The second end of the switch MOS 1 is connected to the output end of the edge detection circuit 406 . The third end of the switch MOS 1 is connected to the ground voltage. The first end of the resistor RI is electrically connected to the first end of the switch MOS 1 . The second end of the resistor R 1 is electrically connected to the output end of the feedback circuit. One end of the capacitor C 2 is connected to the first end of the switch MOS 1 and the first end of the resistor R 1 . The other end of the capacitor C 2 is connected to the third end of the switch MOS 1 . The enabling circuit filters the rising edge or the falling edge in the inductive signal outputted by the edge detection circuit 406 according to the driving pulse signal outputted by the feedback circuit so as to extract a correct edge signal.

Those of skills in the art should understand that FIG. 11 not only can be used to describe the control circuit for the bridgeless PFC circuit but also can be used to describe the power source system including the bridgeless PFC circuit and the control circuit and the control method corresponding to the control circuit.

Taking a control method for the bridgeless PFC circuit as an example, in this control method, firstly at least one inductive signal reflecting the inductive voltage of the inductor is received and a zero current detection signal generated through the edge detection and filtering processing; subsequently a predetermined pulse signal is provided and a driving pulse signal is generated according to the zero current detection signal and the predetermined pulse signal; thereafter the polarity of the input voltage is detected to output a first digital signal and a second digital signal indicating the polarity of the input voltage; and finally the driving pulse signal is distributed to the first switch Q 1 and the second switch Q 2 according to the first digital signal and the second digital signal, so that one of the first switch Q 1 and the second switch Q 2 performs the ON operation.

FIG. 12 illustrates a first embodiment of the edge detection circuit in the control circuit in FIG. 11 . FIG. 13 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 12 .

Referring to FIG. 12 , the control circuit includes a first auxiliary winding AUX 1 and a second auxiliary winding AUX 2 which are both coupled to the inductor L 1 . The polarity of a first inductive signal generated by the first auxiliary winding AUX 1 is opposite to that of a second inductive signal generated by the second auxiliary winding AUX 2 .

In an embodiment, the edge detection circuit includes a first analog switch and a second analog switch. The first analog switch is formed by a third resistor R 3 , a fifth diode D 5 and a third capacitor C 3 . The second analog switch is formed by a fourth resistor R 4 , a sixth diode D 6 and a fourth capacitor C 4 .

One end of the third resistor R 3 is connected to the first end of the first auxiliary winding AUX 1 The cathode of the fifth diode D 5 is connected to the first end of the first auxiliary winding AUX 1 . The anode of the fifth diode D 5 is connected to the other end of the third resistor R 3 . One end of the third capacitor C 3 is connected to the anode of the fifth diode D 5 . The other end of the third capacitor C 3 is connected to the ground end.

One end of the fourth resistor R 4 is connected to the first end of the second auxiliary winding AUX 2 . The second ends of the second auxiliary winding AUX 2 and the first auxiliary winding AUX 1 are connected to the ground end respectively. The cathode of the sixth diode D 6 is connected to the first end of the second auxiliary winding AUX 2 . The anode of the sixth diode D 6 is connected to the other end of the fourth resistor R 4 . One end of the fourth capacitor C 4 is connected to the anode of the sixth diode D 6 . The other end of the fourth capacitor C 4 is connected to the ground end. The anode of the fifth diode D 5 and the anode of the sixth diode D 6 are connected to the third diode D 3 and the fourth diode D 4 respectively, so as to output the zero current detection signal V ZCD through the third diode D 3 and the fourth diode D 4 .

Referring to FIGS. 12 and 13 , at t 1 , the voltage V c3 on the capacitor C 3 is changed from a positive voltage signal to a negative voltage signal with one falling edge. If the above-mentioned enabling circuit is not provided, after the logic AND circuit formed by the diode D 3 and the diode D 4 , V ZCD generates a corresponding falling edge waveform at the same time as t 1 . However, the falling edge is caused by the reversion of the voltage across two ends of the auxiliary winding due to the action of the switch, which is not a correct edge signal. Therefore, the driving signal V DRV of the switch is received by the enabling circuit. A certain delay is generated according to the resistor R 1 and the capacitor C 2 in order to drive the switch MOS 1 , so that V ZCD s a signal at a low potential during the period when V DRV is positive, such as V TH in FIG. 13 . In this way, a wrong hopping signal is filtered through V ZCD and the enabling circuit and a correct zero current detection signal is obtained.

FIG. 14 illustrates a second embodiment of the edge detection circuit in the control circuit in FIG. 12 . FIG. 15 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 14 .

Referring to FIG. 14 , the edge detection circuit includes a first detection module and a second detection module. The first detection module is formed by a first operational amplifier A 2 - 1 , a RC circuit, an inverter N 2 - 1 and a NAND gate circuit 2 - 1 . The second detection module is formed by a second operational amplifier A 2 - 2 , a RC circuit, an inverter N 2 - 2 and a NAND gate circuit 2 - 2 .

The first operational amplifier A 2 - 1 has a first input end, a second input end and an output end. The first input end of the first operational amplifier A 2 - 1 is connected to the first end of the first auxiliary winding AUX 1 . The second input end of the first operational amplifier A 2 - 1 is connected to a ground voltage. The output end of the first operational amplifier A 2 - 1 outputs a first digital signal V D2-1 . The RC circuit has a first resistor R 2 - 1 and a first capacitor C 2 - 1 . One end of the first resistor R 2 - 1 is connected to the output end of the first operational amplifier A 2 - 1 . One end of the first capacitor C 2 - 1 is connected to the ground end. The input end of the inverter N 2 - 1 is connected to the common node of the first resistor R 2 - 1 and the first capacitor C 2 - 1 . The NAND gate circuit 2 - 1 has a first input end, a second input end and an output end. The first input end of the NAND gate circuit 2 - 1 is connected to the output end of the first operational amplifier A 2 - 1 . The second input end of the NAND gate circuit 2 - 1 is connected to the output end of the inverter N 2 - 1 . The output end of the NAND gate circuit 2 - 1 outputs a first pulse signal V D2-3 .

The second operational amplifier A 2 - 2 has a first input end, a second input end and an output end. The first input end of the second operational amplifier A 2 - 2 is connected to the first end of the second auxiliary winding AUX 2 . The second input end of the second operational amplifier A 2 - 2 is connected to a ground voltage. The output end of the second operational amplifier A 2 - 2 outputs a second digital signal V D2-2 . The RC circuit has a second resistor R 2 - 2 and a second capacitor C 2 - 2 One end of the second resistor R 2 - 2 is connected to the output end of the second operational amplifier A 2 - 2 . One end of the second capacitor C 2 - 2 is connected to the ground end. The input end of the inverter N 2 - 2 is connected to the common node of the second resistor R 2 - 2 and the second capacitor C 2 - 2 . The NAND gate circuit 2 - 2 has a first input end, a second input end and an output end. The first input end of the NAND gate circuit 2 - 2 is connected to the output end of the second operational amplifier A 2 - 2 . The second input end of the NAND gate circuit 2 - 2 is connected to the output end of the inverter N 2 - 2 . The output end of the NAND gate circuit 2 - 2 outputs a second pulse signal V D2-4 . The logic AND operation is performed for the first pulse signal V D2-3 and the second pulse signal V D2-4 to obtain the zero current detection signal.

Referring to FIG. 15 , the first digital signal V D2-1 outputted by the first operational amplifier A 2 - 1 is used to detect the rising edge of the voltage waveform of the auxiliary winding AUX 1 . The second digital signal V D2-2 outputted by the second operational amplifier A 2 - 2 is used to detect the rising edge of the voltage waveform of the auxiliary winding AUX 2 . Therefore, the edge detection circuit is also referred to as the rising edge detection circuit. Additionally, the zero current detection signal V ZCD2 is the voltage waveform obtained when the logic AND operation is performed for the first pulse signal V D2-3 and the second pulse signal V D2-4 .

FIG. 16 illustrates a third embodiment of the edge detection circuit in the control circuit in FIG. 12 . FIG. 17 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 16 .

Referring to FIG. 16 the control circuit includes the single auxiliary winding AUX 1 coupled to the inductor L 1 . A third inductive signal generated by the auxiliary winding AUX 1 is used to detect and output the rising edge or the falling edge in the third inductive signal.

The edge detection circuit includes a detection module. The detection module has an operational amplifier A 3 - 1 , a RC circuit, an inverter N 3 - 1 , a NAND gate circuit 3 - 1 and an OR gate circuit 3 - 2 .

The operational amplifier A 3 - 1 has a first input end, a second input end and an output end. The first input end of the operational amplifier A 3 - 1 is connected to the first end of the auxiliary winding AUX 1 . The second input end of the operational amplifier A 3 - 1 is connected to a ground end. The output end of the operational amplifier A 3 - 1 outputs a digital signal V D3-1 . The RC circuit has a resistor R 3 - 1 and a capacitor C 3 - 1 . One end of the resistor R 3 - 1 is connected to the output end of the operational amplifier A 3 - 1 . One end of the capacitor C 3 - 1 is connected to the ground end. The input end of the inverter N 3 - 1 is connected to the common node of the resistor R 3 - 1 and the capacitor C 3 - 1 . The NAND gate circuit 3 - 1 has a first input end, a second input end and an output end. The first input end of the NAND gate circuit 3 - 1 is connected to the output end of the operational amplifier A 3 - 1 . The second input end of the NAND gate circuit 3 - 1 is connected to the output end of the inverter N 3 - 1 . The output end of the NAND gate circuit 3 - 1 outputs a first pulse signal V D3-3 . The OR gate circuit 3 - 2 has a first input end, a second input end and an output end. The first input end of the OR gate circuit 3 - 2 is connected to the output end of the operational amplifier A 3 - 1 . The second input end of the OR gate circuit 3 - 2 is connected to the output end of the inverter N 3 - 1 . The output end of the OR gate circuit 3 - 2 outputs a second pulse signal V D3-4 . The logic AND operation is performed for the first pulse signal V D3-3 and the second pulse signal V D3-4 to obtain the zero current detection signal V ZCD3 .

Referring to FIGS. 16 and 17 , the rising edge detection circuit is formed by the resistor R 3 - 1 , the capacitor C 3 - 1 , the NOT gate N 3 - 1 and the NAND gate 3 - 1 , so as to convert the rising edge of the inductive voltage of the auxiliary winding AUX 1 into the negative-logic narrow pulse V D3-3 . The falling edge detection circuit is formed by the resistor R 3 - 1 , the capacitor C 3 - 1 , the NOT gate N 3 - 1 and the OR gate 3 - 2 , so as to convert the falling edge of the inductive voltage of the auxiliary winding AUX 1 into the negative-logic narrow pulse V D3-4 . The AND gate 3 - 3 combines the narrow pulses respectively formed by the rising edge detection circuit and the falling edge detection circuit so as to generate the zero current detection signal V ZCD3 . Therefore, in the embodiment, both the rising edge and the falling edge of the inductive voltage waveform of the auxiliary winding can be converted into the negative-logic narrow pulse so as to realize the functions of the rising edge detection and falling edge detection.

FIG. 18 illustrates a fourth embodiment of the edge detection circuit in the control circuit in FIG. 12 . FIG. 19 illustrates a waveform schematic view of the current zero-crossing detection signal outputted by the edge detection circuit in FIG. 18 .

Referring to FIG. 18 , the control circuit includes the single auxiliary winding AUX 1 coupled to the inductor L 1 . An inductive signal generated by the auxiliary winding AUX 1 is used to detect and output the rising edge or the falling edge in the inductive signal.

The edge detection circuit includes a first optical coupler 4 - 1 and a second optical coupler 4 - 2 . The first input end of the first optical coupler 4 - 1 is connected to the second end of the auxiliary winding AUX 1 . The second input end of the first optical coupler 4 - 1 is connected to the first end of the auxiliary winding AUX 1 through a first resistor R 4 - 1 . The first output end of the first optical coupler 4 - 1 is connected to a power source voltage V CC . The first input end of the second optical coupler 4 - 2 is connected to the second input end of the first optical coupler 4 - 1 . The second input end of the second optical coupler 4 - 2 is connected to the second end of the auxiliary winding AUX 1 . The first output end of the second optical coupler 4 - 2 is connected to the power source voltage V CC . The second output end of the second optical coupler 4 - 2 is connected to the second output end of the first optical coupler 4 - 1 so as to output the zero current detection signal V ZCD4 .

Referring to FIGS. 18 and 19 , when the inductive voltage of the auxiliary winding AUX 1 has no hop, the inductive voltage can make one of the optical coupler 4 - 1 and the optical coupler 4 - 2 on so that the zero current detection signal V ZCD4 is at a high potential. When the inductive voltage of the auxiliary winding is reversed (including conditions that the inductive voltage is modulated from the negative voltage to the positive voltage and from the positive voltage to the negative voltage), it is sure that the inductive voltage passes the common cutoff region of the optical coupler 4 - 1 and the optical coupler 4 - 2 . At this time, the zero current detection signal V ZCD4 is at a low potential so as to output a negative-logic narrow pulse. In this way, the edge detection function for the inductive voltage of the auxiliary winding also can be realized so that the zero-crossing point of the inductor current can be determined.

Although the present invention has been disclosed with reference to the above embodiments, these embodiments are not intended to limit the present invention. It will be apparent to those of skills in the art that various modifications and variations can he made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention shall be defined by the appended claims.