Amplifier for output buffer and signal processing apparatus using the same

This application claims the benefit of Korean Patent Application No. 10-2012-0028962, filed on Mar. 21, 2012, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Example embodiments relate to an amplifier, and more particularly, to an amplifier for an output buffer and a signal processing apparatus using the amplifier.

An operational amplifier is an example of an amplifier that is used for an output buffer in a signal processing apparatus. The operational amplifier has two input terminals and one output terminal, amplifies a voltage difference between voltages applied to a first input terminal and a second input terminal, and outputs the amplified voltage difference. As a driving frequency of the signal processing apparatus increases, research for improving a slew rate of an amplifier for an output buffer may be useful.

According to some embodiments, the disclosure provides an amplifier for an output buffer that may improve a slew rate of the amplifier by employing an adaptive-type self-bias circuit.

The disclosure also provides a signal processing apparatus using an amplifier for an output buffer that may improve a slew rate of the amplifier by employing an adaptive-type self-bias circuit.

According to one embodiment, there is provided an amplifier for an output buffer, the amplifier including: an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit configured to generate a first current path and a second current when the voltage difference between signals applied to the first input terminal and the second input terminal is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path and to add the generated tail current to the input bias current of the operational amplifier, wherein the second input terminal is connected to the output terminal.

If the voltage difference between signals applied to the first input terminal and the second input terminal is less than the predetermined voltage, both the first and second current paths may be cut off.

The self-bias circuit may add the tail current that is generated on the first or second current path to an input bias current of the operational amplifier by using a current mirror circuit.

According to another embodiment, there is provided a signal processing apparatus including: a digital-to-analog converter (DAC) configured to convert a digital image signal into an analog image signal; and an amplifier for an output buffer configured to amplify the analog image signal and to supply the amplified analog image signal to a display panel, wherein the amplifier includes: an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit configured to generate a first current path and a second current when the voltage difference between signals applied to the first input terminal and the second input terminal is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path, and to add the generated tail current to the input bias current of the operational amplifier, and wherein the second input terminal is connected to the output terminal.

According to further another embodiment, there is provided an amplifier circuit of a semiconductor device. The amplifier circuit including: an operational amplifier comprising an input circuit including a first input terminal, a second input terminal, a first node, and a second node, and an output terminal, the operational amplifier configured to amplify a voltage difference between a first input voltage applied to the first input terminal and a second input voltage applied to the second input terminal, and configured to output the amplified voltage difference through the output terminal; a first self-bias circuit connected to the first input terminal, the second input terminal, the first node, and the second node, the first self-bias circuit configured to generate a first current path when a second input voltage applied to the second input terminal is greater than a first input voltage applied to the first input terminal; and a second self-bias circuit connected to the first input terminal, the second input terminal, the first node, and the second node, the second self-bias circuit configured to generate a second current path when a first input voltage applied to the first input terminal is greater than a second input voltage applied to the second input terminal, wherein the second input terminal is connected to the output terminal.

Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a structure of a display system according to one embodiment;

FIG. 2 illustrates a structure of a source driver illustrated in FIG. 1 , according to an exemplary embodiment;

FIG. 3 illustrates a structure of an output buffer circuit illustrated in FIG. 2 , according to an exemplary embodiment;

FIG. 4 illustrates a structure of an amplifier for the output buffer circuit illustrated in FIG. 3 , according to one embodiment;

FIG. 5 is a block diagram of a structure of an operational amplifier illustrated in FIG. 4 , according to one embodiment;

FIG. 6 is a detailed block diagram of the amplifying circuit illustrated in FIG. 5 , according to one embodiment;

FIG. 7 illustrates a detailed circuit structure of the operational amplifier of FIG. 4 , according to one embodiment;

FIG. 8 is a block diagram of a structure of a self-bias circuit illustrated in FIG. 4 , according to one embodiment;

FIG. 9 illustrates a detailed circuit structure of the self-bias circuit of FIG. 4 that is connected to an input circuit of the operational amplifier of FIG. 4 , according to one embodiment;

FIGS. 10A through 10D illustrate exemplary waveforms of primary signals that are generated in the circuit of FIG. 9 ;

FIG. 11 illustrates a detailed circuit structure of the self-bias circuit of FIG. 4 that is connected to an input circuit of the operational amplifier of FIG. 4 , according to another embodiment; and

FIGS. 12A through 12D illustrate exemplary waveforms of primary signals that are generated in the circuit of FIG. 11 .

Example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.

The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Like reference numerals refer to like elements. In the drawings, elements may be enlarged compared to their actual sizes for convenience of explanation, and ratios of the elements may be exaggerated or reduced.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, A, B, etc. may be used herein in reference to elements of the disclosure, such elements should not be construed as limited by these terms unless the context indicates otherwise. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the present disclosure. Herein, the term “and/or” includes any and all combinations of one or more referents.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which exemplary embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 illustrates a structure of a display system 1000 according to one embodiment.

As illustrated in FIG. 1 , the display system 1000 includes a timing controller 110 , a source driver 120 , a gate driver 130 , and a display panel 140 .

The display panel 140 may be, for example, a liquid crystal display (LCD) panel. The timing controller 110 generates a control signal used in controlling the source driver 120 and the gate driver 130 and processes image data received from outside so as to transmit the processed image data to the source driver 120 .

The source driver 120 may receive the image data provided by the timing controller 120 , may generate analog grey scale signals corresponding to the received image data, and may output the analog grey scale signals to source lines Y 1 to Yn of the display panel 140 .

The gate driver 130 enables gate lines G 1 to Gm of the display panel 140 sequentially in response to control signals supplied by the timing controller 120 .

Thus, in each of a plurality of liquid crystal cells arranged in the enabled gate lines G 1 to Gm of the display panel 140 , optical characteristics of liquid crystal are adjusted according to voltages of the analog grey scale signals applied to the source lines Y 1 to Yn so that an image may be displayed.

FIG. 2 illustrates a structure of the source driver 120 illustrated in FIG. 1 , according to an exemplary embodiment.

As illustrated in FIG. 2 , the source driver 120 includes a shift register circuit 210 , a data latch circuit 220 , a digital-to-analog converter (DAC) 230 , and an output buffer circuit 240 .

The shift register circuit 210 controls a time at which pieces of digital image data DATA are sequentially stored in the data latch circuit 220 . The shift register circuit 210 shifts a horizontal start signal DIO that is received in response to a clock signal HCLK.

The data latch circuit 220 receives and stores the digital image data DATA transmitted from the timing controller 110 (see FIG. 1 ) in response to the horizontal start signal DIO. When storing of the image data DATA corresponding to one horizontal line is completed, the data latch circuit 220 may output the image data DATA in response to an output control signal CLK 1 .

The DAC 230 receives the digital image data DATA that is output from the data latch circuit 220 , and outputs analog grey scale signals corresponding to the data image data DATA in response to the output control signal CLK 1 .

The output buffer circuit 240 buffers the analog grey scale signals that are output by the DAC 230 , and outputs the buffered analog grey scale signals.

FIG. 3 illustrates a structure of the output buffer circuit 240 illustrated in FIG. 2 , according to an exemplary embodiment.

As illustrated in FIG. 3 , the output buffer circuit 240 may include amplifiers 310 A and 310 B for an output buffer, output control switches SO 1 and SO 2 , share switches SCS 1 to SCS 4 , resistors Resd 1 and Resd 2 , and diodes D 1 to D 4 .

A grey scale voltage that is to be applied to a first data line of the display panel 140 (see FIG. 1 ) as an input voltage Vin 1 is applied to the amplifier 310 A for an output buffer. The amplifier 310 A for an output buffer buffers the input voltage Vin 1 and outputs the buffered input voltage Vin 1 as a first driving voltage Vout 1 .

A grey scale voltage that is to be applied to a second data line of the display panel 140 (see FIG. 1 ) as an input voltage Vin 2 is applied to the amplifier 310 B for an output buffer. The amplifier 310 B for an output buffer buffers the input voltage Vin 2 and outputs the buffered input voltage Vin 2 as a second driving voltage Vout 2 .

The output buffer circuit 240 performs a buffering operation by using the amplifiers 310 A and 310 B having a good current driving capability so that, when a load current flowing through a load, for example, a data line of the display panel 140 and a pixel capacitor, is increased, the output buffer circuit 240 may supply an output signal at a predetermined voltage level.

The output control switches SO 1 and SO 2 are switches for controlling the supply of an output signal from the amplifier 310 A or 310 B for an output buffer to the first data line or the second data line of the display panel 140 .

The share switches SCS 1 to SCS 4 form charge share paths. A charge share function allows data lines of the display panel 140 to be temporarily connected to one another when gate lines to be driven, i.e., lines to be displayed, are changed and allows the data lines to share charges. Thus, a driving burden of the amplifiers 310 A and 310 B that drive the data lines may be reduced.

The resistors Resd 1 and Resd 2 are elements that protect internal devices from static electricity. The diodes D 1 to D 4 are also elements that protect internal devices from static electricity when high voltages are applied to output pads Y 1 and Y 2 .

FIG. 4 illustrates a structure of the amplifier 310 A or 310 B for the output buffer circuit 240 illustrated in FIG. 3 , according to one embodiment. However, the amplifier 310 A or 310 B illustrated in FIG. 4 is not limited to being applied to a source driver and may be applied to an output buffer for various electronic devices, for example, a regulator, a power booster, various driver circuits, and the like.

As illustrated in FIG. 4 , the amplifier 310 A or 310 B according to the present embodiment may include a self-bias circuit 410 and an operational amplifier 420 .

The self-bias circuit 410 may include first and second current paths that are connected to a first input terminal IN 1 and a second input terminal IN 2 of the operational amplifier 420 , respectively. When a voltage difference between signals applied to the first input terminal IN 1 and the second input terminal IN 2 is equal to or greater than a predetermined voltage (e.g., V=Vthn+|Vthp|, Vthn=a threshold voltage of either “an NMOS transistor” or “NMOS transistors” connected to the first input terminal IN 1 , Vthp=a threshold voltage of either “a PMOS transistor” or “PMOS transistors” connected to the second input terminal IN 2 ), the self-bias circuit 410 generates a tail current on the first current path or the second current path and transmits the generated tail current to the operational amplifier 420 .

The operational amplifier 420 may include the first input terminal IN 1 , the second input terminal IN 2 , and an output terminal OUT. The operational amplifier 420 amplifies a voltage difference between signals applied to the first input terminal IN 1 and the second input terminal IN 2 based on a bias current to which the tail current transmitted from the self-bias circuit 410 is added, and outputs the amplified voltage difference to the output terminal OUT.

The second input terminal IN 2 of the operational amplifier 420 of the amplifier 310 A or 310 B for an output buffer may be connected to the output terminal OUT.

FIG. 5 is a block diagram of a structure of the operational amplifier 420 illustrated in FIG. 4 , according to one embodiment.

As illustrated in FIG. 5 , the operational amplifier 420 may include an input circuit 510 , an amplifying circuit 520 , and an output circuit 530 .

The input circuit 510 outputs a differential current caused by the voltage difference between the signals applied to the first input terminal IN 1 and the second input terminal IN 2 based on the bias current to which the tail current generated by the self-bias circuit 410 is added. The second input terminal IN 2 of the input circuit 510 is connected to the output terminal OUT of the output circuit 530 . Thus, the input circuit 510 outputs the differential current caused by the voltage difference between an input voltage Vin applied to the first input terminal IN 1 and an output voltage Vout applied to the second input terminal IN 2 . For example, the first input terminal IN 1 may be a positive terminal (+), and the second input terminal IN 2 may be a negative terminal (−). Alternatively, the first input terminal IN 1 may be a negative terminal (−), and the second input terminal IN 2 may be a positive terminal (+).

The amplifying circuit 520 adds the differential current output from the input circuit 510 and amplifies a voltage caused by the added differential current.

The output circuit 530 outputs the output voltage Vout output from the amplifying circuit 520 to the output terminal OUT.

FIG. 6 is a detailed block diagram of the amplifying circuit 520 illustrated in FIG. 5 , according to one embodiment.

As illustrated in FIG. 6 , the amplifying circuit 520 may include a current adding circuit 520 A, a floating current source 520 B, and a class AB control circuit 520 C.

The current adding circuit 520 A adds the differential current output from two pairs of differential transistors of the input circuit 510 .

The floating current source 520 B controls the amplifying circuit 520 to generate a predetermined bias current by receiving a bias voltage.

The class AB control circuit 520 C increases a gain of the operational amplifier 420 .

A detailed circuit structure of the operational amplifier 420 included in the amplifier 310 A or 310 B for an output buffer illustrated in FIG. 4 will now be described.

FIG. 7 illustrates the detailed circuit structure of the operational amplifier 420 of FIG. 4 , according to one embodiment.

The input circuit 510 (see FIG. 5 ) is a folded cascade operational transconductance amplifier (OTA). The folded cascade OTA converts a voltage difference into a current and transmits the current.

The input circuit 510 may include PMOS transistors MP 1 , MP 2 , and MP 3 and NMOS transistors MN 1 , MN 2 , and MN 3 and outputs the differential current by receiving the input voltage Vin and the output voltage Vout.

The input circuit 510 may include a first differential input circuit composed of a PMOS transistor MP 1 and a transistor MP 2 and a second differential input circuit composed of the NMOS transistor MN 1 and the NMOS transistor MN 2 . The PMOS transistor MP 3 and the NMOS transistor MN 3 supply a bias current to the first differential input circuit and the second differential input circuit, respectively.

The PMOS transistor MP 3 applies a first bias current to the first differential input circuit according to a first bias voltage VB 1 , and the NMOS transistor MN 3 applies a second bias current to the second differential input circuit according to a second bias voltage VB 2 .

Each of the first differential input circuit and the second differential input circuit separates the first and second bias current according to a differential input signal and outputs the separated current as a differential current to the current adding circuit 520 A.

That is, the input circuit 510 converts a voltage difference between the input voltage Vin and the output voltage Vout into a current and outputs the current to the current adding circuit 520 A.

Referring to FIGS. 4 through 7 , the input circuit 510 may include a first pair of differential amplifying transistors MP 1 and MP 2 that are connected to a first branch through which a first bias current flows, and a second pair of differential amplifying transistors MN 1 and MN 2 that are connected to a second branch through which a second bias current flows. In this regard, a branch through which the tail current generated by the self-bias circuit 410 flows may be connected in parallel to the first branch or the second branch.

The current adding circuit 520 A is a current mirror circuit composed of PMOS transistors MP 4 , MP 5 , MP 6 , and MP 7 and NMOS transistors MN 4 , MN 5 , MN 6 , and MN 7 .

The current adding circuit 520 A adds the differential current input from the input circuit 510 . The NMOS transistors MN 4 , MN 5 , MN 6 , and MN 7 of the current adding circuit 520 A are connected to the first differential input circuit, and the PMOS transistors MP 4 , MP 5 , MP 6 , and MP 7 are connected to the second differential input circuit.

The PMOS transistor MP 4 and the PMOS transistor MP 5 are connected in series between a power supply voltage VDD and the floating current source 520 B, and the PMOS transistor MP 6 and the PMOS transistor MP 7 are connected in series between the power supply voltage VDD and the class AB control circuit 520 C. The NMOS transistor MN 4 and the NMOS transistor MN 5 are connected in series between a ground terminal VSS and the floating current source 520 B, and the NMOS transistor MN 6 and the NMOS transistor MN 7 are connected in series between the ground terminal VSS and the class AB control circuit 520 C. A third bias voltage VB 3 is applied to a gate terminal of each of the PMOS transistors MP 4 and MP 6 , and a fourth bias voltage VB 4 is applied to a gate terminal of each of the NMOS transistors MN 4 and MN 6 .

The floating current source 520 B has a configuration in which a PMOS transistor MP 8 and an NMOS transistor MN 8 are connected in parallel. Each of the PMOS transistor MP 8 and the NMOS transistor MN 8 generates a predetermined static bias current by receiving a fifth bias voltage VB 5 and a sixth bias voltage VB 6 , respectively. The floating current source 520 B may be composed of a single current source, instead of the PMOS transistor MP 8 and the NMOS transistor MN 8 .

The class AB control circuit 520 C has a configuration in which PMOS transistors MP 9 and MP 10 are connected in parallel with NMOS transistors MN 9 and MN 10 . A seventh bias voltage VB 7 is applied to a gate terminal of the PMOS transistor MP 9 , and an eighth bias voltage VB 8 is applied to a gate terminal of the NMOS transistor MN 10 . A gate terminal and a drain terminal of each of the NMOS transistor MN 9 and the PMOS transistor MP 10 are connected to each other. Thus, the NMOS transistor MN 9 and the PMOS transistor MP 10 perform an operation of a circuit, such as a diode.

If the NMOS transistor MN 9 and the PMOS transistor MP 10 are not provided, when the operational amplifier 420 is driven with a high voltage, a gain of the operational amplifier 420 is decreased. That is, when the power supply voltage VDD of the operational amplifier 420 is high, a difference between voltages applied to a pull-up node pu and a pull-down node pd increases. This results in increasing a drain-source voltage of each of the PMOS transistor MP 9 and the NMOS transistor MN 10 . An increase in the drain-source voltage causes a breakdown phenomenon of the PMOS transistor MP 9 and the NMOS transistor MN 10 . The breakdown phenomenon results in rapidly decreasing a small signal resistance generated in the drain terminal of each of the PMOS transistor MP 9 and the NMOS transistor MN 10 . Since the small signal resistance is proportional to a gain of an amplifier, a decrease in the small signal resistance is related with a decrease in the gain of the amplifier.

Thus, when the NMOS transistor MN 9 is connected to the NMOS transistor MN 10 in series and the PMOS transistor MP 10 is connected to the PMOS transistor MP 9 in series, the difference between the voltages applied to the pull-up node pu and the pull-down node pd may be dispersed. This results in decreasing the drain-source voltage of each of the PMOS transistors MP 9 and MP 10 and the NMOS transistors MN 9 and MN 10 so that the small signal resistance may be increased. An increase in the small signal resistance is related with an increase in the gain of the amplifier so that the gain of the operational amplifier 420 may be boosted.

In addition, when a large gain is generated by the operational amplifier 420 , the NMOS transistor MN 9 and the PMOS transistor MP 10 prevent an output voltage from being distorted due to parasitic capacitance components between peripheral circuits.

The output circuit 530 may include capacitors C 1 and C 2 , a PMOS transistor MP 11 , and an NMOS transistor MN 11 . The output circuit 530 generates an output signal by receiving an amplified voltage output from the class AB control circuit 520 C. The capacitors C 1 and C 2 stabilize frequency characteristics of the output signal. That is, the capacitors C 1 and C 2 may prevent the output signal from oscillating.

A source terminal of the PMOS transistor MP 11 of the output circuit 530 is connected to the power supply voltage VDD, a gate terminal of the PMOS transistor MP 11 of the output circuit 530 is connected to the pull-up node pu, and a drain terminal of the PMOS transistor MP 11 of the output circuit 530 is connected to the output terminal OUT and a drain terminal of the NMOS transistor MN 11 . A source terminal of the NMOS transistor MN 11 is connected to the ground terminal VSS, a gate terminal of the NMOS transistor MN 11 is connected to the pull-down node pd, and the drain terminal of the NMOS transistor MN 11 is connected to the output terminal OUT and the drain terminal of the PMOS transistor MP 11 .

The above-described input circuit 510 is biased by the first and second bias voltages VB 1 and VB 2 so that a slew rate of an amplifier for an output buffer may be expressed as Equation 1:

Slew Rate=( I DCbias )/ C c   (1)

where I DCbias is a DC bias current value that is generated by the first or second bias voltage VB 1 or VB 2 , and C c is a capacitance value of the capacitor C 1 or C 2 of the output circuit 530 .

The present disclosure provides a scheme for improving a slew rate of the amplifier for an output buffer by combining the self-bias circuit 410 with the operational amplifier 420 , as illustrated in FIG. 4 .

FIG. 8 is a block diagram of a structure of the self-bias circuit 410 illustrated in FIG. 4 , according to one embodiment.

As illustrated in FIG. 8 , the self-bias circuit 410 includes a circuit that generates first and second current paths 810 X and 810 Y, and first and second current mirror circuits 820 X and 820 Y.

Each of the first and second current paths 810 X and 810 Y is formed between a power rail VDD (e.g., power supply voltage VDD) and a ground rail VSS (e.g., ground terminal VSS). Each of the first and second current paths 810 X and 810 Y is connected to the first input terminal IN 1 and the second input terminal IN 2 of the operational amplifier 420 . Since the second input terminal IN 2 of the operational amplifier 420 of the amplifier for an output buffer is connected to the output terminal OUT, a voltage of the signal applied to the second input terminal IN 2 is the output voltage Vout output from the output terminal OUT, and a voltage of the signal applied to the first input terminal IN 1 is the input voltage Vin.

In one embodiment, on each of the first and second current paths 810 X and 810 Y, a plurality of transistors may be connected between the power rail VDD and the ground rail VSS in a cascade structure, and at least one pair of an NMOS transistor and a PMOS transistor may be designed to share a source terminal in the cascade structure. For example, the first input terminal IN 1 may be connected to a gate terminal of the NMOS transistor included in the pair of an NMOS transistor and a PMOS transistor that share the source terminal, and the second input terminal IN 2 may be connected to a gate terminal of the PMOS transistor included in the pair of an NMOS transistor and a PMOS transistor that share the source terminal. In addition, the second input terminal IN 2 may be connected to a gate terminal of the NMOS transistor included in the pair of an NMOS transistor and a PMOS transistor that share the source terminal, and the first input terminal IN 1 may be connected to a gate terminal of the PMOS transistor included in one pair of NMOS transistor and PMOS transistor that share the source terminal.

In another embodiment, on each of the first and second current paths 810 X and 810 Y, a plurality of transistors are connected between the power rail VDD and the ground rail VSS in a cascade structure, and a circuit may be designed to connect the first input terminal IN 1 to a gate terminal of one transistor connected in the cascade structure and to connect the second input terminal IN 2 to a source terminal of the one transistor connected in the cascade structure.

The self-bias circuit 410 may generate a tail current on the first current path 810 X or the second current path 810 Y when a difference between voltages of the signals applied to the first input terminal IN 1 and the second input terminal IN 2 is equal to or greater than a predetermined voltage (e.g., V=Vthn+|Vthp|, Vthn=a threshold voltage of either “an NMOS transistor” or “NMOS transistors” connected to the first input terminal IN 1 , Vthp=a threshold voltage of either “a PMOS transistor” or “PMOS transistors” connected to the second input terminal IN 2 ). When the difference between voltages of the signals applied to the first input terminal IN 1 and the second input terminal IN 2 is less than the predetermined voltage, both the first and second current paths 810 X and 810 Y may be cut off.

The tail current that is generated on the first current path 810 X may be transmitted to the input circuit 510 of the operational amplifier 420 via the first current mirror circuit 820 X, and the tail current that is generated on the second current path 810 Y may be transmitted to the input circuit 510 of the operational amplifier 420 via the second current mirror circuit 820 Y. In detail, the tail currents that are generated on the first and second current paths 810 X and 810 Y may be added to an input bias current that is generated by the input circuit 510 of the operational amplifier 420 via the first and second current mirror circuits 820 X and 820 Y.

Now, circuit structures of the self-bias circuit 410 according to various embodiments will be described in detail.

FIG. 9 illustrates a detailed circuit structure of the self-bias circuit 410 of FIG. 4 that is connected to an input circuit of the operational amplifier of FIG. 4 , according to one embodiment.

The detailed circuit structure of the self-bias circuit 410 that is connected to the input circuit 510 of the operational amplifier 420 illustrated in FIG. 9 will now be described. The input circuit of FIG. 5 is included in FIG. 9 for convenience of explanation.

In one embodiment, on a first current path 810 X′, four transistors, for example, PMOS transistors MP_ 1 X and MP_ 2 X and NMOS transistors MN_ 1 X and MN_ 2 X, are connected between a power rail VDD and a ground rail VSS in a cascade structure.

A source terminal of the PMOS transistor MP_ 1 X is connected to the power rail VDD, a gate terminal and a drain terminal of the PMOS transistor MP_ 1 X are connected to a node nd_ 1 x , a drain terminal of the NMOS transistor MN_ 1 X is connected to the node nd_ 1 x , a source terminal of the NMOS transistor MN_ 1 X is connected to a node nd_ 3 x , a gate terminal of the NMOS transistor MN_ 1 X is connected to the second input terminal IN 2 , a source terminal of the PMOS transistor MP_ 2 X is connected to the node nd_ 3 x , a drain terminal of the PMOS transistor MP_ 2 X is connected to a node nd_ 2 x , a gate terminal of the PMOS transistor MP_ 2 X is connected to the first input terminal IN 1 , a gate terminal and a drain terminal of the NMOS transistor MN_ 2 X are connected to the node nd_ 2 x , and a source terminal of the NMOS transistor MN_ 2 X is connected to the ground rail VSS.

Since the input voltage Vin is applied to the first input terminal IN 1 and the output voltage Vout is applied to the second input terminal IN 2 , the output voltage Vout is applied to the gate terminal of the NMOS transistor MN_ 1 X, and the input voltage Vin is applied to the gate terminal of the PMOS transistor MP 2 x.

In one embodiment, on a second current path 810 Y′, four transistors, for example, PMOS transistors MP_ 1 Y and MP_ 2 Y and NMOS transistors MN_ 1 Y and MN_ 2 Y, are connected between the power rail VDD and the ground rail VSS in a cascade structure.

A source terminal of the PMOS transistor MP_ 1 Y is connected to the power rail VDD, a gate terminal and a drain terminal of the PMOS transistor MP_ 1 Y are connected to a node nd_ 1 y , a drain terminal of the NMOS transistor MN_ 1 Y is connected to the node nd_ 1 y , a source terminal of the NMOS transistor MN_ 1 Y is connected to a node nd_ 3 y , a gate terminal of the NMOS transistor MN_ 1 Y is connected to the second input terminal IN 2 , a source terminal of the PMOS transistor MP_ 2 Y is connected to the node nd_ 3 y , a drain terminal of the PMOS transistor MP_ 2 Y is connected to a node nd_ 2 y , a gate terminal of the PMOS transistor MP_ 2 Y is connected to the first input terminal IN 1 , a gate terminal and a drain terminal of the NMOS transistor MN_ 2 Y are connected to the node nd_ 2 y , and a source terminal of the NMOS transistor MN_ 2 Y is connected to the ground rail VSS.

Since the input voltage Vin is applied to the first input terminal IN 1 and the output voltage Vout is applied to the second input terminal IN 2 , the input voltage Vin is applied to the gate terminal of the NMOS transistor MN_ 1 Y, and the output voltage Vout is applied to the gate terminal of the PMOS transistor MP_ 2 Y.

In one embodiment, a PMOS transistor MP_ 3 X and an NMOS transistor MN_ 3 X of a first current mirror circuit 820 X′ that are combined with the PMOS transistor MP_ 1 X and the NMOS transistor MN_ 2 X of the first current path 810 X′, respectively, add the tail current that is generated on the first current path 810 X′ to an input bias current of the input circuit 510 .

In detail, a source terminal of the PMOS transistor MP_ 3 X is connected to the power rail VDD, a gate terminal of the PMOS transistor MP_ 3 X is connected to the node nd_ 1 x , a drain terminal of the PMOS transistor MP_ 3 X is connected to a node ps, a source terminal of the NMOS transistor MN_ 3 X is connected to the ground rail VSS, a gate terminal of the NMOS transistor MN_ 3 X is connected to the node nd_ 2 x , and a drain terminal of the NMOS transistor MN_ 3 X is connected to a node ns.

The bias current caused by the first bias voltage VB 1 and the tail current that is measured by the PMOS transistor MP_ 3 X are applied to the node ps. Thus, the tail current may be added to the bias current caused by the first bias voltage VB 1 .

The bias current caused by the second bias voltage VB 2 and the tail current that is formed by the NMOS transistor MN_ 3 X are applied to the node ns. Thus, the tail current may be added to the bias current caused by the second bias voltage VB 2 .

In one embodiment, a PMOS transistor MP_ 3 Y and an NMOS transistor MN_ 3 Y of a second current mirror circuit 820 Y′ that are combined with the PMOS transistor MP_ 1 Y and the NMOS transistor MN_ 2 Y of the second current path 810 Y′ add the tail current that is generated on the second current path 810 Y′ to the input bias current of the input circuit 510 .

In detail, a source terminal of the PMOS transistor MP_ 3 Y is connected to the power rail VDD, a gate terminal of the PMOS transistor MP_ 3 Y is connected to the node nd_ 1 y , a drain terminal of the PMOS transistor MP_ 3 Y is connected to the node ps, a source terminal of the NMOS transistor MN_ 3 Y is connected to the ground rail VSS, a gate terminal of the NMOS transistor MN_ 3 Y is connected to the node nd_ 2 y , and a drain terminal of the NMOS transistor MN_ 3 Y is connected to the node ns.

The bias current caused by the first bias voltage VB 1 and the tail current that is formed by the PMOS transistor MP_ 3 Y are applied to the node ps. Thus, the tail current may be added to the bias current caused by the first bias voltage VB 1 .

The bias current caused by the second bias voltage VB 2 and the tail current that is formed by the NMOS transistor MN_ 3 Y are applied to the node ns. Thus, the tail current may be added to the bias current caused by the second bias voltage VB 2 .

Now, an operation of generating the tail current on the first and second current paths 810 X′ and 810 Y′ will be described.

On the first current path 810 X′, if a gate-source voltage Vgs of the NMOS transistor MN_ 1 X is equal to or greater than a threshold voltage Vthn of the NMOS transistor MN_ 1 x , the NMOS transistor MN_ 1 X electrically connects the node nd_ 1 x and the node nd_ 3 x , and if not, the NMOS transistor MN_ 1 X does not electrically connect the node nd_ 1 x , the node nd_ 3 x.

Thus, conditions for electrical connection of the NMOS transistor MN_ 1 X may be expressed as Inequality 2:

V out− Vx≧Vthn   (2),

where Vx is a voltage that is detected from the node nd_ 3 X illustrated in FIG. 9 , and Vthn is a threshold voltage of the NMOS transistor MN_ 1 X.

Conditions for electrical connection of the PMOS transistor MP_ 2 X may be expressed as Inequality 3:

Vx−V in≧| Vthp|   (3),

where Vthp is a threshold voltage of the PMOS transistor MP_ 2 X.

In order to enable electrical connection of the first current path 810 X′, Inequalities 2 and 3 that are conditions for electrical connection of the NMOS transistor MN_ 1 X and the PMOS transistor MP_ 2 X need to be satisfied.

Thus, conditions for electrical connection of the first current path 810 X′ may be expressed as Inequality 4:

V out− V in≧ Vthn+|Vthp|   (4)

On the conditions shown in Equation 5, the first current path 810 X′ is cut off.

V out− V in< Vthn+|Vthp|   (5)

Next, on the second current path 810 Y′, when the gate-source voltage Vgs of the NMOS transistor MN_ 1 Y is equal to or greater than a threshold voltage Vthn of the NMOS transistor MN_ 1 Y, electrical connection of the NMOS transistor MN_ 1 Y is formed, and if not, the NMOS transistor MN_ 1 Y is cut off.

Thus, the NMOS transistor MN_ 1 Y may be expressed as Inequality 6:

Vin−Vy≧Vthn   (6),

where Vy is a voltage that is detected from the node nd_ 3 y illustrated in FIG. 9 , and Vthn is a threshold voltage of the NMOS transistor MN_ 1 Y.

Conditions for electrical connection of the PMOS transistor MP_ 2 Y may be expressed as Inequality 7:

Vy−V out≧| Vthp   (7),

where Vthp is a threshold voltage of the PMOS transistor MP_ 2 Y.

In order to enable electrical connection of the second current path 810 Y′, Inequalities 6 and 7 that are conditions for electrical connection of the NMOS transistor MN_ 1 Y and the PMOS transistor MP_ 2 Y need to be satisfied.

Thus, conditions for electrical connection of the second current path 810 Y′ may be expressed as Inequality 8:

V in− V out≧ Vthn+|Vthp|   (8)

On the conditions shown in Inequality 9, the second current path 810 Y′ is cut off.

V in− V out< Vthn+|Vthp|   (9)

Assuming that an absolute value of the threshold voltage of the PMOS transistors MP_ 2 X and MP_ 2 Y and the threshold voltage of the NMOS transistors MN_ 1 X and MN_ 1 Y are the same as Vth, if a voltage difference between the input voltage Vin and the output voltage Vout is less than 2Vth, both the first and second current paths 810 X′ and 810 Y′ are cut off. If the voltage difference between the input voltage Vin and the output voltage Vout is equal to or greater than 2Vth, selective electrical connection of the first current path 810 X′ or the second current path 810 Y′ is formed.

A current that flows through the first current path 810 X′ or the second current path 810 Y′ electrically connected, may be defined as a tail current. The tail current is added to the input bias current of the input circuit 510 by the transistors MP_ 3 X, MN_ 3 X, MP_ 3 Y, and MN_ 3 Y included in the first and second current mirror circuits 820 X′ and 820 Y′.

A tail current Ix that is generated on the first current path 810 X′, and a tail current Iy that is generated on the second current path 810 Y′ according to the voltage difference between the input voltage Vin and the output voltage Vout of the amplifier for an output buffer that uses the self-bias circuit 410 illustrated in FIG. 9 are illustrated in FIG. 10A .

A current Ibias illustrated in FIG. 10A represents an input bias current that flows through the drain terminal of the NMOS transistor MN 3 according to the second bias voltage VB 2 as a DC bias voltage.

A waveform of the input voltage Vin that is a voltage of a signal input to the first input terminal IN 1 of the amplifier for an output buffer that does not include the self-bias circuit 410 illustrated in FIG. 9 , and a waveform of the output voltage Vout that is a voltage of a signal output to the output terminal OUT of the amplifier for an output buffer that does not include the self-bias circuit 410 of FIG. 9 , are illustrated in FIG. 10B .

A waveform of the tail current Ix that is generated on the first current path 810 X′ and a waveform of the tail current Iy that is generated on the second current path 810 Y′ when the input voltage Vin illustrated in FIG. 10B is input to the first input terminal IN 1 of the amplifier for an output buffer that includes the self-bias circuit 410 illustrated in FIG. 9 , are illustrated in FIG. 10C .

A waveform of the input voltage Vin and a waveform of the output voltage Vout of the amplifier for an output buffer that includes the self-bias circuit 410 illustrated in FIG. 9 are illustrated in FIG. 10D .

Referring to FIGS. 10B and 10D , FIG. 10B illustrates exemplary voltage waveforms of the input signal and the output signal in the amplifier for an output buffer that does not include the self-bias circuit 410 of FIG. 9 , and FIG. 10D illustrates the voltage waveforms of the input signal and the output signal in the amplifier for an output buffer that includes the self-bias circuit 410 of FIG. 9 . The output signal Vout of FIG. 10D may follow the input signal faster than the output signal Vout of FIG. 10B .

In addition, a slew rate of the amplifier for an output buffer that includes the self-bias circuit 410 illustrated in FIG. 9 may be expressed as Equation 10:

Slew Rate=( I DCbias +I tail )/ C c   (10),

where I DCbias is a DC bias current value that is generated by the DC bias voltage VB 1 or VB 2 , I tail is a current that flows through the first current path 810 X′ or the second current path 810 Y′ of the self-bias circuit 410 of FIG. 9 , and C c is a capacitance value of the capacitor C 1 or C 2 of the output circuit 530 .

Referring to Inequality 1 and Equation 10, the slew rate of the amplifier for an output buffer that includes the self-bias circuit 410 of FIG. 9 may be improved compared to the slew rate of the amplifier for an output buffer that does not include the self-bias circuit 410 of FIG. 9 .

FIG. 11 illustrates a detailed circuit structure of the self-bias circuit 410 of FIG. 4 that is connected to the input circuit 510 of the operational amplifier 420 of FIG. 4 , according to another embodiment. The input circuit of FIG. 5 is included in FIG. 11 for convenience of explanation.

In one embodiment, on a first current path 810 X″, three transistors, for example, PMOS transistors MP_ 1 X′ and MP_ 2 X′ and NMOS transistor MN_ 1 X′, are connected between the power rail VDD and the ground rail VSS in a cascade structure.

A source terminal of the PMOS transistor MP_ 1 X′ is connected to the power rail VDD, a gate terminal of the PMOS transistor MP_ 1 X′ is connected to a node nd_ 1 y ′, a drain terminal of the PMOS transistor MP_ 1 X′ is connected to a node nd_ 1 x ′, a source terminal of the PMOS transistor MP_ 2 X′ is connected to the node nd_ 1 x ′, a drain terminal of the PMOS transistor MP_ 2 X′ is connected to a node nd_ 2 x ′, a gate terminal of the PMOS transistor MP_ 2 X′ is connected to the first input terminal IN 1 , a gate terminal and a drain terminal of the NMOS transistor MN_ 1 X′ are connected to the node nd_ 2 x ′, and a source terminal of the NMOS transistor MN_ 1 X′ is connected to the ground rail VSS. The second input terminal IN 2 is connected to the node nd_ 1 x′.

Since the input voltage Vin is applied to the first input terminal IN 1 and the output voltage Vout is applied to the second input terminal IN 2 , the input voltage Vin is applied to the gate terminal of the PMOS transistor MP_ 2 X′, and the output voltage Vout is applied to the node nd_ 1 x ′ as the source terminal of the PMOS transistor MP_ 2 X′.

In one embodiment, on a second current path 810 Y″, three transistors, for example, a PMOS transistor MP_ 1 Y′ and NMOS transistors MN_ 1 Y′ and MN_ 2 Y′, are connected between the power rail VDD and the ground rail VSS in a cascade structure.

A source terminal of the PMOS transistor MP_ 1 Y′ is connected to the power rail VDD, a gate terminal and a drain terminal of the PMOS transistor MP_ 1 Y′ are connected to the node nd_ 1 y ′, a drain terminal of the NMOS transistor MN_ 1 Y′ is connected to the node nd_ 1 y ′, a source terminal of the NMOS transistor MN_ 1 Y′ is connected to a node nd_ 2 y ′, a gate terminal of the NMOS transistor MN_ 1 Y′ is connected to the first input terminal IN 1 , a gate terminal of an NMOS transistor MN_ 2 Y′ is connected to the node nd_ 2 x ′, a drain terminal of the NMOS transistor MN_ 2 Y′ is connected to the node nd_ 2 y ′, and a source terminal of the NMOS transistor MN_ 2 Y′ is connected to the ground rail VSS. The second input terminal IN 2 is connected to the node nd_ 2 y′.

Since the input voltage Vin is applied to the first input terminal IN 1 and the output voltage Vout is applied to the second input terminal IN 2 , the input voltage Vin is applied to a gate terminal of the NMOS transistor MN_ 1 Y′, and the output voltage Vout is applied to the node nd_ 2 Y′ as the source terminal of the NMOS transistor MN_ 1 Y′.

An NMOS transistor MN_ 2 X′ of a first current mirror circuit 820 X″ that is combined with the NMOS transistor MN_ 1 X′ of the first current path 810 X″ adds the tail current that is generated on the first current path 810 X″ to the input bias current of the input circuit 510 .

In detail, a source terminal of the NMOS transistor MN_ 2 X′ is connected to the ground rail VSS, a gate terminal of the NMOS transistor MN_ 2 X′ is connected to the node nd_ 2 x ′, and a drain terminal of the NMOS transistor MN_ 2 X′ is connected to a node ns.

A bias current caused by the second bias voltage VB 2 and a tail current that is metered by the NMOS transistor MN_ 2 X′ are applied to the node ns. Thus, the tail current may be added to the bias current caused by the second bias voltage VB 2 .

In one embodiment, a PMOS transistor MP_ 2 Y′ of a second current mirror circuit 820 Y″ that is combined with the PMOS transistor MP_ 1 Y′ of the second current path 810 Y″ adds the tail current that is generated on the second current path 810 Y″ to the input bias current of the input circuit 510 .

In detail, a source terminal of the PMOS transistor MP_ 2 Y′ is connected to the power rail VDD, a gate terminal of the PMOS transistor MP_ 2 Y′ is connected to the node nd_ 1 y ′, and a drain terminal of the PMOS transistor MP_ 2 Y′ is connected to a node ps.

A bias current caused by the first bias voltage VB 1 and a tail current that is metered by the PMOS transistor MP_ 2 Y′ are applied to the node ps. Thus, the tail current may be added to the bias current caused by the first bias voltage VB 1 .

On the first current path 810 X″, electrical connection of the PMOS transistor MP_ 2 X′ is formed when conditions shown in Inequality 11 are satisfied.

V out− V in≧| Vthp|   (11),

where Vthp is a threshold voltage of the PMOS transistor MP_ 2 X′.

On the second current path 810 Y″, electrical connection of the NMOS transistor MN_ 1 Y′ is formed when conditions shown in Inequality 12 are satisfied.

V in− V out≧ Vthn   (12),

where Vthn is a threshold voltage of the NMOS transistor MN_ 1 Y′.

Assuming that an absolute value of a threshold voltage of the PMOS transistor MP_ 2 X′ and a threshold voltage of the NMOS transistor MN_ 1 Y′ are the same as Vth, if a voltage difference between the input voltage Vin and the output voltage Vout is less than Vth, both the first and second current paths 810 X″ and 810 Y″ are cut off. If the voltage difference between the input voltage Vin and the output voltage Vout is equal to or greater than Vth, selective electrical connection of the first current path 810 X″ or the second current path 810 Y″ is formed.

If electrical connection of the first current path 810 X″ or the second current path 810 Y″ is formed, the tail current flows through the first current path 810 X″ or the second current path 810 Y″. The tail current is added to the input bias current of the input circuit 510 by the PMOS transistors MP_ 2 X′ and MP_ 2 Y′ included in the first and second current mirror circuits 820 X″ and 820 Y″.

A tail current Ix′ that is generated on the first current path 810 X″, and a tail current Iy′ that is generated on the second current path 810 Y″ according to the voltage difference between the input voltage Vin and the output voltage Vout of the amplifier for an output buffer that uses the self-bias circuit 410 illustrated in FIG. 11 are illustrated in FIG. 12A .

A current Ibias illustrated in FIG. 12A represents an input bias current that flows through the drain terminal of the PMOS transistor MP 3 by the first bias voltage VB 1 as a DC bias voltage, or an input bias current that flows through the drain terminal of the NMOS transistor MN 3 by the second bias voltage VB 2 .

A waveform of the input voltage Vin that is a voltage of a signal input to the first input terminal IN 1 of the amplifier for an output buffer that does not include the self-bias circuit 410 illustrated in FIG. 11 , and a waveform of the output voltage Vout that is a voltage of a signal output to the output terminal OUT of the amplifier for an output buffer that does not include the self-bias circuit 410 of FIG. 11 are illustrated in FIG. 12B .

A waveform of the tail current Ix′ that is generated on the first current path 810 X″ and a waveform of the tail current Iy′ that is generated on the second current path 810 Y″ when the input voltage Vin illustrated in FIG. 12B is input to the first input terminal IN 1 of the amplifier for an output buffer that includes the self-bias circuit 410 illustrated in FIG. 11 are illustrated in FIG. 12C .

A waveform of the input voltage Vin and a waveform of the output voltage Vout of the amplifier for an output buffer that includes the self-bias circuit 410 illustrated in FIG. 11 are illustrated in FIG. 12D .

Referring to FIGS. 12B and 12D , FIG. 12B illustrates exemplary voltage waveforms of the input signal and the output signal in the amplifier for an output buffer that does not include the self-bias circuit 410 of FIG. 11 , and FIG. 12D illustrate the voltage waveforms of the input signal and the output signal, in the amplifier for an output buffer that includes the self-bias circuit 410 of FIG. 11 . The output signal Vout of FIG. 12D may follow the input signal faster than the output signal Vout OF FIG. 12B .

The slew rate of the amplifier for an output buffer may be improved by the tail current Ix′ that is generated on the first current path 810 X″ and the tail current Iy′ that is generated on the second current path 810 Y″.

The self-bias circuit 410 that is implemented with MOS transistors is illustrated in FIGS. 9 and 11 , however, the self-bias circuit 410 may be implemented with bipolar transistors.

As described above, in one embodiment, one or more of the circuits described above may be used in a system that includes a display panel. For example, the various described embodiments could be used in a smart phone, a tablet, a laptop computer, a television, or other device that uses a display panel. The display panel may be, for example, an LCD, LED, or other type of display panel.

While the disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.