Method of manufacturing solar cell

This application is a continuation application of International Application No. PCT/JP2011/0067274, filed on Jul. 28, 2011, entitled “METHOD OF MANUFACTURING SOLAR CELL”, which claims priority based on Article 8 of Patent Cooperation Treaty from prior Japanese Patent Applications No. 2010-173598, filed on Aug. 2, 2010, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

This disclosure relates to a method of manufacturing a solar cell, and more particularly relates to a method of manufacturing a back contact solar cell.

2. Description of Related Art

There has heretofore been known so-called aback contact solar cell which has p-type and n-type semiconductor regions formed on aback surface side of the solar cell and has no electrodes formed on a light-receiving surface side (for example, Patent Document 1 below). In this back contact solar cell, no electrodes need to be provided on the light-receiving surface side. Thus, the back contact solar cell can improve light reception efficiency. Therefore, higher power generation efficiency can be achieved. Moreover, connection of the solar cell by wiring can be performed only on the back surface side. Thus, wide wiring materials can be used, which can prevent a voltage drop due to wiring to connect multiple solar cells by use of wiring materials.

Patent Document 1: Japanese Patent Application Publication No. 2005-101240

As described above, the back contact solar cell described in Patent Document 1 can achieve high power generation efficiency. However, there is also a demand for further improvement of the power generation efficiency of the solar cell.

An embodiment of the invention has been made in consideration of the foregoing circumstances. An object of an embodiment of the invention is to provide a method of manufacturing a solar cell having improved power generation efficiency.

In a method of manufacturing a solar cell according to an aspect of the invention, a semiconductor substrate is prepared, which has first and second main surfaces and has a first semiconductor layer formed on the first main surface, the first semiconductor layer being made of a semiconductor having one of p-type conductivity and n-type conductivity. An insulating layer is formed so as to cover a portion of the first semiconductor layer. A portion of the first semiconductor layer, which is not covered with the insulating layer, is removed by etching with an etchant, thereby exposing a portion of the first main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is cleaned using a cleaning liquid containing hydrofluoric acid. A second semiconductor layer made of a semiconductor having the other conductivity of the p-type conductivity and n-type conductivity is formed on the exposed portion of the first main surface of the semiconductor substrate. Then, electrodes are formed on the first and second semiconductor layers, respectively. The insulating layer has a first surface layer, the first surface layer being on the opposite side to the first semiconductor layer, and a second surface layer, the second surface layer being on the first semiconductor layer side. The insulating layer is formed such that an etching rate by the etchant to etch the first semiconductor layer is higher than an etching rate by the etchant to etch the first surface layer of the insulating layer and that an etching rate by the cleaning liquid to etch the second surface layer of the insulating layer is lower than an etching rate by the cleaning liquid to etch the first surface layer of the insulating layer.

The aspect of the invention can provide a method of manufacturing a solar cell having improved power generation efficiency.

FIG. 1 is a schematic plan view of a solar cell according to a first embodiment.

FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. 1 .

FIG. 3 is a flowchart showing steps of manufacturing a solar cell according to the first embodiment.

FIG. 4 is a schematic cross-sectional view for explaining the steps of manufacturing a solar cell.

FIG. 5 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 6 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 7 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 8 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 9 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 10 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 11 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

FIG. 12 is a schematic cross-sectional view for explaining the steps of manufacturing the solar cell.

Preferred embodiment(s) of the invention are described below. However, the following embodiment(s) are provided as examples but are not intended to limit the invention thereto.

Note that, in the drawings to be referred to in the embodiments and the like, members having substantially the same functions are denoted by the same reference numerals. In addition, the drawings to be referred to in the embodiments and the like are schematic and ratios of dimensions and the like are different from actual ones. Moreover, the drawings also include portions having different dimensional relationships and ratios from each other. Therefore, specific dimensions and the like should be determined in consideration of the following description.

First Embodiment

Configuration of Solar Cell 1

First, a configuration of solar cell 1 to be manufactured in this embodiment is described in detail with reference to FIGS. 1 and 2 .

Solar cell 1 is a back contact solar cell. Note that when solar cell 1 of this embodiment cannot achieve a sufficiently large output by itself, multiple solar cells 1 may be connected by wiring and used as a solar cell module.

As shown in FIG. 2 , solar cell 1 includes semiconductor substrate 10 . Semiconductor substrate 10 has light-receiving surface 10 a as a second main surface and back surface 10 b as a first main surface. Semiconductor substrate 10 receives light 11 on light-receiving surface 10 a to generate carriers. Here, the carriers are holes and electrons to be generated by semiconductor substrate 10 absorbing light.

Semiconductor substrate 10 is formed of a crystalline semiconductor substrate having n-type or p-type conductivity. Specific examples of the crystalline semiconductor substrate include crystalline silicon substrates such as a single-crystal silicon substrate and a polycrystalline silicon substrate, for example.

Note that the semiconductor substrate can also be formed of a semiconductor substrate other than the crystalline semiconductor substrate. For example, a compound semiconductor substrate made of GaAs, InP or the like can be used in place of semiconductor substrate 10 . In this embodiment, description is given below of an example where semiconductor substrate 10 is formed using an n-type single-crystal silicon substrate.

On light-receiving surface 10 a of semiconductor substrate 10 , i-type amorphous semiconductor layer 17 i is formed, which is made of an intrinsic amorphous semiconductor (the intrinsic semiconductor is hereinafter referred to as the “i-type semiconductor”). To be more specific, in this embodiment, i-type amorphous semiconductor layer 17 i is formed of i-type amorphous silicon containing hydrogen. The thickness of i-type amorphous semiconductor layer 17 i is not particularly limited as long as it does not substantially contribute to power generation. The thickness of i-type amorphous semiconductor layer 17 i can be set to, for example, about several Å to 250 Å.

Note that, in the invention, the “amorphous semiconductor” includes a microcrystalline semiconductor. The microcrystalline semiconductor is a semiconductor in which an average particle size of semiconductor crystal deposited in the amorphous semiconductor is in the range of 1 nm to 50 nm.

On i-type amorphous semiconductor layer 17 i , n-type amorphous semiconductor layer 17 n is formed, which has the same conductivity as that of semiconductor substrate 10 . N-type amorphous semiconductor layer 17 n is an amorphous semiconductor layer which is doped with an n-type dopant and has the n-type conductivity. To be more specific, in this embodiment, n-type amorphous semiconductor layer 17 n is made of n-type amorphous silicon containing hydrogen. The thickness of n-type amorphous semiconductor layer 17 n is not particularly limited. The thickness of n-type amorphous semiconductor layer 17 n can be set to, for example, about 20 Å to 500 Å.

On n-type amorphous semiconductor layer 17 n , insulating layer 16 is formed, which serves both as an antireflection film and as a protective film. Insulating layer 16 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride or the like. The thickness of insulating layer 16 can be set according to antireflection properties and the like of the antireflection film to be provided. The thickness of insulating layer 16 can be set to, for example, about 80 nm to 1 μm. The laminate structure of i-type amorphous semiconductor layer 17 i , n-type amorphous semiconductor layer 17 n and insulating layer 16 described above functions as a passivation layer and as an antireflection film for semiconductor substrate 10 .

On back surface 10 b of semiconductor substrate 10 , IN laminate 12 and IP laminate 13 are formed. As shown in FIG. 1 , each of IN laminate 12 and IP laminate 13 is formed in a comb-teeth shape. IN laminate 12 and IP laminate 13 are configured to mesh with each other. Thus, on back surface 10 b , IN laminate 12 and IP laminate 13 are alternately arranged along direction x perpendicular to intersection width direction y. IN laminate 12 and IP laminate 13 which are adjacent to each other in direction x are in contact with each other. More specifically, in this embodiment, substantially the entire back surface 10 b is covered with IN laminate 12 and IP laminate 13 . Note that width W 1 (see FIG. 2 ) of IN laminate 12 and interval W 2 of IN laminate 12 in direction x can be set to, for example, about 100 μm to 1.5 mm, respectively. Width W 1 and interval W 2 may be equal to or different from each other.

IN laminate 12 is a laminate including i-type amorphous semiconductor layer 12 i formed on back surface 10 b and n-type amorphous semiconductor layer 12 n formed on i-type amorphous semiconductor layer 12 i . As in the case of i-type amorphous semiconductor layer 17 i described above, i-type amorphous semiconductor layer 12 i is made of i-type amorphous silicon containing hydrogen. The thickness of i-type amorphous semiconductor layer 12 i is not particularly limited as long as it does not substantially contribute to power generation. The thickness of i-type amorphous semiconductor layer 12 i can be set to, for example, about several Å to 250 Å.

As in the case of n-type amorphous semiconductor layer 17 n described above, n-type amorphous semiconductor layer 12 n is doped with an n-type dopant and has the same n-type conductivity as that of semiconductor substrate 10 . To be more specific, in this embodiment, n-type amorphous semiconductor layer 12 n is made of n-type amorphous silicon containing hydrogen. The thickness of n-type amorphous semiconductor layer 12 n is not particularly limited. The thickness of n-type amorphous semiconductor layer 12 n can be set to, for example, about 20 Å to 500 Å.

Insulating layer 18 is formed on both end portions of IN laminate 12 in direction x except for a center portion thereof. The center portion of IN laminate 12 in direction x is exposed from insulating layer 18 . Width W 3 of insulating layer 18 in direction x is not particularly limited and may be set to, for example, about ⅓ of width W 1 . Moreover, interval W 4 between insulating layers 18 in direction x is also not particularly limited but can be set to, for example, about ⅓ of width W 1 .

In this embodiment, insulating layer 18 is formed of silicon nitride. However, the material of insulating layer 18 is not particularly limited. Insulating layer 18 may be formed of, for example, silicon oxide, silicon oxynitride or the like. Also, insulating layer 18 may contain hydrogen.

IP laminate 13 is formed on a portion of back surface 10 b exposed from IN laminate 12 and on end portions of insulating layer 18 . Thus, both end portions of IP laminate 13 overlap with IN laminate 12 in height direction z.

IP laminate 13 is a laminate including i-type amorphous semiconductor layer 13 i formed on back surface 10 b and p-type amorphous semiconductor layer 13 p formed on i-type amorphous semiconductor layer 13 i.

I-type amorphous semiconductor layer 13 i is made of i-type amorphous silicon containing hydrogen. The thickness of i-type amorphous semiconductor layer 13 i is not particularly limited as long as it does not substantially contribute to power generation. The thickness of i-type amorphous semiconductor layer 13 i can be set to, for example, about several Å to 250 Å.

p-type amorphous semiconductor layer 13 p is an amorphous semiconductor layer which is doped with a p-type dopant and has a p-type conductivity. To be more specific, in this embodiment, p-type amorphous semiconductor layer 13 p is made of p-type amorphous silicon containing hydrogen. The thickness of p-type amorphous semiconductor layer 13 p is not particularly limited. The thickness of p-type amorphous semiconductor layer 13 p can be set to, for example, about 20 Å to 500 Å.

As described above, this embodiment has a structure in which i-type amorphous semiconductor layer 13 i having the thickness that does not substantially contribute to power generation is provided between crystalline semiconductor substrate 10 and p-type amorphous semiconductor layer 13 p . By adopting such a structure in this embodiment, minority carriers can be prevented from being recombined at the junction interface between semiconductor substrate 10 and IN laminate 12 and IP laminate 13 . As a result, photoelectric conversion efficiency can be improved.

Note that it is preferable that amorphous semiconductor layers 17 , 12 and 13 contain hydrogen.

On n-type amorphous semiconductor layer 12 n , n-side electrode 14 is formed to collect electrons. On the other hand, on p-type amorphous semiconductor layer 13 p , p-side electrode 15 is formed to collect holes. P-side electrode 15 and n-side electrode 14 are electrically insulated from each other. Note that distance W 5 between n-side electrode 14 and p-side electrode 15 on insulating layer 18 can be set to, for example, about ⅓ of width W 3 .

As described above, in this embodiment, each of IN laminate 12 and IP laminate 13 is formed in the comb-teeth shape. Thus, each of n-side electrode 14 and p-side electrode 15 is formed in a comb-teeth shape including bus bars and multiple fingers. However, each of n-side electrode 14 and p-side electrode 15 may be a so-called bus bar-less electrode including only multiple fingers and having no bus bar.

n-side electrode 14 and p-side electrode 15 are not particularly limited as long as they can collect carriers. In this embodiment, each of n-side electrode 14 and p-side electrode 15 includes a laminate of first to fourth conductive layers 19 a to 19 d.

First conductive layer 19 a can be formed of TCO (Transparent Conductive Oxide) or the like, such as ITO (indium tin oxide), for example. To be more specific, in this embodiment, first conductive layer 19 a is formed of ITO. The thickness of first conductive layer 19 a can be set to, for example, about 50 to 100 nm.

Second to fourth conductive layers 19 b to 19 d can be formed of metal or alloy such as Cu, for example. To be more specific, in this embodiment, second and third conductive layers 19 b and 19 c are formed of Cu, respectively. Fourth conductive layer 19 d is formed of Sn. The thicknesses of second to fourth conductive layers 19 b to 19 d can be set to, for example, about 50 nm to 1 μm, about 10 μm to 20 μm, and about 1 μm to 5 μm, respectively.

Note that a method for forming first to fourth conductive layers 19 a to 19 d is not particularly limited but can be formed using a thin-film formation method, such as a sputtering method and a CVD method, a plating method or the like, for example. To be more specific, in this embodiment, first and second conductive layers 19 a and 19 b are formed using the thin-film formation method, and third and fourth conductive layers 19 c and 19 d are formed using the plating method.

Next, a method of manufacturing solar cell 1 of this embodiment is described mainly with reference to FIGS. 3 to 12 .

First, semiconductor substrate 10 (see FIGS. 4 and 2 ) is prepared. Next, as shown in FIG. 3 , light-receiving surface 10 a and back surface 10 b of semiconductor substrate 10 are cleaned in Step S 1 . Semiconductor substrate 10 can be cleaned using, for example, an HF solution or the like. Note that, in this Step S 1 , a texture structure is formed on light-receiving surface 10 a.

Next, in Step S 2 , i-type amorphous semiconductor layer 17 i and n-type amorphous semiconductor layer 17 n are formed on light-receiving surface 10 a of semiconductor substrate 10 , and i-type amorphous semiconductor layer 21 and n-type amorphous semiconductor layer 22 are formed on back surface 10 b . A method for forming i-type amorphous semiconductor layers 17 i and 21 as well as n-type amorphous semiconductor layers 17 n and 22 is not particularly limited. I-type amorphous semiconductor layers 17 i and 21 as well as n-type amorphous semiconductor layers 17 n and 22 may be formed using, for example, a CVD (Chemical Vapor Deposition) method, such as a plasma CVD method, or the like.

Then, in Step S 3 , insulating layer 16 is formed on n-type amorphous semiconductor layer 17 n , and insulating layer 23 is formed on n-type amorphous semiconductor layer 22 . Note that insulating layer 16 is formed so as to cover substantially the entire n-type amorphous semiconductor layer 17 n , while insulating layer 23 is formed so as to cover a part of n-type amorphous semiconductor layer 22 , using a metal mask or the like, for example. Note that insulating layer 23 may be formed by etching a part of an insulating layer formed covering substantially the entire n-type amorphous semiconductor layer 22 .

In this embodiment, as insulating layer 23 , a laminate of first insulating layer 23 a and second insulating layer 23 b is formed. First and second insulating layers 23 a and 23 b are formed such that a ratio of Si to N (Si/N) is smaller in second insulating layer 23 b than in first insulating layer 23 a . Thus, the ratio of Si to N (Si/N) in first surface layer 23 A of insulating layer 23 , first surface layer 23 A being on the side opposite to n-type amorphous semiconductor layer 22 , is smaller than that in second surface layer 23 B of insulating layer 23 , second surface layer 23 B being on n-type amorphous semiconductor layer 22 side. To be more specific, it is preferable that first and second insulating layers 23 a and 23 b are formed such that first insulating layer 23 a has a refractive index of 2.1 to 2.3 and second insulating layer 23 b has a refractive index of 1.9 to 2.1.

Note that control of the ratio of Si to N (Si/N) in first and second insulating layers 23 a and 23 b can be performed by adjusting a ratio between an N source gas and a Si source gas to be supplied when first and second insulating layers 23 a and 23 b are formed using the CVD (Chemical Vapor Deposition) method, such as the plasma CVD method. To be more specific, when thin film formation using the CVD method is performed by supplying, for example, SiH 4 gas and NH 3 gas as the N source gas, the ratio of Si to N (Si/N) can be controlled by adjusting a flow ratio between SiH 4 gas and NH 3 gas.

Next, in Step S 4 , using insulating layer 23 as a mask, i-type amorphous semiconductor layer 21 and n-type amorphous semiconductor layer 22 are etched with an alkaline etchant including NaOH, KOH or the like. Thus, portions of i-type amorphous semiconductor layer 21 and n-type amorphous semiconductor layer 22 , other than those covered with insulating layer 23 are removed. Accordingly, a portion of back surface 10 b , above which no insulating layer 23 is located, is exposed, and i-type amorphous semiconductor layer 12 i and n-type amorphous semiconductor layer 12 n (see FIG. 2 ) are formed using semiconductor layers 21 and 22 .

Next, in Step S 5 , back surface 10 b of semiconductor substrate 10 is cleaned using a cleaning liquid that contains hydrofluoric acid.

Here, in this embodiment, first and second insulating layers 23 a and 23 b are formed such that the ratio of Si to N (Si/N) is smaller in second insulating layer 23 b than in first insulating layer 23 a . Thus, the alkaline etchant including NaOH, KOH or the like, which is used in Step S 4 , has a higher etching rate to etch n-type amorphous semiconductor layer 22 than that to etch insulating layer 23 b . For this reason, in Step S 4 , second insulating layer 23 b remains, and favorably protects the portions of n-type amorphous semiconductor layer 22 and i-type amorphous semiconductor layer 21 which are covered with insulating layer 23 .

On the other hand, second insulating layer 23 b is etched at a high etching rate by the cleaning liquid containing hydrofluoric acid used in Step S 5 . Thus, as shown in FIG. 7 , second insulating layer 23 b disappears in Step S 5 . However, the etching rate by the cleaning liquid to etch first insulating layer 23 a having large Si/N is lower than the etching rate by the cleaning liquid to etch second insulating layer 23 b . For this reason, first insulating layer 23 a is slightly soluble in the cleaning liquid containing hydrofluoric acid. Therefore, first insulating layer 23 a is unlikely to disappear in Step S 5 .

Note that, from the viewpoint of more favorable etching of n-type amorphous semiconductor layer 22 and i-type amorphous semiconductor layer 21 , the etching rate to etch n-type amorphous semiconductor layer 22 is preferably 1.1 times or more larger, more preferably 5 times or more larger, still more preferably 10 times or more larger of the etching rate to etch insulating layer 23 b.

Moreover, the cleaning liquid used in Step S 5 has an etching rate to etch first insulating layer 23 a that is preferably 5 times or more larger, more preferably 10 times or more larger of the etching rate to etch second insulating layer 23 b.

Next, in Step S 6 , i-type amorphous semiconductor layer 24 and p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover back surface 10 b . In this embodiment, since back surface 10 b of semiconductor substrate 10 is cleaned in Step S 5 , semiconductor substrate 10 and i-type amorphous semiconductor layer 24 can be favorably joined. Thus, high photoelectric conversion efficiency can be achieved.

Note that a method for forming amorphous semiconductor layers 24 and 25 is not particularly limited. Amorphous semiconductor layers 24 and 25 can be formed using the thin-film formation method such as the sputtering method and the CVD method, for example.

Thereafter, in Step S 7 , portions of amorphous semiconductor layers 24 and 25 , which are located on first insulating layer 23 a , are partially etched. Thus, i-type amorphous semiconductor layer 13 i and p-type amorphous semiconductor layer 13 p are formed from amorphous semiconductor layers 24 and 25 .

This Step S 7 uses an etchant having a higher etching rate for amorphous semiconductor layers 24 and 25 than the etching rate to etch first insulating layer 23 a . For this reason, amorphous semiconductor layers 24 and 25 are selectively etched among first insulating layer 23 a and amorphous semiconductor layers 24 and 25 .

It is preferable that the etching rate by the first etchant to etch amorphous semiconductor layers 24 and 25 is 1.1 times or more larger, preferably 1.5 times or more larger, more preferably twice or more larger of the etching rate to etch first insulating layer 23 a . Furthermore, it is preferable that the first etchant should etch amorphous semiconductor layers 24 and 25 while not substantially etching first insulating layer 23 a . Specific examples of such first etchant, for a case where amorphous semiconductor layers 24 and 25 are made of silicon and first insulating layer 23 a is made of silicon oxide, silicon nitride or silicon oxynitride, include an alkaline aqueous solution such as an NaOH solution containing NaOH and a KOH solution containing KOH, TMAH (tetramethylammonium hydroxide), and the like, for example. Moreover, the first etchant does not always have to be a liquid, i.e., an etching liquid. The first etchant may be a gas, for example. Specific examples of an etching gas preferably used as the first etchant include Cl 2 gas, CF 4 gas, SF 6 gas, HBr gas and the like, for example.

Note that the “etchant” in the invention includes an etching paste and a viscosity-adjusted etching ink.

Next, as shown in FIG. 3 , first insulating layer 23 a is etched in Step S 8 . To be more specific, an exposed portion of first insulating layer 23 a is removed by etching with an etchant from above amorphous semiconductor layers 13 i and 13 p made of amorphous semiconductor layers 24 and 25 partially removed by the etching in Step S 7 . Thus, n-type amorphous semiconductor layer 12 n is exposed, and insulating layer 18 is formed from first insulating layer 23 a.

This Step S 8 uses a second etchant having a higher etching rate to etch first insulating layer 23 a than the etching rate to etch amorphous semiconductor layers 24 and 25 . For this reason, first insulating layer 23 a is selectively etched among first insulating layer 23 a and amorphous semiconductor layers 24 and 25 .

It is preferable that the etching rate by the second etchant to etch first insulating layer 23 a is 10 times or more larger, preferably 15 times or more larger, more preferably 20 times or more larger, still more preferably 100 times or more larger of the etching rate to etch amorphous semiconductor layers 24 and 25 . Furthermore, it is preferable that the second etchant should etch first insulating layer 23 a while not substantially etching amorphous semiconductor layers 24 and 25 . Specific examples of such second etchant, for a case where amorphous semiconductor layers 24 and 25 are made of silicon and first insulating layer 23 a is made of silicon oxide, silicon nitride or silicon oxynitride, include an HF solution containing HF, an NH 4 F solution, and the like, for example. Moreover, as in the case of the first etchant, the second etchant does not always have to be a liquid, i.e., an etching liquid. The second etchant may be a gas, for example. Specific examples of an etching gas preferably used as the second etchant include CF 4 gas, CHF 3 gas, and the like, for example.

Next, in Step S 9 , solar cell 1 can be completed by performing an electrode formation step to form n-side electrode 14 and p-side electrode 15 on n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p , respectively.

In this embodiment, p-type amorphous semiconductor layer 13 p has a function to form an HIT junction with semiconductor substrate 10 and a function as a mask layer to form a contact hole in insulating layer 18 . In other words, according to this embodiment, the semiconductor layer to form the HIT junction with semiconductor substrate 10 and the mask layer for contact hole formation are formed in the same step. Thus, the manufacturing time can be reduced.

A method for forming n-side electrode 14 and p-side electrode 15 can be selected according to the materials of the electrodes. More specifically, in this embodiment, n-side electrode 14 and p-side electrode 15 are formed as follows.

First, conductive layer 26 made of TCO and conductive layer 27 made of metal or alloy such as Cu are formed in this order using a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a thin-film formation method such as a sputtering method.

Next, as shown in FIG. 12 , portions of conductive layers 26 and 27 , which are positioned above insulating layer 18 , are divided. Thus, first and second conductive layers 19 a and 19 b are formed from conductive layers 26 and 27 . Note that the division of conductive layers 26 and 27 can be performed using, for example, a photolithography method or the like.

Next, third conductive layer 19 c made of Cu and fourth conductive layer 19 d made of Sn are sequentially formed by electrolytic plating on first and second conductive layers 19 a and 19 b formed on n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p . Thus, n-side electrode 14 and p-side electrode 15 shown in FIG. 2 can be completed.

Meanwhile, it is also conceivable that the insulating layer positioned on the semiconductor layer formed on the back surface of the semiconductor substrate is integrally formed of silicon nitride having a substantially constant Si/N. However, in such a case, the insulating layer becomes soluble in the alkaline etchant for etching the semiconductor layer or the cleaning liquid containing hydrofluoric acid. For example, when the insulating layer is soluble in the alkaline etchant, the insulating layer disappears in the etching step of the semiconductor layer, and the semiconductor layer sometimes cannot be favorably patterned. On the other hand, when the insulating layer is soluble in the cleaning liquid containing hydrofluoric acid, the insulating layer disappears in the cleaning step of the back surface of the semiconductor substrate. This makes it difficult to accurately form the n-side or p-side electrode on each of the n-type semiconductor layer and the p-type semiconductor layer. To be more specific, when the insulating layer has disappeared, the n-side and p-side electrodes need to be formed by the thin-film formation step using a metal mask. However, it is difficult to arrange the metal mask with high positional accuracy. This makes it difficult to reduce the pitch between the n-side and p-side electrodes. For this reason, the increased pitch between the n-side and p-side electrodes makes minority carriers likely to be recombined. As a result, it becomes difficult to achieve high photoelectric conversion efficiency.

On the other hand, in this embodiment, the etchant used in Step S 4 has a higher etching rate to etch n-type amorphous semiconductor layer 22 is higher than the etching rate to etch second insulating layer 23 b . Moreover, the cleaning liquid has a lower etching rate to etch first insulating layer 23 a than the etching rate to etch second insulating layer 23 b . Therefore, etching of n-type amorphous semiconductor layer 22 and cleaning of back surface 10 b can be favorably performed. Moreover, second insulating layer 23 b remains even after the etching step of Step S 4 and the cleaning step of Step S 5 . Thus, using second insulating layer 23 b , n-side electrode 14 and p-side electrode 15 can be formed with high positional accuracy and with a narrow pitch. As a result, solar cell 1 having improved power generation efficiency can be manufactured.

Particularly, in this embodiment, the entire back surface 10 b is covered with n-type amorphous semiconductor layer 12 n or p-type amorphous semiconductor layer 13 p . Thus, higher photoelectric conversion efficiency can be achieved.

In this embodiment, insulating layer 23 is formed of silicon nitride. Thus, insulating layer 18 formed of insulating layer 23 has high gas barrier properties. Therefore, solar cell 1 having excellent weather resistance can be manufactured.

In this embodiment, insulating layer 18 is formed on one of n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p , i.e., on n-type amorphous semiconductor layer 12 n . In other words, the semiconductor layer positioned below insulating layer 18 is n-type amorphous semiconductor layer 12 n . Moreover, p-side electrode 15 is formed on substantially the entire p-type amorphous semiconductor layer 13 p . Thus, holes which are the minority carriers are likely to be collected in p-side electrode 15 . Therefore, the photoelectric conversion efficiency of solar cell 1 obtained can be further improved.

However, when the semiconductor substrate has the p-type conductivity, the minority carriers are electrons. Thus, it is preferable that the first semiconductor layer positioned below the insulating layer is formed of a p-type semiconductor.

Moreover, in this embodiment, p-type amorphous semiconductor layer 13 p is formed such that back surface 10 b of semiconductor substrate 10 made of the crystalline semiconductor is substantially entirely covered with n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p . Thus, back surface 10 b of semiconductor substrate 10 made of the crystalline semiconductor is substantially not exposed. Therefore, holes which are the minority carriers are unlikely to be recombined in back surface 10 b of semiconductor substrate 10 . Thus, the photoelectric conversion efficiency of solar cell 1 obtained can be further improved.

In this embodiment, after the division of first and second conductive layers 19 a and 19 b formed by the thin-film formation method, third and fourth conductive layers 19 c and 19 d are formed by plating. Thus, division of the electrodes can be performed more easily and quickly compared with the case where, for example, all first to fourth conductive layers 19 a to 19 d are formed and then divided into n-side electrode 14 and p-side electrode 15 .

Moreover, since the division of first and second conductive layers 19 a and 19 b is performed on insulating layer 18 , n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p are unlikely to be damaged during the division of first and second conductive layers 19 a and 19 b.

Furthermore, in this embodiment, insulating layer 18 , n-side electrode 14 and p-side electrode 15 are formed such that n-type amorphous semiconductor layer 12 n and p-type amorphous semiconductor layer 13 p are substantially entirely covered with insulating layer 18 , n-side electrode 14 and p-side electrode 15 . Therefore, according to the manufacturing method of this embodiment, solar cell 1 having more excellent gas barrier properties and weather resistance can be manufactured.

Note that, in the first embodiment described above, the description has been given of the example where insulating layer 23 is formed using the laminate of first and second insulating layers 23 a and 23 b which are different in Si/N. However, the invention is not limited to such a configuration. For example, insulating layer 23 may be formed of a single silicon nitride layer having Si/N gradually increased from first surface layer 23 A side toward second surface layer 23 B, for example. Such insulating layer 23 can be formed by gradually changing the flow ratio between SiH 4 gas and NH 3 gas during formation of insulating layer 23 by the CVD method, for example.

1 solar cell

10 semiconductor substrate

10 a light-receiving surface

10 b back surface

11 light

12 IN laminate

12 i i-type amorphous semiconductor layer

12 n n-type amorphous semiconductor layer

13 IP laminate

13 i i-type amorphous semiconductor layer

13 p p-type amorphous semiconductor layer

14 n-side electrode

15 p-side electrode

16 insulating layer

17 i i-type amorphous semiconductor layer

17 n n-type amorphous semiconductor layer

18 insulating layer

19 a first conductive layer

19 b second conductive layer

19 c third conductive layer

19 d fourth conductive layer

21 i-type amorphous semiconductor layer

22 n-type amorphous semiconductor layer

23 insulating layer

23 a first insulating layer

23 b second insulating layer

23 A first surface layer

23 B second surface layer

24 i-type amorphous semiconductor layer

25 p-type amorphous semiconductor layer

26 , 27 conductive layer