Solid-state image sensor

1. Field of the Invention

The present invention relates to a solid-state image sensor.

2. Description of the Related Art

In a solid-state image sensor, a plurality of column signal lines can be arranged at each column of a pixel array in order to increase the reading speed of the pixel array in which a plurality of pixels are arrayed in a matrix, and to individually read out signals from two photoelectric conversion portions in a unit pixel. For example, a shield pattern can be interposed between these column signal lines to prevent so-called crosstalk in which signals from column signal lines interfere with each other.

As the numbers of column signal lines and shield patterns increase, the aperture ratio of each pixel of the solid-state image sensor may decrease because these wiring lines block incident light.

The present invention provides a technique advantageous for suppressing a decrease in aperture ratio caused by an increase in the number of wiring lines.

One of the aspects of the present invention provides a solid-state image sensor comprising a pixel array in which a plurality of pixels are arrayed in a matrix having a plurality of rows and a plurality of columns, wherein the pixel array includes a first wiring layer and a second wiring layer arranged above the first wiring layer, the first wiring layer includes first column signal lines arranged at the respective columns of the pixel array, and the second wiring layer includes second column signal lines arranged at the respective columns of the pixel array.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

FIG. 1 is a block diagram for explaining an example of the arrangement of a solid-state image sensor according to the first embodiment;

FIG. 2 is a circuit diagram for explaining an example of the arrangement of a unit pixel;

FIG. 3 is a plan view for explaining an example of the layout of a pixel array according to the first embodiment;

FIG. 4 is a view for explaining a reference example of the arrangement of a solid-state image sensor;

FIGS. 5A and 5B are views for explaining an example of the arrangement of the solid-state image sensor according to the first embodiment;

FIG. 6 is a view for explaining the Bayer arrangement of the pixel array;

FIG. 7 is a block diagram for explaining an example of the arrangement of a solid-state image sensor according to the second embodiment;

FIG. 8 is a plan view for explaining an example of the layout of a pixel array according to the second embodiment;

FIG. 9 is a block diagram for explaining an example of the arrangement of a solid-state image sensor according to the third embodiment;

FIG. 10 is a plan view for explaining an example of the layout of a pixel array according to the third embodiment;

FIG. 11 is a view for explaining a reference example of the arrangement of a solid-state image sensor;

FIGS. 12A to 12C are views for explaining examples of the arrangement of the solid-state image sensor according to the third embodiment;

FIG. 13 is a block diagram for explaining an example of the arrangement of a solid-state image sensor according to the fourth embodiment;

FIG. 14 is a circuit diagram for explaining an example of the arrangement of a unit pixel;

FIG. 15 is a plan view for explaining an example of the layout of a pixel array according to the fourth embodiment;

FIG. 16 is a view for explaining an example of a focus detection operation by a phase-difference detection method;

FIGS. 17A and 17B are graphs for explaining the phase-difference detection method;

FIGS. 18A and 18B are views for explaining another example of the arrangement of the solid-state image sensor;

FIG. 19 is a view for explaining another example of the arrangement of the solid-state image sensor; and

FIG. 20 is a view for explaining still another example of the arrangement of the solid-state image sensor.

First Embodiment

A solid-state image sensor 1 1 according to the first embodiment will be described with reference to FIGS. 1 to 5B . FIG. 1 is a block diagram for explaining the arrangement of the solid-state image sensor 1 1 . The solid-state image sensor 1 1 includes a pixel array 2 in which a plurality of pixels 3 are arrayed in a matrix having a plurality of rows and a plurality of columns. For descriptive convenience, the pixel array 2 illustrated has 4×4 pixels 3 . First column signal lines 4 A and second column signal lines 4 B are arranged to transfer pixel signals read out from the pixel array 2 to horizontal scanning circuits 8 A and 8 B, respectively. The pixel signals of the pixels 3 on odd-numbered rows (first and third rows) in the pixel array 2 are output to the first column signal lines 4 A. The pixel signals of the pixels 3 on even-numbered rows (second and fourth rows) are output to the second column signal lines 4 B. Power supply wiring 5 and power supply wiring 6 are arranged at each column of the pixel array 2 . A timing control circuit 9 A can output a control signal to the horizontal scanning circuit 8 A to control the processing timing of a pixel signal. Similarly, a timing control circuit 9 B can output a control signal to the horizontal scanning circuit 8 B. A vertical scanning circuit 7 can output control signals RES 1 , TX 1 , SEL 1 , and the like to the respective pixels 3 of the pixel array 2 to read out pixel signals. Although the connections of the control signals RES 1 , TX 1 , SEL 1 , and the like to the pixel array 2 are omitted, the pixel 3 is controlled as follows. Each of the horizontal scanning circuits 8 A and 8 B can include, for example, a noise suppression circuit, amplifier circuit, and analog-to-digital conversion circuit. With this arrangement, each pixel signal output from the pixel array 2 by the vertical scanning circuit 7 can undergo a signal process by the horizontal scanning circuit 8 A or 8 B, and can be read out.

FIG. 2 exemplifies the arrangement of the circuit of the pixel 3 (unit pixel). The pixel 3 includes a photoelectric conversion portion 10 (for example, photodiode), transfer transistor 11 , floating diffusion capacitor 14 , reset transistor 15 , source follower transistor 17 , and selection transistor 18 . In the pixel 3 , VDD power is supplied to a power supply terminal 21 (the power supply wiring 5 is connected to it), and the ground potential is supplied to a power supply terminal 22 (the power supply wiring 6 is connected to it). The control signal TX 1 is supplied to a gate terminal 12 of the transfer transistor 11 . When the control signal TX 1 is activated, charges which are generated upon receiving light and accumulated in the photoelectric conversion portion 10 are transferred by the transfer transistor 11 to the floating diffusion capacitor 14 . The amount of current flowing through the source follower transistor 17 can change depending on potential fluctuations at a node 13 , that are caused by charges transferred to the floating diffusion capacitor 14 . The control signal SEL 1 is supplied to a gate terminal 19 of the selection transistor 18 . When the control signal SEL 1 is activated, the selection transistor 18 can output a pixel signal corresponding to the current amount of the source follower transistor 17 from a pixel signal output portion 20 . As exemplified in FIG. 1 , the pixel signal output portion 20 is connected to the first or second column signal line 4 A or 4 B. The control signal RES 1 is supplied to the gate terminal of the reset transistor 15 . When the control signal RES 1 is activated, the reset transistor 15 can reset the potential of the node 13 .

FIG. 3 is a plan view schematically showing the layout of 2×3 pixels 3 in the pixel array 2 of the solid-state image sensor 1 1 . For illustrative convenience of FIG. 3 , the illustration of wiring lines for the control signals RES 1 , TX 1 , SEL 1 , and the like is omitted. For the pixels 3 on the third column, the illustration of the first and second column signal lines 4 A and 4 B, the power supply wiring 5 , and the power supply wiring 6 is omitted.

As a reference example, FIG. 4 schematically shows a typical structure in which the first and second column signal lines 4 A and 4 B are arranged in the same wiring layer in a sectional structure along a cutline A-B in FIG. 3 . On the left side of FIG. 4 , the photoelectric conversion portion 10 receives light entering a microlens 25 via a color filter 24 . The pixel array 2 includes a first wiring layer M 1 , and a second wiring layer M 2 arranged above it. The first wiring layer M 1 can be, for example, a lowermost layer among a plurality of wiring layers. In this reference example, both the first and second column signal lines 4 A and 4 B are arranged in the first wiring layer M 1 . A conductive shield pattern (for example, the power supply wiring 5 ) is interposed between the first column signal line 4 A and the second column signal line 4 B. The first column signal line 4 A, power supply wiring 5 , and second column signal line 4 B are spaced apart from each other at an inter-wiring distance W 1 (for example, the critical dimension which can be decided by the manufacturing process). Another shield pattern (for example, the power supply wiring 6 ) is arranged in the second wiring layer M 2 . The power supply wiring 5 for VDD power and the power supply wiring 6 for ground (GND) can be used as these shield patterns, as in the embodiment, or wiring lines which receive other reference potentials may also be used. A solid line L 1 indicates a range where the optical path of light entering the microlens 25 is not blocked by the first and second column signal lines 4 A and 4 B.

FIG. 5A schematically shows a sectional structure along the cutline A-B when the embodiment is applied. The first wiring layer M 1 includes the first column signal line 4 A arranged at each column of the pixel array 2 . The second wiring layer M 2 includes the second column signal line 4 B arranged at each column of the pixel array 2 . At least the first wiring layer M 1 out of the first wiring layer M 1 and second wiring layer M 2 preferably further includes a conductive shield pattern. The shield pattern (in this case, the power supply wiring 5 ) is arranged adjacent to the first column signal line 4 A of the first wiring layer M 1 . The second column signal line 4 B is arranged at a position shifted from a position immediately above the first column signal line 4 A. The second wiring layer M 2 also includes another shield pattern (in this case, the power supply wiring 6 ). This shield pattern is arranged adjacent to the second column signal line 4 B. A solid line L 2 shown in FIG. 5A indicates a range where the optical path of light entering the microlens 25 is not blocked by the second column signal line 4 B and the shield pattern (power supply wiring 6 ). A broken line L 1 shown in FIG. 5A is identical to the solid line L 1 in the reference example ( FIG. 4 ). A comparison between L 1 and L 2 reveals that the photoelectric conversion portion 10 can receive a larger amount of light thanks to the wiring arrangement in the embodiment. This phenomenon stands out more in the peripheral region of the pixel array 2 than in the center region.

As described above, according to the first embodiment, a plurality of column signal lines are arranged in different wiring layers. This arrangement can reduce an area where the optical path is blocked, and suppress a decrease in the aperture ratio of the solid-state image sensor 1 1 . As another effect of the first embodiment, crosstalk noise between column signal lines can be suppressed by shifting the position of the second column signal line 4 B arranged in the second wiring layer M 2 from a position immediately above the first column signal line arranged in the first wiring layer M 1 . As the crosstalk noise suppression method, shield patterns can be arranged above and below the column signal line and on the left and right sides of it. However, in the first embodiment, a shield pattern is arranged only on one side of the column signal line, or above or below it. The first embodiment can therefore suppress an image signal propagation delay arising from the wiring capacitance.

FIG. 5B schematically shows an application example in which the wiring position is changed from that in the structure of FIG. 5A . More specifically, the first column signal line 4 A and the shield pattern (power supply wiring 5 ) in the first wiring layer M 1 are arranged at a large distance W 2 which nevertheless does not hamper the range (solid line L 2 ) of the optical path shown in FIG. 5A . The distance W 2 is decided within a range where the capacitance value difference between the wiring capacitance of the first column signal line 4 A and that of the second column signal line 4 B falls below a permissible value. This can further reduce, for example, generation of a short circuit between wiring lines in the wiring formation process, and increase the yield.

Second Embodiment

A solid-state image sensor 1 2 according to the second embodiment will be described with reference to FIGS. 6 to 8 . The solid-state image sensor 1 2 is obtained by applying color filters of the Bayer arrangement exemplified in FIG. 6 to the solid-state image sensor 1 1 in the first embodiment. Of symbols shown in FIG. 6 , RD represents a pixel (red pixel) which detects red light, BL represents a pixel (blue pixel) which detects blue pixel, GR and GB represent pixels (green pixels) which detect green light, H represents a column, and L represents a row. FIG. 7 is a block diagram for explaining the arrangement of the solid-state image sensor 1 2 , similar to the first embodiment. A pixel 3 RD which detects red light, a pixel 3 BL which detects blue light, and pixels 3 GR and 3 GB which detect green light are illustrated in a pixel array 2 . Pixel signal output portions 20 of the pixels 3 GR and 3 GB are connected to first column signal lines 4 A. The pixel signal output portions 20 of the pixels 3 RD and 3 BL are connected to second column signal lines 4 B. FIG. 8 is a plan view schematically showing the layout of 2×3 pixels 3 RD, 3 BL, 3 GR, and 3 GB in the pixel array 2 of the solid-state image sensor 1 2 , similar to the first embodiment.

A noise suppression circuit which can be included in a horizontal scanning circuit 8 A can clamp in advance, as a noise level, an output obtained when the potential of a node 13 is reset in reading out a pixel signal from each of the pixels 3 RD, 3 BL, 3 GR, and 3 GB. Then, the difference between the readout signal and the noise level can be read out to suppress noise, and the resultant signal can be processed as a pixel signal. Since outputs from the pixels 3 GR and 3 GB undergo a signal process by the common horizontal scanning circuit 8 A, noise levels arising from the horizontal scanning circuit 8 A can be made uniform. In addition to the effects of the first embodiment, the second embodiment can single out a noise level arising from the horizontal scanning circuit 8 A.

Third Embodiment

A solid-state image sensor 1 3 according to the third embodiment will be described with reference to FIGS. 9 to 12C . FIG. 9 is a block diagram for explaining the arrangement of the solid-state image sensor 1 3 , similar to the first and second embodiments. The third embodiment is different from the first and second embodiments in that four column signal lines 4 A to 4 D are arranged at each column of a pixel array 2 . Further, color filters of the Bayer arrangement are applied, similar to the second embodiment. Pixel signal output portions 20 of a pixel 3 GR on the first row and first column and a pixel 3 GB on the second row and second column are connected to the column signal lines 4 A. The pixel signal output portions 20 of a pixel 3 RD on the first row and second column and a pixel 3 BL on the second row and first column are connected to the column signal lines 4 B. The pixel signal output portions 20 of the pixel 3 GR on the third row and first column and the pixel 3 GB on the fourth row and second column are connected to the column signal lines 4 C. The pixel signal output portions 20 of the pixel 3 RD on the third row and second column and the pixel 3 BL on the fourth row and first column are connected to the column signal lines 4 D. This also applies to the remaining pixels. FIG. 10 is a plan view schematically showing the layout of 4×3 pixels 3 RD, 3 BL, 3 GR, and 3 GB in the pixel array 2 of the solid-state image sensor 1 3 , similar to the first and second embodiments.

FIG. 11 schematically shows a reference example of a sectional structure along a cutline C-D in FIG. 10 . In this reference example, a first wiring layer M 1 includes the column signal lines 4 A to 4 D. A second wiring layer M 2 includes shield patterns (for example, power supply wiring 5 and power supply wiring 6 ). Parasitic capacitance components which may be generated between adjacent wiring lines are shown on the right side of FIG. 11 . Note that a capacitive component (including a fringe capacitive component) between wiring lines adjacent to each other in the horizontal or vertical direction is illustrated. Another capacitive component (for example, between wiring lines positioned in a diagonal direction or wiring lines spaced apart by two or more layers) is small and is not illustrated. CL 1 is a capacitive component which may be generated between wiring lines adjacent to each other in the first wiring layer M 1 . CH 1 is a capacitive component which may be generated between the wiring layer of the first wiring layer M 1 and that of the second wiring layer M 2 immediately above it. At this time, each of capacitive components which may be generated in the column signal lines 4 A and 4 D is CL 1 . Each of capacitive components which may be generated in the column signal lines 4 B and 4 C is 2×CL 1 +CH 1 . Hence, the column signal lines may have a capacitance value difference (CL 1 +CH 1 ). This difference leads to a signal propagation delay difference in the column signal lines 4 A to 4 D, and the subsequent signal process is rate-determined by a column signal line having a large delay. In the structure of this reference example, adjacent column signal lines may generate signal crosstalk.

FIG. 12A schematically shows a sectional structure along the cutline C-D when the embodiment is applied. At least the first wiring layer M 1 out of the first wiring layer M 1 and second wiring layer M 2 further includes a conductive shield pattern (in this case, the power supply wiring 5 ). The first column signal line of the first wiring layer M 1 includes at least two column signal lines (in this case, the column signal lines 4 A and 4 C). The shield pattern (power supply wiring 5 ) is interposed between the two column signal lines 4 A and 4 C. The second wiring layer M 2 also includes two column signal lines (in this case, the column signal lines 4 B and 4 D), and another shield pattern (in this case, the power supply wiring 6 ) interposed between the two column signal lines 4 B and 4 D. Parasitic capacitance components which may be generated between adjacent wiring lines are schematically shown on the right side of FIG. 12A , similar to FIG. 11 . CL 2 is a capacitive component which may be generated between wiring lines adjacent to each other in the first wiring layer M 1 . CL 3 is a capacitive component which may be generated between wiring lines adjacent to each other in the second wiring layer M 2 . CH 2 is a capacitive component which may be generated between the wiring layer of the first wiring layer M 1 and that of the second wiring layer M 2 immediately above it. At this time, the capacitive component which may be generated between the column signal lines 4 A and 4 C, is CL 2 +CH 2 . The capacitive component which may be generated between the column signal lines 4 B and 4 D, is CL 3 +CH 2 . The difference between these capacitance values is |CL 2 −CL 3 |. Compared to the reference example described above, signal propagation delay differences in the column signal lines 4 A to 4 D can be suppressed.

As exemplified in FIG. 12A , column signal lines for propagating pixel signals of the same color are preferably arranged to be symmetrical about the shield pattern in the same wiring layer (for example, the column signal lines 4 A and 4 C or the column signal lines 4 B and 4 D). In this structure, the capacitive component CH 2 between different wiring layers is preferably smaller than each of the capacitive components CL 2 and CL 3 between adjacent wiring lines in the same wiring layers. A shield pattern may be further added to an immediately upper or lower wiring layer.

As described above, according to the third embodiment, a plurality of column signal lines are arranged in different wiring layers. This arrangement can reduce an area where the optical path is blocked, and suppress a decrease in the aperture ratio of the solid-state image sensor 1 3 . In general, the thickness of an interlayer dielectric film is larger than the distance (for example, the critical dimension which can be decided by the manufacturing process) between wiring lines adjacent to each other in the same wiring layer. Hence, as another effect of the third embodiment, the capacitance between wiring lines in different wiring layers becomes smaller than that between adjacent wiring lines in the same wiring layer, and crosstalk noise between column signal lines can be suppressed. As the crosstalk noise suppression method, shield patterns can be arranged above and below the column signal line and on the left and right sides of it. However, in the embodiment, a shield pattern is arranged only on one side of the column signal line, or above or below it. The third embodiment can suppress even an image signal propagation delay arising from the wiring capacitance.

FIG. 12B schematically shows an application example in which the wiring position is changed from that in the structure of FIG. 12A . That is, the column signal lines 4 A and 4 C and the shield pattern (power supply wiring 5 ) in the first wiring layer M 1 are arranged at, for example, a distance W 4 larger than W 3 . This can further reduce, for example, generation of a short circuit between wiring lines in the wiring formation process, and increase the yield while ensuring the light receiving amount of a photoelectric conversion portion 10 . Parasitic capacitance components which may be generated between adjacent wiring lines are similarly shown on the right side of FIG. 12B . CL 4 is a capacitive component which may be generated between wiring lines adjacent to each other in the first wiring layer M 1 . CL 5 is a capacitive component which may be generated between wiring lines adjacent to each other in the second wiring layer M 2 . CH 3 is a capacitive component which may be generated between the wiring layer of the first wiring layer M 1 and that of the second wiring layer M 2 immediately above it. The distance W 4 is decided within, for example, a range where the difference |CL 4 −CL 5 | between capacitance values which may be generated in the column signal lines 4 A to 4 D falls below a permissible value.

In FIG. 12C , the shield pattern (in this case, the power supply wiring 6 ) is arranged not in the second wiring layer M 2 but in another wiring layer (for example, third wiring layer). Similarly, parasitic capacitance components which may be generated between adjacent wiring lines are schematically shown on the right side of FIG. 12C . CL 6 is a capacitive component which may be generated between wiring lines adjacent to each other in the first wiring layer M 1 . CL 7 is a capacitive component which may be generated between wiring lines adjacent to each other in the second wiring layer M 2 . CH 4 is a capacitive component which may be generated between the wiring layer of the first wiring layer M 1 and that of the second wiring layer M 2 immediately above it. At this time, if CL 7 is much smaller than CH 4 , crosstalk between the adjacent column signal lines 4 B and 4 D can be suppressed. This suffices to be achieved as long as, for example, the capacitance value differences between the wiring capacitances of the column signal lines 4 A to 4 D fall within a permissible range. In this manner, the shield pattern (power supply wiring 6 ) may be arranged in another wiring layer (for example, third wiring layer).

Fourth Embodiment

A solid-state image sensor 1 4 according to the fourth embodiment will be described with reference to FIGS. 13 to 15 . FIG. 13 is a block diagram for explaining the arrangement of the solid-state image sensor 1 4 , similar to the third embodiment. The fourth embodiment is different from the third embodiment in that each unit pixel 3 includes two photoelectric conversion portions (photodiodes 10 A and 10 B). More specifically, light enters the photodiodes 10 A and 10 B via a microlens common to them. Signals read out from the photodiodes 10 A and 10 B contain focus detection signals, and can be used in a focus detection operation to be described later. As exemplified in FIG. 14 , each of the photodiodes 10 A and 10 B is connected to various transistors for reading out signals, including a transfer transistor 11 . The unit pixels 3 will be referred to as divided pixels 3 RD-A, 3 BL-A, 3 GR-A, 3 GB-A, 3 RD-B, 3 BL-B, 3 GR-B, and 3 GB-B. Although a circuit arrangement including no selection transistor 18 is employed in FIG. 14 , a circuit arrangement including a selection transistor 18 may be adopted, as described in the first embodiment ( FIG. 2 ).

Pixel signal output portions 20 A of the divided pixel 3 GR-A on the first row and first column and the divided pixel 3 GB-A on the second row and second column are connected to column signal lines 4 A. The pixel signal output portions 20 A of the divided pixel 3 RD-A on the first row and second column and the divided pixel 3 BL-A on the second row and first column are connected to column signal lines 4 B. Pixel signal output portions 20 B of the divided pixel 3 GB-B on the first row and first column and the divided pixel 3 GR-B on the second row and second column are connected to column signal lines 4 C. The pixel signal output portions 20 B of the divided pixel 3 RD-B on the first row and second column and the divided pixel 3 BL-B on the second row and first column are connected to column signal lines 4 D. This also applies to the remaining pixels. FIG. 15 is a plan view schematically showing the layout of 2×3 pixels 3 in a pixel array 2 of the solid-state image sensor 1 4 , similar to the first to third embodiments.

In this fashion, when the unit pixel 3 includes the two photodiodes 10 A and 10 B and their signals are individually read out, the column signal lines 4 A to 4 D are preferably arranged as in the fourth embodiment. Accordingly, the fourth embodiment can obtain the same effects as those of the first to third embodiments while maintaining the pixel signal reading speed of the pixel array 2 .

FIGS. 18A and 18B show modification 1 to the fourth embodiment. The same reference numerals as those in FIGS. 13 to 15 denote portions having the same functions, and a detailed description thereof will not be repeated. FIG. 18A is a plan view schematically showing the layout of 2×3 pixels 3 in the pixel array 2 of the solid-state image sensor 1 4 , similar to FIG. 15 . FIG. 18B schematically shows the sectional structure of a portion including the column signal line and power supply wiring. In this modification, as shown in FIG. 18B , on the first column, signals in the divided pixels 3 BL-A and 3 BL-B are read out in the first wiring layer, and signals in the divided pixels 3 GR-A and 3 GR-B are read out in the second wiring layer. On the second column, signals in the divided pixels 3 RD-A and 3 RD-B are read out in the first wiring layer, and signals in the divided pixels 3 GB-A and 3 GB-B are read out in the second wiring layer. This layout can reduce the influence of color mixing in the column signal lines.

FIG. 19 shows modification 2, similar to FIGS. 18A and 18B . The difference of modification 2 from modification 1 is the layout of column signal lines. Column signal lines are interposed not between divided pixels, but between adjacent pixels. Further, column signal lines for transferring signals of the same color are distributed to different wiring layers, and arranged close to each other. This layout can reduce the influence of color mixing in the column signal lines because close column signal lines transfer signals of the same color.

FIG. 20 shows modification 3, similar to FIGS. 18A and 18B . The difference of modification 3 from modification 2 is the layout of column signal lines. In modification 3, column signal lines for transferring signals from the divided pixels 3 GR-A, 3 GR-B, 3 GB-A, and 3 GB-B are arranged close to each other using two layers. This layout can reduce the influence of color mixing for signals of green pixels in the column signal lines.

An example of the focus detection operation will be explained with reference to FIGS. 16 , 17 A, and 17 B. FIG. 16 is a view schematically showing a state in which a beam emerging from an exit pupil 902 of a photographing lens 900 enters a solid-state image sensor 901 . The solid-state image sensor 901 includes a microlens 202 , a color filter 301 , and two photoelectric conversion portions PD 1 and PD 2 for each unit pixel. Light having passed through the exit pupil 902 enters the solid-state image sensor 901 using an optical axis 903 as the center. Reference numerals 906 and 907 denote rays at the outermost periphery of light passing through a partial region 904 of the exit pupil 902 . Reference numerals 908 and 909 denote rays at the outermost periphery of light passing through another partial region 905 of the exit pupil 902 . In FIG. 16 , of beams having passed through the exit pupil 902 , those illustrated above the optical axis 903 enter the photoelectric conversion portion PD 1 , and those illustrated below it enter the photoelectric conversion portion PD 2 . In other words, the photoelectric conversion portions PD 1 and PD 2 receive beams having passed through different regions of the exit pupil 902 of the photographing lens 900 .

For example, signals output from the photoelectric conversion portions PD 1 upon receiving light in respective pixels on one column of the pixel array will be defined as the first line data. Similarly, signals output from the photoelectric conversion portions PD 2 will be defined as the second line data. For example, based on the difference (phase-difference) between the first line data and the second line data, a processor (not shown) which performs the focus detection operation determines whether an image is in focus.

FIG. 17A shows line data in an in-focus state when a point light source is formed into an image. FIG. 17B shows line data in an out-of-focus state. The abscissa represents the position of each pixel, and the ordinate represents the output value of each pixel. In the in-focus state, the first line data and second line data overlap each other. To the contrary, in the out-of-focus state, the first line data and second line data do not overlap each other. At this time, the processor can calculate, from a shift amount 1001 between these outputs, a distance by which the lens position is moved to focus on the image. The focus detection operation may be executed by the above-described processor. Alternatively, an arithmetic unit configured to execute the focus detection operation may be included in the solid-state image sensor, as needed. A larger difference of the incident light amount may be generated between the photoelectric conversion portions PD 1 and PD 2 of each pixel in the peripheral region of the pixel array than in the center region. Thus, focus detection pixels are preferably arranged in the peripheral region of the pixel array.

Next, generation of image data in this pixel arrangement will be described. As described above, signals output from the two photoelectric conversion portions PD 1 and PD 2 are separately read out and used for focus detection. The signals output from the photoelectric conversion portions PD 1 and PD 2 in response to light entering each pixel 3 are added, obtaining the pixel signal of the pixel 3 . For example, when the amount of charges generated and accumulated in one of the photoelectric conversion portions PD 1 and PD 2 reaches the saturated state, a sequence to determine that the reliability of the signal is poor, and not to perform phase detection or to stop it can be adopted. In this way, the above operation may be controlled in accordance with the states (charge amounts and signals) of the photoelectric conversion portions PD 1 and PD 2 .

Although the four embodiments have been described, the present invention is not limited to them. The purpose, state, application, function, and other specifications can be properly changed, and the present invention can be practiced by another embodiment, as a matter of course. For example, the arrangement of the column signal lines 4 A to 4 D is not limited to these embodiments. The column signal lines 4 A and 4 C may be arranged in the second wiring layer M 2 , and the column signal lines 4 B and 4 D may be arranged in the first wiring layer M 1 . The power supply wiring 5 for VDD power and the power supply wiring 6 for ground (GND) are used for the conductive shield patterns in each of the above embodiments, but wiring lines for another application may be used. Color filters of the Bayer arrangement are used in each of the above embodiments, but color filters of another array may be used or color filters may be implemented by monochrome sensors. The pixel array 2 has been described as a CMOS image sensor in each of the above embodiments, but may be another sensor. All or part of the operation of each functional block in each of the above embodiments may be controlled by an OS or the like running on a computer, together with or instead of the computer.

A solid-state image sensor incorporated in a camera has been described. However, the concept of the camera includes not only an apparatus mainly for shooting, but also an apparatus accessorily having the a shooting function (for example, a personal computer or a mobile terminal). The camera can include the solid-state image sensor according to the present invention which has been exemplified in the embodiments, and a processor which processes a signal output from the solid-state image sensor. The processor can include, for example, an A/D converter, and a processor which processes digital data output from the A/D converter.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application Nos. 2012-008447, filed Jan. 18, 2012 and 2012-281754, filed Dec. 25, 2012, which are hereby incorporated by reference herein in their entirety.