Capacitive load testing device of power supply

1. Technical Field

The present disclosure is related to a device for testing capacitive loads of a power supply.

2. Description of Related Art

A power supply unit (PSU) of a computer is a power supply having multiple outputs which may output voltages, +3.3V, +5V, +12V, for example. Each of the outputs of the PSU includes capacitive loads which equals to a capacitance value that can be connected to the PSU in parallel when the PSU turns on. When the capacitive loads, which are electronically connected to one of outputs of the PSU in parallel exceeds the largest capacitance value, the PSU may execute an over-current protection function which stops output the voltage of the PSU. Then, the computer cannot be operated or be turned on. When designing a main board of the computer, clearly understanding the largest capacitance value of each of the outputs of the PSU is very important.

Therefore, there is room for improvement within the art.

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Like item numbers denote like items in the various figures.

FIG. 1 is a functional module diagram of a capacitive load testing device of a power supply and a power supply unit of one embodiment.

FIG. 2 is a connection schematic diagram of a first power supply interface of the power supply unit and a second power supply interface of the device of FIG. 1 .

FIG. 3 is a circuit diagram of a power supply switching circuit and a controller of the device of FIG. 1 .

FIG. 4 is a circuit diagram of a current sampling circuit and the controller of the device of FIG. 1 .

FIG. 5 is a circuit diagram of a capacitive load switching circuit, a discharge circuit and the controller of the device of FIG. 1 .

FIG. 1 and FIG. 2 are one embodiment of a capacitive load testing device 100 of the present disclosure. The capacitive load testing device 100 of a power supply determines a greatest capacitance value of an output power supply unit (PSU) 200 . The PSU 200 is a multiple output power supply. The PSU 200 is used in conjunction with a computer to output multiple voltages for each power supply element of the computer. The multiple voltages may be +5V, +3.3V, +5V for backup, and +12V. The PSU 200 includes a first power supply interface 210 . The capacitive load testing device 100 of the power supply includes a second power supply interface 10 , a controller 20 , a power supply switching circuit 30 , a current sampling circuit 40 , a capacitive load switching circuit 50 , a discharge circuit 60 , and a display 70 .

FIG. 2 is a connection schematic diagram of the first power supply interface 210 and the second power supply interface 10 of the capacitive load testing device 100 of the power supply. The first power supply interface 210 includes a pin P 1 for output +5V, a pin P 2 for output +3.3V, a pin P 3 for output +5V for backup, and a pin P 4 for output +12V. The first power supply interface 210 is a power supply interface of twenty-four pins, and FIG. 2 shows four pins of twenty-four pins.

The second power supply interface 10 is electronically connected between the power supply switching circuit 30 of the capacitive load testing device 100 and the first power supply interface 210 of the PSU 200 to receive the multiple voltages, +5V, +3.3V, +5V for backup, and +12V. The second power supply interface 10 has a same structure as the first power supply interface 210 and includes a pin P 1 for output +5V, a pin P 2 for output +3.3V, a pin P 3 for output +5V for backup, and a pin P 4 for output +12V which are electronically connected to the pins of the first power supply interface 210 .

FIG. 3 is a circuit diagram of the power supply switching circuit 30 and the controller 20 of the device 100 . For electronically connecting one of the outputs of the PSU 200 with the capacitive load switching circuit 50 , the controller 20 turns on one of switches of the power supply switching circuit 30 . The controller 20 then controls the capacitive load switching circuit 50 to be electronically connected to the output of the PSU 200 for different capacitance values of the capacitive load. The controller 20 receives a current sampling by the current sampling circuit 40 and determines weather the capacitive load electronically connected to the PSU 200 is the largest capacitance value by the output current.

The controller 20 includes power supply switching pins PD 1 -PD 4 electronically connected to the power supply switching circuit 30 , capacitive loads switching pins PA 1 -PAn electronically connected to the capacitive load switching circuit, a sampling data updating pin PC 1 electronically connected to the current sampling circuit 40 , and a discharge controlling pin PB 1 electronically connected to the discharge circuit 60 .

The power supply switching circuit 30 includes a plurality of first switches. A number of the first switches is equal to a number of the outputs of the PSU 200 . Two first switches 31 a , 31 b are shown in FIG. 3 . Each of the first switches 31 a , 31 b includes an input contact, an output contact, and a control contact electronically connected to the controller 20 . Each of the input contacts of the first switches 31 a , 31 b is electronically connected to one of the outputs of the PSU 200 by the second power supply interface 10 . The output contacts of the first switches 31 a , 31 b are all electronically connected to the capacitive load switching circuit 50 and the current sampling circuit 40 . The capacitive load switching circuit 50 and the current sampling circuit 40 are electronically connected or disconnected to one of the outputs of the PSU 200 according to the first switches turned on and off by the controller 20 . The controller 20 turns on only one of the first switches at a time to separately test the outputs of the PSU 200 .

In the embodiment, the power supply switching circuit 30 further includes a boost chip 33 . The boost chip 33 converts an input voltage (e.g. +5V) into a drain voltage. The drain voltage is larger than each output voltage of the PSU 200 . The drain voltage is +15V in the embodiment.

FIG. 3 shows two first switches 31 a , 31 b which are electronically connected to +5V of the PSU 200 and +3.3V of the PSU 200 separately and other switches are omissible. The first switch 31 a includes a first Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Q 1 and a second MOSFET Q 2 . A gate g 1 of the first MOSFET Q 1 is electronically connected to the switching pin PD 1 of the controller 20 , and a source s 1 of the first MOSFET Q 1 is grounded. A drain d 1 of the first MOSFET Q 1 is electronically connected to an output contact of the boost chip 33 to receive the drain voltage of +15V through a first pull-up resistor R 1 . A gate g 2 of the second MOSFET Q 2 is electronically connected to the drain d 1 of the first MOSFET Q 1 . A drain d 2 of the second MOSFET Q 2 is electronically connected to the pin P 1 for receiving the voltage of +5V output from the second power supply interface 10 . A source s 2 of the second MOSFET Q 2 is electronically connected to the capacitive load switching circuit 50 and the current sampling circuit 40 . The gate g 1 of the first MOSFET Q 1 is the control contact of the first switch 31 a . The drain d 2 of the second MOSFET Q 2 is the input contact of the first switch 31 a . The source s 2 of the second MOSFET Q 2 is the output contact of the first switch 31 a . The other first switch 31 b has a same structure as the first switch 31 a , with the only differences being that the gate g 1 of the first MOSFET Q 1 of the first switch 31 b is electronically connected to the switching pin PD 2 of the controller 20 , and the drain d 2 of the second MOSFET Q 2 of the first switch 31 b is electronically connected to the pin P 2 for receiving the voltage of +3.3V output from the second power supply interface 10 . A node A of the first switches 31 a and 31 b is the output contact of the power supply switching circuit 30 .

If the controller 20 need to test the output of +5V of the PSU 200 , then the controller 20 outputs a low voltage signal (logic 0) to the gate g 1 of the first MOSFET Q 1 of the first switch 31 a by the switching pin PD 1 and output a high voltage signal (logic 1) to other first switches. The first MOSFET Q 1 of the first switch 31 a is turned off, and the second MOSFET Q 2 of the first switch 31 a is turned on. The first MOSFET Q 1 of the first switch 31 b is turned on, and the second MOSFET Q 2 of the first switch 31 b is turned off. When the other output of the PSU 200 needs to be tested, the first switch 31 b for example, the controller 20 outputs the low voltage signal to the first switch 31 b and outputs the high voltage signal to other first switches, and the output voltage of the node A is +3.3V.

FIG. 4 is a circuit diagram of the current sampling circuit 40 of the device 100 and the controller 20 . The current sampling circuit 40 samples the output current output from the power supply switching circuit 30 and the output current is selected by the controller 20 . The current sampling circuit 40 includes a current detecting resistor R 3 , two filter capacitors C 1 and C 2 , a voltage sampling amplification unit 41 , and an analog-to-digital converter 43 , which is an analog-to-digital converter and electronically connected to the voltage sampling amplification unit 41 . The current detecting resistor R 3 is connected to the output contact of the power supply switching circuit 30 in series in addition, is positioned between the node A and the capacitive load switching circuit 50 (shown in FIG. 5 ). One side of the current detecting resistor R 3 is grounded through the filter capacitor C 1 , and the other side of the current detecting resistor R 3 is grounded through the filter capacitor C 2 .

The voltage sampling amplification unit 41 detects a voltage across the current detecting resistor R 3 and amplifies the voltage to output to the analog-to-digital converter 43 . In the embodiment, the voltage sampling amplification unit 41 includes a first non-inverting amplifier 411 , a second non-inverting amplifier 412 , a differential amplifier 413 , a gain set resistor R 4 , and resistors R 5 -R 9 . Non-inverting input contacts of the first non-inverting amplifier 411 and the second non-inverting amplifier 412 are electronically connected to two ends of the current detecting resistor R 3 separately. Inverting input contacts of the first non-inverting amplifier 411 and the second non-inverting amplifier 412 are electronically connected to two ends of the gain set resistor R 4 . The output contact of the first non-inverting amplifier 411 is electronically connected to the inverting input contact of the differential amplifier 413 through the resistor R 7 . The output contact of the second non-inverting amplifier 412 is electronically connected to the non-inverting input contact of the differential amplifier 413 through the resistor R 8 . A resistor R 5 is positioned between the input contact and the output contact of the first non-inverting amplifier 411 . A resistor R 6 is positioned between the input contact and the output contact of the second non-inverting amplifier 412 . A resistor R 9 is positioned between the input contact and the output contact of the differential amplifier 413 . The first non-inverting amplifier 411 and the second non-inverting amplifier 412 are symmetrical non-inverting amplifiers, and separately amplify the voltages of the two ends of the current detecting resistor R 3 , and separately output the amplified voltages to the non-inverting input contact and the inverting input contact of the differential amplifier 413 . The differential amplifier 413 amplifies a subtraction of the non-inverting input and the inverting input to output to the analog-to-digital converter 43 . The gain set resistor R 4 may adjust a gain of the voltage sampling amplification unit 41 .

The analog-to-digital converter 43 converts an analog signal sampled by the voltage sampling amplification unit 41 into a digital signal and outputs to the sampling data updating pin PC 1 of the controller 20 . A value of the digital signal divided by the resistor value of the current detecting resistor R 3 and the gain of the voltage sampling amplification unit 41 equals a value of the current output from the power supply switching circuit 30 . The controller 20 compares the value of the output current with a reference current, and the reference current is a current value when the power supply executes the over-current protection, which stops output the voltage of the PSU 200 .

FIG. 5 is a circuit diagram of the capacitive load switching circuit 50 , the discharge circuit 60 of the device 100 and the controller 20 . The capacitive load switching circuit 50 includes a plurality of second switches. A number of second switches is equal to a number of the capacitive load switching pins PA 1 -PAn of the controller 20 (two second switches 51 a , 51 b are shown in FIG. 5 ) and a plurality of loading capacitors. A number of loading capacitors is equal to a number of the second switches (two loading capacitors C 3 , C 4 are shown in FIG. 5 ). Each of the second switches is electronically connected to the corresponding capacitive load switching pins PA 1 -PAn of the controller 20 . Each anode of the each loading capacitor is electronically connected to the output contact of the power supply switching circuit 30 through the current detecting resistor R 3 , and each cathode of the each loading capacitor is grounded through the second switch. Different total magnitudes of the capacitive loads are connected to the power supply according to the controller 20 turning on and off the second switches.

In FIG. 5 , the two second switches 51 a , 51 b and the two loading capacitors C 3 , C 4 are examples. The second switch 51 a includes a third MOSFET Q 3 and a fourth MOSFET Q 4 . A gate g 3 of the third MOSFET Q 3 is electronically connected to the capacitive load switching pin PA 1 of the controller 20 . A drain d 3 of the third MOSFET Q 3 is electronically connected to the output contact of the boost chip 33 for receiving the drain voltage of +15V through a second pull-up resistor R 2 . A source s 3 of the third MOSFET Q 3 is grounded. A gate g 4 of the fourth MOSFET Q 4 is electronically connected to the drain d 3 of the third MOSFET Q 3 . A drain d 4 of the fourth MOSFET Q 4 is electronically connected to the output contact of the power supply switching circuit 30 through the loading capacitor C 3 . A source s 4 of the fourth MOSFET Q 4 is grounded. The second switch 51 b has the same structure as the second switch 51 a , with the differences being that the gate g 3 of the third MOSFET Q 3 of the second switch 51 b is electronically connected to the capacitive load switching pin PAn of the controller 20 and the drain d 4 of the fourth MOSFET Q 4 of the second switch 51 b is electronically connected to the output contact of the power supply switching circuit 30 through the loading capacitor C 4 .

When the controller 20 tests capacitive loads of the power supply, +5V of the power supply for example, the controller 20 output the low voltage signal output from the capacitive load switching pin PA 1 to turn on the second switch 51 a , and the loading capacitor C 3 is connected to the +5V of the power supply. If a value of the current output from the +5V of the power supply is smaller than the reference current value, then the controller 20 turns on the other second switches for increasing the capacitance value of the capacitive load switching circuit 50 until the output current value equals to the reference current value. In addition, the total capacitance value of the capacitive load switching circuit 50 is the largest capacitance value of the +5V of the power supply. The controller 20 calculates the total capacitance value of the capacitive load switching circuit 50 according to the capacitance value corresponding to the second switches.

The capacitance value of the filter capacitors C 1 and C 2 are preferably smaller than one nanofarad, and the current detecting resistor value is preferably smaller than 0.1Ω to avoid influencing the accuracy of the largest capacitance value calculated by the controller 20 . In the embodiment, the capacitance value of the filter capacitor is one nanofarad, and the current detecting resistor value is 0.04Ω.

The discharge circuit 60 is electronically connected to the controller 20 and discharges the loading capacitors to raise the accuracy after testing the largest capacitive load of the power supply. The discharge circuit 60 includes a fifth MOSFET Q 5 and a discharge resistor R 10 . A gate g 5 of the fifth MOSFET Q 5 is electronically connected to the discharge controlling pin PB 1 of the controller 20 , and a drain d 5 of the fifth MOSFET Q 5 is electronically connected to the anodes of the loading capacitors through discharge resistor R 10 . When the test of one of the output of the PSU 200 is finished, the controller 20 transmits the low voltage signal output from the discharge controlling pin PB 1 to the fifth MOSFET Q 5 and the discharge resistor is grounded to discharge electronic charges of the loading capacitors C 3 , C 4 . The discharge circuit 60 further includes a plurality of fifth MOSFETs and discharge resistors to avoid a larger current damaging the fifth MOSFET Q 5 . Each gate of the fifth MOSFETs is electronically connected to the discharge controlling pin PB 1 of the controller 20 , and each source of the fifth MOSFETs is grounded, and each drain of the fifth MOSFETs is electronically connected to the anode of the loading capacitors through one of discharge resistors. When the discharge circuit is discharged, the discharge resistors may separate the current for reducing damage of the MOSFETs.

The display 70 is electronically connected to the controller 20 and displays the largest value of the capacitive loads of each of the outputs of the PSU 200 determined by the controller 20 .

The capacitive load testing device 100 of the power supply tests the largest value of the capacitive loads of one of the outputs of the PSU 200 by the power supply switching circuit 30 . The controller 20 turns on and off the switches of the capacitive load switching circuit 50 for determining the largest total value of the capacitive loads of the PSU 200 . Therefore, the capacitive load testing device 100 of power supply may clearly test the largest value of the capacitive loads of each of the outputs of the PSU 200 .

It is to be further understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, together with details of structures and functions of various embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of arrangement of parts within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.