Current-responsive active rectification for a power supply operable in a discontinuous mode

This application claims priority from provisional patent application No. 61/666,290, filed 29 Jun. 2012, which is incorporated in its entirety herein by reference.

An embodiment relates generally to power supplies, and more specifically to rectifying a current so as to block a reverse current from flowing while a power supply is operating in discontinuous mode (DCM), where the rectifying is performed in response to the current.

A discontinuous-mode (DCM) switching power supply generates a regulated output voltage in response to a current that goes to zero for a period of time during each switching cycle.

If the current reverses its direction, i.e., becomes negative or falls below zero, then the efficiency of the power supply may be significantly reduced.

Therefore, a DCM power supply may include circuitry to rectify the current; that is, such circuitry allows the current to flow in a forward direction (i.e., allows a forward current), but inhibits the current from flowing in a reverse direction (i.e., inhibits a reverse current). For example, a DCM power supply may include a transistor in the current path, and may activate the transistor while the current is flowing in the forward direction and deactivate the transistor to block the current from flowing in the reverse direction; that is, the power supply may actively rectify the current by using an active component (here a transistor) to rectify the current instead of using an inactive component such as a diode.

But unfortunately, such rectification circuitry may cause a reduction in the efficiency of a power supply that includes such rectification circuitry. For example, such rectification circuitry may not provide optimum rectification timing, and, therefore, may allow a reverse current to flow for a significant period of time before blocking the reverse current, or may block a forward current for a significant period of time when it should be conducting the forward current.

An embodiment is an apparatus that includes an energy-storage circuit and a rectifying circuit. The energy-storage circuit is configured to generate a current that flows in a direction, and the rectifying circuit is configured to substantially block the current from flowing in a reverse direction in response to the current.

Such an apparatus may be configured to block a reverse current before the reverse current begins to flow. For example, such an apparatus may include a transistor disposed in the path of the current, and may be configured to deactivate the transistor while a forward current is still flowing.

Furthermore, by being configured to block the current from flowing in a reverse direction in response to the current itself, such an apparatus may better block a reverse current than an apparatus that blocks a reverse current in another manner, such as in response to a voltage across a rectifying transistor.

FIG. 1 is block diagram of a discontinuous-mode (DCM) power supply that is configured to actively rectify a current in response to the current according to an embodiment.

FIG. 2 is a schematic diagram of a portion of the DCM power supply of FIG. 1 according to an embodiment.

FIG. 3 is plot of the actively rectified current of FIG. 2 versus time according to an embodiment.

FIG. 4 is a plot of the gate voltage of the rectifying transistor of FIG. 2 versus time overlaid with a plot of the actively rectified current of FIG. 2 versus time according to an embodiment.

FIG. 5 is a plot of the drain voltage of the rectifying transistor of FIG. 2 versus time overlaid with a plot of the actively rectified current of FIG. 2 versus time according to an embodiment.

FIG. 6 is another plot of the drain voltage of the rectifying transistor of FIG. 2 versus time overlaid with a plot of the actively rectified current of FIG. 2 versus time according to an embodiment.

FIG. 7 is a schematic diagram of a portion of the DCM power supply of FIG. 1 according to another embodiment.

FIG. 8 is a block diagram of a system that incorporates the power supply of FIG. 1 according to an embodiment.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a block diagram of a discontinuous-mode (DCM) power supply 10 , which is configured to generate a regulated output voltage V out in response to a current, and which includes a rectifier circuit 12 configured to block the current from flowing in a reverse direction in response to the current itself, according to an embodiment. For example, the rectifier circuit 12 may be configured to block the current from flowing in a reverse direction even before the current starts to flow in the reverse direction. By reducing or eliminating the period of time during which a reverse current flows, the circuit 12 may increase the efficiency of the power supply 10 as compared to the efficiency of a conventional DCM power supply.

In addition to the rectifying circuit 12 , the power supply 10 includes a driver 14 , an energy-storage circuit 16 , and a regulator 18 .

The driver 14 receives an input voltage V in and a current I in , and generates first intermediate voltage V int — 1 and first intermediate current I int — 1 .

The energy-storage circuit receives V int — 1 and I int — 1 , and generates a second intermediate voltage V int — 2 and a second intermediate current I int — 2 .

And the regulator 18 receives V int — 2 and I int — 2 , and generates a regulated output voltage V out and a load current I out .

The rectifying circuit 12 includes a rectifier 20 , a current sensor 22 , and a controller 24 .

In operation, the driver 14 drives the energy-storage circuit 16 , which generates a decaying, i.e., dissipating, current I int — 2 flowing in a forward direction (i.e., through the rectifier 20 ) indicated by the arrow above “I int — 2 ” in FIG. 1 .

While the current I int — 2 is flowing in the forward direction and has a magnitude that is above a threshold set by the controller 24 , the rectifying circuit 12 allows I int — 2 to continue to flow. In detail, the sensor 22 monitors I int — 2 and generates a signal SENSE that represents the magnitude and the direction of I int — 2 . In response to the signal SENSE indicating that I int — 2 is flowing in the forward direction and has a magnitude above the threshold, the controller 24 activates the rectifier 20 such that the rectifier presents a relatively small impedance to the forward flow of I int — 2 . For example, the impedance presented by the rectifier 20 may be such that a voltage drop across the rectifier is significantly less than the voltage drop (e.g., ˜0.7 Volts) across a forward-biased diode; typically, the smaller the voltage drop across the rectifier, the more efficient the power supply 10 .

But in response to the magnitude of the forward current I int — 2 falling below the threshold, the rectifying circuit 12 blocks I int — 2 from flowing, thus limiting or eliminating the time during which I int — 2 flows in a reverse direction (i.e., opposite to the direction shown by the arrow above “I int — 2 ” in FIG. 1 ). In detail, in response to the signal SENSE indicating that I int — 2 is flowing in the forward direction and has a magnitude below the threshold, the controller 24 deactivates the rectifier 20 such that the blocking circuit presents a relatively high impedance to the flow of I int — 2 , the impedance being high enough to cause the magnitude of I int — 2 to decrease to zero, and being high enough to limit or eliminate the period of time during which I int — 2 flows in a reverse direction. Typically, the shorter the period of time during which I int — 2 flows in a reverse direction, the more efficient the power supply 10 .

The regulator 18 converts the current I int — 2 into the voltage V int — 2 , and regulates V int — 2 to generate V out . For example, the regulator 18 may be any type of regulator, such as DC-DC converter (e.g., a buck converter, a buck-boost converter) or a linear regulator (e.g., a low-drop-out (LDO) regulator).

Still referring to FIG. 1 , alternate embodiments of the power supply 10 are contemplated. For example, the regulator 18 may generate a regulated current I out instead of a regulated voltage V out . Furthermore, the rectifier 20 , the sensor 22 , or both the rectifier and the sensor may be disposed in the high-side path (i.e., the path that is at voltage V int — 2 ) instead of in the low-side path. Moreover, the energy-storage circuit 16 may be omitted, and the driver 14 may generate I int — 2 directly. In addition, although described as being a DCM power supply, the power supply 10 may be another type of supply, such as a continuous-mode (CCM) power supply that sometimes operates in a discontinuous mode. For example, the power supply 10 may operate predominantly in a discontinuous mode, but may sometimes operate in a continuous mode, such as during a load transient.

FIG. 2 is a schematic diagram of a portion 30 of the power supply 10 of FIG. 1 according to an embodiment.

The driver 14 includes an input filter capacitor C 1 , a switching drive NMOS transistor Q 1 , and a voltage-clamping circuit 32 . The gate of the transistor Q 1 is driven by circuitry that is omitted from FIG. 2 for clarity.

The energy-storage circuit 16 includes a transformer T 1 having a primary winding Np coupled to the driver 14 , and having a secondary winding Ns, which is magnetically coupled to the primary winding per the dot convention shown in FIG. 2 .

The regulator 18 includes an input filter capacitor C 2 , and the remaining section of the regulator is omitted from FIG. 2 for brevity.

The rectifier 20 includes an NMOS transistor Q 2 , and the current sensor 22 includes a transformer T 2 having a primary winding 34 configured to receive the current I int — 2 , and a secondary winding 36 , which is magnetically coupled to the primary winding 34 per the dot convention shown in FIG. 2 , and which is configured to provide the signal SENSE to the controller 24 .

The controller 24 includes a circuit 38 configured to activate and deactivate the transistor Q 2 in response to the current I int — 2 flowing in a forward direction (the forward direction is indicated by the arrow over “I int — 2 ” in FIG. 2 ), and includes a circuit 40 configured to deactivate the transistor Q 2 in the event that I int — 2 flows in a reverse direction.

The circuit 38 includes diodes D 1 and D 2 , a bias resistor R 1 , a bipolar NPN transistor Q 3 , and a bias-voltage generator 42 configured to generate a bias voltage V 1 . As further described below, the value of R 1 determines at what value of the forward current I int — 2 the transistor Q 2 turns off, i.e., deactivates.

And the circuit 40 includes diodes D 3 and D 4 and a bipolar PNP transistor Q 4 .

FIG. 3 is plot of the current I int — 2 of the power-supply portion 30 of FIG. 2 versus time according to an embodiment.

FIG. 4 is a plot of the gate voltage of the transistor Q 2 of FIG. 2 versus time overlaid with a plot of the current I int — 2 of FIG. 2 versus time according to an embodiment.

FIG. 5 is a plot of the drain voltage of the transistor Q 2 of FIG. 2 versus time overlaid with a plot of the current I int — 2 of FIG. 2 versus time according to an embodiment.

FIG. 6 is another plot of the drain voltage of the transistor Q 2 of FIG. 2 versus time overlaid with a plot of the current I int — 2 of FIG. 2 versus time, with a higher-resolution time scale relative to the overlaid plots of FIG. 5 according to an embodiment.

Referring to FIGS. 2-6 , operation of the portion 30 of the power supply 10 of FIG. 1 is described according to an embodiment.

During a charging portion of the transistor Q 1 switching cycle ( FIG. 3 ) between times t 0 and t 1 , Q 1 is activated such that it draws a current through the primary winding Np of the transformer T 1 . This forces the dotted nodes of the primary and secondary windings Np and Ns to low voltage levels relative to the respective undotted winding nodes. Normally, this would cause the secondary winding Ns to source a reverse current I int — 2 ; but because the transistor Q 2 is deactivated, and its body diode is reverse biased, the secondary winding does not generate a current. Therefore, the energy generated by the current flowing through the primary winding Np is stored in the transformer's magnetic field.

At time t 1 , the transistor Q 1 is deactivated such that it stops drawing a current through the primary winding Np of the transformer T 1 .

During a discharging portion of the transistor Q 1 switching cycle ( FIG. 3 ) between times t 1 and t 2 , the voltage clamping circuit 32 provides a path for the leakage inductance (not shown in FIG. 2 ) of the transformer T 1 , referred to the primary winding Np, to discharge by sourcing a primary-side discharge current that flows clockwise through the primary winding and the clamping circuit; furthermore, the voltage clamping circuit limits the voltage across the primary winding to a predetermined value (e.g., 20 Volts) to protect Q 1 from excessive voltage-induced stress.

Further during the discharging portion of the transistor Q 1 switching cycle ( FIG. 3 ) between the times t 1 and t 2 , the energy stored in the magnetic field of the transformer T 1 during the charging portion of the Q 1 switching cycle dissipates by causing a forward current I int — 2 to flow through the secondary winding Ns (i.e., in the direction shown by the arrow over “I int — 2 ” in FIG. 2 ), where I int — 2 dissipates approximately linearly from an initial, maximum value at time t 1 to zero at time t 2 .

As I int — 2 begins to flow at time t 1 , the transistor Q 2 is initially inactive; therefore, I int — 2 initially flows through the primary winding 34 of the transformer T 2 and the forward-biased body diode of Q 2 .

This initial flow of I int — 2 through the primary winding 34 of the transformer T 2 forces the dotted nodes of the primary winding and the secondary winding 36 to high voltage levels relative to the respective undotted nodes, and the voltage across the secondary winding causes a current SENSE to flow through the secondary winding in the direction shown by the arrow. In more detail, the voltage across the secondary winding 36 causes the voltage V CE across the collector-emitter junction of the transistor Q 3 to drop to the voltage V BE across the base-emitter junction of Q 3 such that Q 3 begins to conduct (the limiting of V CE to V BE is described below), and the current SENSE begins to flow after Q 3 begins to conduct.

The current SENSE flows to the diode D 2 , and a first portion of this current flows through the diode D 1 , a second portion of this current flows through the diode D 2 into the base of the transistor Q 3 , thus activating Q 3 , and a third portion flows through the resistor R 1 . The diode D 1 has at least two effects. The first effect is that the diode D 1 serves to conduct away an excess amount of the current SENSE so as to maintain the base current of the transistor Q 3 at a level that is low enough to prevent damage to Q 3 . The second effect, which can be shown by application of Kirchoff's voltage law around the two circuit loops that include the secondary winding 36 of the transformer T 2 , is that the diode D 1 limits the minimum value of the voltage V CE across the collector-emitter junction of the transistor Q 3 to approximately the voltage V BE across the base-emitter junction of Q 3 ; this limiting of the minimum value of V CE may keep Q 3 out of saturation, and thus may allow Q 3 to deactivate faster than if it were to saturate.

Consequently, the transistor Q 3 couples an activation voltage equal to approximately V 1 −V CE =V 1 −V BE to the gate of the transistor Q 2 , thus activating Q 2 . Per FIG. 4 , the transistor Q 3 applies this activation voltage to the gate of the transistor Q 2 relatively quickly after I int — 2 begins to flow at time t 1 . Furthermore, the voltage at the node of the resistor R 1 that is coupled to the base of the transistor Q 3 is at approximately the voltage V 1 , and, therefore, the current though R 1 is approximately V 1 /R 1 (assuming that the voltage drop across the primary winding 34 of the transformer T 2 is relatively small).

After the transistor Q 2 turns on (i.e., activates), the current I int — 2 stops flowing through the body diode of Q 2 , and instead flows from the drain to the source of Q 2 . Therefore, the voltage across the transistor Q 2 drops from a forward-biased-P-N-junction voltage to a significantly smaller voltage equal to the product of I int — 2 and R ds — on , which is the resistance between the drain and the source of Q 2 while Q 2 is active. Because the power dissipated in the transistor Q 2 is equal to the product of I int — 2 and the drain-source voltage V DS across Q 2 , by activating Q 2 relatively quickly, the controller 24 limits the power loss in Q 2 by limiting the time that I int — 2 flows through Q 2 's body diode.

At a time t 0 ( FIG. 4 ), the decrease in the forward current I int — 2 is enough to decreases the current SENSE to a point where SENSE cannot maintain the voltage at the base of the transistor Q 3 at approximately V 1 due to the current being sunk through the resistor R 1 ; therefore, the voltage at the gate of the transistor Q 2 also begins to decrease. As the current SENSE continues to decrease, the voltage at the gate of the transistor Q 2 also continues to decrease. And during this period of decreasing gate voltage, the transistor Q 2 operates in its triode region, and thus operates as voltage-controlled resistor. Therefore, as the gate voltage of Q 2 decreases, R ds — on of Q 2 increases.

At a time t b , the voltage at the gate of the transistor Q 2 decreases to a level that causes Q 2 to deactivate.

If there is still a forward current I int — 1 flowing after Q 2 deactivates, then, after R ds — on of Q 2 decreases to a point where the drain-source voltage V ds of Q 2 exceeds the activation voltage of Q 2 's body diode, I int — 1 begins to flow through Q 2 's body diode as described below in conjunction with FIG. 6 .

Referring to FIG. 6 , during the period from the time t b to the time t 2 , a “last gasp” of the current I int — 2 flows through the body diode of the transistor Q 2 ; but the period between t b and t 2 may be short enough, and the product of I int — 2 and the forward voltage of the body diode (i.e., the power dissipated by Q 2 ) during this period small enough, so as to negligibly increase the total power dissipated by Q 2 during the Q 1 switching cycle. The time from t b to t 2 may act as a buffer period that allows Q 2 to fully deactivate before I int — 2 begins to flow in a reverse direction.

Furthermore, FIG. 6 also shows that the drain voltage of the transistor Q 2 increases linearly as I int — 2 decreases; this is due to the drain voltage increasing toward ground as I int — 2 decreases.

Referring to FIG. 3 , the period between the times t 2 and t 3 is the discontinuous portion of the transistor Q 1 switching cycle, during which Q 1 is still inactive and I int — 2 is not flowing, i.e., is equal to zero. Referring to FIG. 5 , although parasitic currents may flow between the drain and source of the transistor Q 2 and in the primary winding 34 of T 2 as evidenced by the oscillation of the voltage at the drain of Q 2 during the discontinuous period, these currents are too small to turn on Q 2 ; therefore, these currents do not cause I int — 2 to flow in a reverse direction, and to discharge C 2 , during the discontinuous period.

Referring to FIGS. 2-6 , the power-supply portion 30 repeats the above-described operation for each subsequent switching cycle of the transistor Q 1 .

Still referring to FIGS. 2-6 , if I int — 2 does reverse its direction before the transistor Q 2 deactivates, then the transistor Q 4 deactivates Q 2 . If a reverse current I int — 2 begins to flow, this causes a reverse current to flow through the secondary winding 36 of the transformer T 2 , the emitter-collector junction of the transistor Q 4 , and the diode D 4 , and also causes a base current to flow from the base of Q 4 through the diode D 3 . Therefore, the current sunk by the emitter of the transistor Q 4 discharges the gate of the transistor Q 2 , and thus deactivates Q 2 , relatively quickly, thus limiting the amount of time during which I int — 2 can flow in a reverse direction. A reason that the current I int — 2 may flow in a reverse direction is if one sets the value of the resistor R 1 so as to reduce the time period between t b and t 2 , during which I int — 2 flows through the body diode of the transistor Q 2 , to approximately zero; if R 1 is too big due, for example, to a tolerance issue, then Q 2 may not completely deactivate before I int — 2 reverses its direction.

Referring to FIG. 2 , alternate embodiments of the power-supply portion 30 are contemplated. For example, the diode D 4 may be omitted, and one or more of the diodes D 1 -D 3 may be replaced with other voltage-dropping components such as a Zener diode or a resistor. Furthermore, the circuit 40 may be omitted. Moreover, the transformer T 2 may be replaced with another current-sensing component such as a Hall-effect device or an optical coupler. In addition, the transformer T 1 may be replaced with an inductor circuit. Furthermore, although the power-supply portion 30 is disclosed as being a portion of a flyback power supply, an embodiment of the rectifying circuit 12 , or of any other circuit that implements one or more of the rectifying principles described above, may be used with any other type of power supply that is configured to operate in a discontinuous mode.

FIG. 7 is a schematic diagram of a portion 50 of the power supply 10 of FIG. 1 according to an embodiment. The portion 50 is similar to the portion 30 of FIG. 2 except that the transistor Q 3 , the diode D 1 , and the voltage generator 42 are omitted from the circuit 38 . In operation, while the current I int — 2 is flowing in a forward direction, the current SENSE from the secondary winding 36 of the transformer T 2 flows through the resistor R 1 , and, therefore, generates, at the gate of the transistor Q 2 , a voltage that is approximately equal to the product of R 1 and SENSE. Therefore, in a manner similar to that described above in conjunction with FIG. 2 , one can select the value of the resistor R 1 to set the magnitude of I int — 2 at which the transistor Q 2 deactivates, and thus can set the time t b at which Q 2 becomes inactive.

Still referring to FIG. 7 , alternate embodiments of the power-supply portion 50 are contemplated. For example, the one or more of the diodes D 2 -D 4 may be omitted, or may be replaced with another component such as a resistor or a Zener diode. Furthermore, the circuit 40 (i.e., the transistor Q 4 , and the diodes D 3 and D 4 ) may be omitted.

FIG. 8 is a functional block diagram of an electronic system 60 , which includes processing circuitry 62 containing one or more of the embodiments of the power supply 10 of FIG. 1 . The processing circuitry 62 includes circuitry for performing various functions, such as executing specific software to perform specific calculations or controlling the system 60 to provide desired functionality. In addition, the electronic system 60 includes one or more input devices 64 , such as a keyboard, mouse, touch screen, audible or voice-recognition component, and so on, coupled to the processing circuitry 62 to allow an operator to interface with the electronic system. Typically, the electronic system 60 also includes one or more output devices 66 coupled to the processing circuitry 62 , where the output devices can include a printer, video display, audio output components, and so on. One or more data-storage devices 68 are also typically coupled to the processing circuitry 62 to store data or retrieve data from storage media (not shown). Examples of typical data storage devices 68 include magnetic disks, FLASH memory, other types of solid state memory, tape drives, optical disks like compact disks and digital video disks (DVDs), and so on.

Still referring to FIG. 8 , in an embodiment, at least a portion of the processing circuitry 62 and at least a portion of the power supply 10 are disposed on respective integrated-circuit dies 70 and 72 .

From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.