Method of capturing an image with an image sensor

The present invention relates to a method of capturing an image using an image sensor.

Typical image sensors comprise an array of pixels. Each pixel has a capacitive node to collect electrical charge generated at an accumulation node when it is exposed to incident light, and its sensitivity to light variations from one image to another depends on the capacitance of this capacitive node. FIG. 1 shows the structure of two adjacent pixels P i,j , of a typical array of pixels AP 0 . Pixel P i,j belongs to a row of rank i, pixel P i+1,j belongs to a row of rank 1 +1, and both belong to a column Cj. Each pixel comprises a photosensor PS (or photodetector) embedded in a semiconductor substrate, an accumulation node N 0 formed by the cathode of the photosensor, and a capacitive node N 1 having a capacitance IC shown in dotted lines as a capacitor. The capacitive node N 1 is coupled to the accumulation node N 0 through a transfer transistor TT, to a voltage VS through a reset transistor RT, and to an output line CLj through a source-follower transistor FT and an output transistor OT. The source-follower transistor FT has a gate connected to the capacitive node N 1 , a drain receiving voltage VS, and a source connected to a drain of the output transistor OT, which has a source connected to the output line CLj.

In a typical embodiment of a method of capturing an image with such an array of pixels, the pixels are read on a row-by-row basis with overlapping row read cycles. All the pixels of a selected row (“current row”) are simultaneously read in one row read cycle comprising individual pixel read cycles. The pixels of the next row to be read (“next row”) are subject to read cycles that overlap the read cycles of the pixels of the current row with a determined time offset.

FIG. 2 is a timing diagram of three logic control signals TS, RS, OS involved in a pixel read cycle. Signal TS is a transfer signal applied to a gate of the transfer transistor TT. Signal RS is a reset signal applied to a gate of the reset transistor RT. Signal OS is a readout signal applied to a gate of the output transistor OT. Each control signal is, for example, set to 1 when the corresponding transistor is set in the conducting state (“ON” state), and is set to 0 when the transistor is to be blocked (“OFF” state).

The read cycle is performed between times t 0 and t 9 , and comprises intermediate times t 1 , t 2 . . . t 8 corresponding to rising or falling edges of some of the control signals. Signal TS is set to 1 from t 2 to t 3 and from t 7 to t 8 . Signal RS is set to 1 from t 9 of the previous pixel read cycle to t 1 , from t 4 to t 6 , and from t 9 to t 1 of the next pixel read cycle. Signal OS is set to 1 from t 5 to t 10 . The read cycle may comprise the following steps: S 1 : First reset of the capacitive node N 1 (from t 9 of the previous read cycle to t 1 of the current read cycle): The reset transistor RT is ON and node N 1 is tied to voltage VS. T 1 : First transfer of charges (from t 2 to t 3 ): The transfer transistor TT is ON, and the reset transistor RT is OFF. Electrical charges accumulated by the photosensor at node N 0 are transferred to node N 1 . A 1 : Charge accumulation (from t 3 to t 7 ): The transfer transistor TS is OFF and electrical charges are accumulated at node N 0 . S 2 : Second reset of the capacitive node N 1 (from t 4 to t 6 ): The reset transistor RT is ON and node N 1 is tied to voltage VS. C 1 : Connection of node N 1 to the output line CLj (from t 5 to t 10 ): The output transistor OT is ON and the capacitive node N 1 is coupled to the output line through transistors FT, OT. R 1 : First read of node N 1 (from t 6 to t 7 ): Transistors RT and TT are OFF and transistor OT is ON. The voltage at node N 1 is transferred to line CLj through transistors FT and OT, and is read (i.e. sensed) by peripheral means connected to this line (not shown) T 2 : Second transfer of charges (from t 7 to t 8 ): The transfer transistor TT is ON, and the reset transistor RT is OFF. Electrical charges accumulated at node N 0 during step Al are transferred to node N 1 . R 2 : Second read of node N 1 (from t 8 to t 9 ): The voltage at node N 1 is transferred to line CLj through transistors FT and OT.

The voltage at the capacitive node N 1 is thus read twice, once after the reset R 1 and once after the transfer of charges T 2 , and is supplied to an image processing system for determination of a pixel data. It may happen that the lighting conditions present variations between extreme lighting conditions—from very bright lighting to very dark lighting—which are such that the capacitance of the capacitive node N 1 is inappropriate for capturing an image in one of the extreme lighting conditions. If it has a small capacitance, the capacitive node N 1 may not be able to receive all the electrical charges accumulated by node N 0 in very bright conditions. Conversely, if it has a large capacitance, it may not be possible to differentiate small lighting variations in dark conditions since the voltage at node N 1 varies too little from one transfer step to another to be properly sensed.

It may thus be desired to provide an image sensor with adjustable sensitivity, for improved functioning in both dark and bright lighting conditions. U.S. Patent Application Publication No 2008/0231727 discloses a method for adjusting the dynamic range of an image sensor on a pixel-by-pixel basis. The method may comprise integrating charges in a photodetector with the photodetector at a first capacitance, reading the resulting signal level at a first time with the photodetector at the first capacitance, changing the photodetector capacitance to a second capacitance, and reading the signal level associated with the photodetector at the second capacitance. To change the capacitance of the capacitive node, the node of a current pixel (pixel being read) is connected both to the capacitive node of a previous pixel (pixel previously read) and to the capacitive node of a next pixel (pixel to be read during a next pixel read cycle).

This method may be incompatible with overlapping read cycles since connecting the capacitive node of the current pixel (pixel being read) to the capacitive node of the next pixel (pixel to be read) prevents the next pixel from correctly performing the accumulation step due to crosstalk between photosensors. Even if its transfer transistor is OFF, the crosstalk may disturb the charge accumulation process of the next pixel when its capacitive mode is connected to the capacitive node of the current pixel.

In other respects, this method aims to extend the dynamic range of each pixel for a given image, by a real-time comparison of two voltage values corresponding to two capacitance values of the capacitive node, which amounts to extending the global dynamic range of the image sensor to accommodate large lighting variations within a single image. This may imply storing numerous voltage values for each pixel, two per capacitance value of the pixel, and post-processing of the voltage values to decide which one must be retained, thereby possibly necessitating powerful processing demands.

It may be desired to provide an image capture method that is simple to implement while allowing the sensitivity of pixels to be set for a given image.

It also may be desired to provide an image sensor having a variable sensitivity, which can be adjusted from one image to another, to adapt the sensitivity of the array of pixels or parts thereof to the overall brightness of the captured image.

An aspect of the present disclosure is directed to a method of capturing at least one image with an array of pixels, each pixel comprising a photosensitive accumulation node and a capacitive node. The method may comprise a cycle of reading a current pixel comprising: connecting the capacitive node of the pixel to at least one capacitive node of a previous pixel already read, reading a first voltage of the capacitive node of the pixel, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel, and disconnecting the capacitive node from the at least one capacitive node of a previous pixel. The method may also comprise a cycle of reading a next pixel, the cycle overlapping the cycle of reading a current pixel and comprising accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to at least one capacitive node of a previous pixel.

According to some embodiments, the method may comprise resetting the capacitive node of the next pixel while the capacitive node of the current pixel is connected to at least one capacitive node of a previous pixel. According to another embodiment, the method may comprise capturing a first image without connecting the capacitive node of each current pixel to a capacitive node of a previous pixel, analyzing the image, and depending on the result of the analysis, capturing a second image with connecting the capacitive node of at least one current pixel to at least one capacitive node of a previous pixel or capturing the second image without connecting the capacitive node of each current pixel to a capacitive node of a previous pixel.

According to one embodiment, the method may comprise before accumulating charges in the accumulation node of the current pixel, resetting the capacitive node of the current pixel, and transferring charges from the accumulation node to the capacitive node of the current pixel, to reset the accumulation node. According to another embodiment, each capacitive node may be coupled to the output line through a source-follower transistor and an output transistor, and coupling a capacitive node to the output line may comprise setting the output transistor in a conducting state.

According to other embodiments, the method may comprise resetting the at least one capacitive node of a previous pixel while the output transistor is set in a conducting state, and resetting the capacitive node of the at least one previous pixel while the output transistor is then set in a non-conducting state. According to yet another embodiment, the resetting of a capacitive node may comprise applying a determined voltage to the capacitive node. Also, the pixels may be arranged in rows and columns, and the method may comprise capturing the image row-by-row with overlapping row read cycles each comprising a plurality of pixel read cycles, and selecting the at least one previous pixel in a previously read row and in the same column as the current pixel.

Another aspect is directed to an imaging device comprising an array of pixels, and control means or a controller to select and read pixels of the array of pixels. Each pixel may comprise a photosensitive accumulation node and a capacitive node. The controller may be configured to perform the method of capturing at least one image with the array of pixels. Additionally, the controller may be configured to reset the capacitive node of the next pixel while the capacitive node of the current pixel is connected to at least one capacitive node of a previous pixel.

According to some embodiments, the controller may be configured to capture a first image without connecting the capacitive node of each current pixel to a capacitive node of a previous pixel, analyze the image, and depending on the result of the analysis, capture a second image by connecting the capacitive node of at least one current pixel to at least one capacitive node of a previous pixel or capture the second image without connecting the capacitive node of each current pixel to a capacitive node of a previous pixel. Also, the pixels may be arranged in rows and columns, and the controller may be configured to capture the image row-by-row with overlapping row read cycles comprising each a plurality of pixel read cycles, and select the at least one previous pixel in a previously read row and in the same column as the current pixel. According to one embodiment, each capacitive node may be coupled to the output line through a source-follower transistor and an output transistor, and connecting a capacitive node to the output line comprises setting the output transistor in a conducting state.

Embodiments of the present invention will now be described in connection with, but not limited to, the appended drawings in which:

FIG. 1 is a pixel structure in an array of pixels, according to the prior art.

FIG. 2 is a timing diagram of a pixel read cycle, according to the prior art.

FIG. 3 is a schematic block diagram of an image sensor comprising an array of pixels, according to the present invention.

FIG. 4 is a portion of an embodiment of the array of pixels of FIG. 3 .

FIG. 5 is a timing diagram of an embodiment of a method of capturing an image comprising overlapping pixel read cycles, according to the present invention.

FIG. 6 is a timing diagram of another embodiment of an image capture method comprising overlapping pixel read cycles, according to the present invention.

FIG. 7 is a portion of another embodiment of the array of pixels of FIG. 3 .

FIG. 8 is a portion of another embodiment of the array of pixels of FIG. 3 .

FIG. 3 shows an image sensor IS according to an embodiment of the present invention. The image sensor IS comprises an array of pixels AP 1 , a row decoder RDEC, a column decoder CDEC, readout circuitry RC, and a control circuit CCT. The control circuit CCT and the readout circuitry RC are coupled to an external processing unit EPU. Embodiments AP 11 , AP 12 , AP 13 of the array of pixels AP 1 will be described hereinafter in connection with FIGS. 4 , 7 , and 8 . It will be noted that the column decoder CDEC is optional and only used in connection with the array of pixels AP 13 of FIG. 8 .

As shown in FIG. 4 , the array of pixels API comprises pixels P I,J arranged in rows R I of rank i and in columns C J of rank j. Only four pixels P i,j , P i+1,j , P i+2,j , P i+3,j belonging to rows R i , R i+1 , R i+2 , R i+3 and to a column Cj are shown, as well as output line CL j allocated to column C J . Each pixel P comprises a photosensor PS, shown as a photodiode, embedded in a semiconductor substrate, an accumulation node N 0 formed by the cathode of the photosensor PS, and a capacitive node N 1 . The capacitive node N 1 is coupled to the accumulation node N 0 through a transfer transistor TT, to a voltage VS through a reset transistor RT, and to an output line CLj through a source-follower transistor FT and an output transistor OT. The source-follower transistor FT has a gate connected to the capacitive node N 1 , a drain receiving voltage VS, and a source connected to a drain of the output transistor OT, which has a source connected to the output line CLj. The readout circuitry RC is connected to the output lines CLj and provides voltages V(N 1 ) I,j read on the capacitive nodes N 1 of the different pixels of column C J .

The capacitive node N 1 has a capacitance shown with dotted lines as a capacitor IC, which may be an intrinsic capacitance of node N 1 , for example, if node N 1 comprises a floating diffusion (doped semi-conductor region). Generally speaking, node N 0 , transistor TT, and node N 1 together form charge-to-voltage conversion means or a charge conversion circuit. Transistor TT may be a simple transfer gate between a first semiconductor region forming node N 0 and a second semiconductor region forming node N 1 , instead of a complete transistor with source and drain regions.

Each pixel also comprises a connection transistor CT which couples its capacitive node N 1 to the capacitive node N 1 of a previous pixel. By “previous,” it is meant here a pixel read before the considered pixel during an image capture, and which belongs to another row. By convention, rows will be read here in increasing rank order, and a “previous” pixel is a pixel in a row having a rank i inferior to that of the considered row. In one embodiment, the previous pixel is located in the same column as the considered pixel. In the embodiment shown in FIG. 4 , and pixel P i+3,j has a connection transistor CT, which couples its node N 1 to node N 1 of pixel P i+2,j ; pixel P i+2,j has a connection transistor CT, which couples its node N 1 to node N 1 of pixel P i+1,j ; and pixel has a connection transistor CT, which couples its node N 1 to node N 1 of pixel P i,j , and so forth.

At the upper edge of the array of pixels (not shown), nodes N 1 of the first row of pixels cannot be, in principle, coupled to the nodes of pixels of a previous row since there are no previous rows. However, in some embodiments, the array may comprise one or more dummy rows, i.e. rows of pixels which are not controlled by the row decoder. In that case, the nodes of the pixels of the first row may be coupled to the nodes N 1 of the pixels present in such dummy rows.

Referring again to FIG. 3 , the array of pixels AP 11 is coupled to the row decoder RDEC and to the readout circuitry RC, which are both coupled to circuit CCT. Circuit CCT is configured to select and read the pixels on a row-by-row basis with overlapping row read cycles, by way of the row decoder and the readout circuitry. In an embodiment, all the pixels of a selected row (“current row”) are simultaneously selected and read in a row read cycle comprising simultaneous pixel read cycles. The reading of the pixels of a row is performed by way of the readout circuitry RC, through different output lines CLj.

Once an image has been captured, the external processing unit EPU analyzes the different voltages V(N 1 ) I,J read on the capacitive nodes N 1 of the different pixels P I,J , and decides whether the capacitive nodes N 1 must be connected to one or more capacitive nodes N 1 of one or more previously read pixels, to increase their capacitance. The decision to connect or not to connect additional capacitive nodes is communicated to control circuit CCT and executed by the latter during the next read cycle.

For example, if the different voltages V(N 1 ) I,J are high and close to a saturation value, the external processing unit EPU may decide to connect the capacitive node of each pixel to the capacitive node of a previous pixel, to extend its capacitance. If the different voltages V(N 1 ) I,J remain high and close to the saturation value when the next image is captured, or after several image captures, the external processing unit EPU may decide to connect the capacitive node N 1 of each pixel to an additional capacitive node of a further previous pixel.

In some embodiments, voltages V(N 1 ) I,J may be compared to different threshold voltages and the external processing unit EPU may decide to connect one additional capacitive node N 1 to the capacitive node N 1 of each pixel if voltages V(N 1 ) I,J are greater than a first threshold, two additional capacitive nodes N 1 to the capacitive node N 1 of each pixel if voltages V(N 1 ) I,J are greater than a second threshold, and so forth.

FIG. 5 is a timing diagram showing one embodiment of pixel read cycles RC I (RC i , RC i+1 , RC i+2 , RC i+3 ) performed on pixels P i,j , P i+1,j , P i+2,j , P i+3,j shown in FIG. 4 , respectively. For each pixel, FIG. 5 shows four logic control signals TS, RS, OS, CS involved in the read cycle of each pixel and supplied by the row decoder RDEC. The control signals applied to the different pixels are differentiated each other by their rank “i” (from TS i , RS i , OS i , CS i for pixel P i,j to TS i+3 , RS i+3 , OS i+3 , CS i+3 for pixel P i+3,j ): TS is a transfer signal applied to a gate of the transfer transistor TT; RS is a reset signal applied to a gate of the reset transistor RT; OS is a readout signal applied to a gate of the output transistor OT; and CS is a connection signal applied to a gate of the connection transistor CT, to connect the capacitive node N 1 of the considered pixel to the capacitive node of a previous pixel.

Each control signal is set to 1 when the corresponding transistor must be set in the conducting state (ON state), and is set to 0 when the transistor must be blocked (“OFF” state). Each read cycle is performed between times t 0 and t 13 , and comprises intermediate times t 1 , t 2 , . . . t 12 corresponding to rising or falling edges of some of the control signals: TS is set to 1 from t 2 to t 3 and from t 7 to t 8 ; RS is set to 1 from t 13 of the precedent read cycle to t 1 , from t 4 to t 6 , and from t 13 to t 1 of the next read cycle; OS is set to 1 from t 5 to t 10 ; and CS is set to 1 from t 5 to t 10 and from t 11 to t 12 .

The read cycles shown in FIG. 5 correspond to the case when the external processing unit EPU has decided to connect the capacitive node N 1 of each pixel P to two nodes N 1 of previous pixels. The read cycles therefore comprise, for each current pixel, the following steps:

S 1 : First reset of the capacitive node N 1 (from t 13 of previous read cycle to t 1 ): The reset transistor RT is ON and node N 1 is tied to voltage VS. T 1 : First transfer of charges (from t 2 to t 3 ): The transfer transistor TT is ON, and the reset transistor RT is OFF. Electrical charges previously accumulated by the photosensor at node N 0 are transferred to node N 1 . This step amounts to resetting node N 0 by transferring its electrical charge to node N 1 after resetting thereof. A 1 : Charge accumulation (from t 3 to t 7 ): The transfer transistor TS is OFF and electrical charges are accumulated at node N 0 , whatever the state of the reset transistor RT. S 2 : Second reset of the capacitive node N 1 (from t 4 to t 6 ): The reset transistor RT is ON and node N 1 is tied to voltage VS. I 1 : Connection of node N 1 to at least one capacitive node N 1 of a previous pixel (from t 5 to t 10 ): Transistor CT is ON and the capacitive node N 1 is connected to the capacitive node N 1 of a previous pixel, here two previous pixels, so that its capacitance is increased. C 1 : Connection of node N 1 to the output line CLj (from t 5 to t 10 ) by setting the output transistor OT in a conducting state (Cf. FIG. 4 ). R 1 : First read of node N 1 (from t 6 to t 7 ): Transistors RT and TT are OFF and transistor OT is ON. The voltage at node N 1 , which has just been reset, is transferred to line CLj through transistors FT and OT and is read by the readout circuitry RC (for the sake of simplicity, the threshold voltages of transistors FT, OT are considered to be zero). T 2 : Second transfer of charges (from t 7 to t 8 ): The transfer transistor TT is ON, and the reset transistor RT is OFF. Electrical charges accumulated by the photosensor at node N 0 during step A 1 are transferred to node N 1 . R 2 : Second read of node N 1 (from t 8 to t 9 ): Transistors RT and TT are OFF and transistor OT is ON. The voltage at node N 1 is transferred to line CLj through transistors FT and OT and is read by the readout circuitry RC. I 2 : Connection of node N 1 to at least one capacitive node N 1 of a previous pixel (from t 11 to t 12 ): Transistor CT is ON, and the capacitive node N 1 is connected to the capacitive node N 1 of a previous pixel.

It appears in FIG. 5 that each succeeding read cycle overlaps the precedent read cycle so that step I 1 is performed at the same time as step 12 of the precedent cycle. Therefore, referring, for example, to the read cycle RC i+2 of pixel P i+2,j , steps R 1 , T 2 , R 2 of cycle RC i+2 occur when the node N 1 of the current pixel P i+2,j is connected to the node N 1 of the previous pixel P i+1,j (CS i+2 =1), which is itself connected to the node N 1 of the previous pixel P i,j (CS i+1 =1).

Although step 12 has been presented as a step of the read cycle of a given pixel by commodity, strictly speaking, step 12 belongs to the read cycle of the next pixel, which has its node N 1 connected to node N 1 of the given pixel, since the reading of the given pixel is finished when step 12 has been performed. Step 12 allows the node of the next pixel, when it is the current pixel, to be connected to the node N 1 of a pixel which is the previous pixel with respect to the given pixel, when the next pixel undergoes steps R 1 , T 2 , R 2 . Indeed, if the external processing unit EPU has decided to connect a current pixel to only one node N 1 of a previous pixel instead of two, step 12 is not performed.

As to the overlapping of the different pixel read cycles, it can be noted that time t 5 i (i.e. t 5 of cycle RC i ) is equal to t 4 i+1 (i.e. time t 4 of cycle RC i+1 ) and that t 11 i =t 5 i+1 . Also, t 13 1 =t 9 i+2 , which means that node N 1 of pixel P i,j is not reset (beginning of step S 1 ) until step R 2 of pixel P 1+2,j has been achieved. It will also be understood that the node N 1 of a pixel undergoing a read cycle is never connected to the node N 1 of a next pixel, which is beginning a read cycle. More particularly, when read step R 1 , transfer step T 2 , then read step R 2 are applied to a pixel, the next pixel has its node N 0 undergoing the accumulation step Al and its node N 1 undergoing the reset step S 2 . For example, while steps R 1 , T 2 , R 2 are performed on pixel P i+1,j (read cycle RC i+1 ), node N 0 of pixel P i+2,j (read cycle RC i+2 ) is undergoing the accumulation step A 1 , and node N 1 of that pixel is undergoing the reset step S 2 .

In other embodiments, the reset step S 2 of the next pixel may be postponed, for example, until steps R 1 , T 2 , R 2 of the current pixel have been performed. In that case, signal RS would be set to 1 at time t 10 of the read cycle of the previous pixel, instead of being set to 1 at time t 4 of the read cycle of the considered pixel. In some embodiments, the external processing unit EPU may be configured to extend the capacitance of the pixels on a row-by-row basis, instead of setting the entire array of pixels at a given capacitance. In that case, the previously captured image is analyzed row by row, to determine which rows must have the capacitances of their pixels extended.

FIG. 6 is a timing diagram showing another embodiment of pixel read cycles RC′ I (RC′ i , RC′ i+1 , RC′ i+2 , RC′ i+3 ) performed on pixels P i,j , P i+1,j , P i+2,j , P i+3,j shown in FIG. 4 . For each pixel, the control circuit CCT supplies the four logic control signals TS, RS, OS, CS previously described with a timing different than that of FIG. 5 , which comprises times t 0 to t 22 :

TS is set to 1 from t 2 to t 3 and from t 7 to t 8 , RS is set to 1 from t 21 (of the precedent read cycle) to t 1 , from t 4 to t 6 , from t 9 to t 11 , from t 12 to t 14 , from t 15 to t 17 , from t 18 to t 20 , and from t 21 to t 1 of the next read cycle, OS is set to 1 from t 5 to t 10 , from t 13 to t 16 , and from t 19 to t 22 , and CS is set to 1 from t 5 to t 10 and from t 13 to t 16 .

It is again assumed in this example that the external processing unit EPU has decided to connect the capacitive node N 1 of each pixel to two nodes N 1 of previous pixels. The read cycle therefore comprises the following steps, for each current pixel:

Step S 1 : First reset of node N 1 (from t 21 of previous cycle to t 1 ), T 1 : First transfer of charges (from t 2 to t 3 ), A 1 : Charge accumulation (from t 3 to t 7 ), S 2 : Second reset of node N 1 (from t 4 to t 6 ), I 1 : Connection of node N 1 to at least one capacitive node of a previous pixel (from t 5 to t 10 ), C 1 : Connection of node N 1 to the output line CLj (from t 5 to t 10 ), R 1 : First read of node N 1 (from t 6 to t 7 ), T 2 : Second transfer of charges (from t 7 to t 8 ), R 2 : Second read of node N 1 (from t 8 to t 9 ), S 3 : Third reset of node N 1 (from t 9 to t 11 ), S 4 : Fourth reset of node N 1 (from t 12 to t 14 ), I 2 : Connection of node N 1 to at least one capacitive node N 1 of a previous pixel (from t 13 to t 16 ), C 2 : Connection of node N 1 to the output line CLj (from t 13 to t 16 ), S 5 : Fifth reset of node N 1 (from t 15 to t 17 ), S 6 : Sixth reset of node N 1 (from t 18 to t 20 ), and C 3 : Connection of node N 1 to the output line CLj (from t 19 to t 22 ).

It can be seen that read cycles RC′ I differ from read cycles RC I in that the output transistor OT of a previously read pixel is also set in the ON state during steps C 2 , C 3 , when the output transistor OT of the current pixel is set in the ON state and when the node N 1 of the previous pixel is connected to the node N 1 of the current pixel. It follows that all the interconnected nodes N 1 are simultaneously coupled to the output line CL j . This allows a faster reading of the voltage V(N 1 ) of the node N 1 of the current pixel through the output transistor of the current pixel and through the output transistors of the previous pixels to which it is connected. This also diminishes the read noise because the interconnection of the nodes forms an equivalent output transistor having a larger area, and allows a better capacitance matching between nodes N 1 .

For example, during step C 1 of the read cycle RC′ i+2 of pixel P i+2,j , pixel is undergoing step C 2 and pixel P i,j is undergoing step C 3 . Obviously, if node N 1 of pixel P i,j was not to be connected to node N 1 of pixel P i+1,j (decided by the external processing unit EPU), step C 3 would not be performed on that pixel.

According to one aspect of this embodiment, each node N 1 undergoes the reset step S 4 , S 6 each time the corresponding output transistor OT is switched from the OFF state to the ON state (signal OS goes from 0 to 1) and undergoes the reset step S 3 , S 5 each time the corresponding output transistor OT is switched from the ON state to the OFF state (signal OS goes from 1 to 0).

FIG. 7 shows another embodiment AP 12 of the array of pixels AP 1 . Only four pixels P i,j , P i+1,j , P i+2,j , P i+3,j belonging to rows R i , R i+1 , R i+2 , R i+3 and to a column Cj are shown. Array AP 12 differs from array AP 11 in that the node N 1 of each pixel, instead of being coupled to the node N 1 of a pixel located in a previous adjacent row, is coupled to the node N 1 of a pixel located in a row which is previous to the previous adjacent row. For example, pixel P i+3,j has a connection transistor CT which couples its node N 1 to node N 1 of pixel P i+1,j instead of to node N 1 of pixel P i+2,j ; pixel P i+2,j has a connection transistor CT which couples its node N 1 to node N 1 of pixel P i,j instead of to node N 1 of pixel P i+1,j , and so forth. Thus, according to some embodiments of the invention, a “previous” pixel is not necessarily located in an adjacent row.

FIG. 8 shows yet another embodiment AP 13 of the array of pixels AP 1 . Only two pixels P i,j , P i+1,j are shown. Each pixel P differs from a pixel of FIG. 4 in that it comprises a select transistor ST whose source supplies the connection signal CS of rank I,J (CS i,j , CS i+1,j ) to the gate of the connection transistor CT. The select transistor ST receives on its gate a first connection signal XCS of rank I (XCS i , XCS i+1 ) supplied by the row decoder RDEC, and on its drain a second connection signal YCS of rank J (YCS j , YCS j+1 ) supplied by the column decoder CDEC (Cf. FIG. 3 ). When both signals XCS, YCS are set to 1, the resulting connection signal CS is at 1, and the node N 1 of the pixel is connected to the node N 1 of the previous pixel.

Due to these double control signals, the external processing unit EPU may be configured to divide the array of pixels AP 1 into different sectors and decide to connect node N 1 of each pixel to one or more nodes N 1 of previous pixels on a sector-by-sector basis. In that case, a sector is defined as the intersection of one or more rows of pixels and one or more columns of pixels and may comprise a single pixel.

In summary, an image sensor IS according to the embodiments presents variable pixel sensitivity due to the adjustable capacitance of the capacitive nodes N 1 of its pixels. In dark lighting conditions, the capacitance of the capacitive nodes N 1 should be as small as possible and thus the node N 1 of a pixel should not be connected to capacitive nodes of previous pixels, the intrinsic capacitance IC of each node N 1 being sufficient to receive the charges accumulated by the corresponding accumulation node N 0 . In that case, the external processing unit EPU captures an image normally. If the brightness of the following images increase until a saturation threshold is reached, the external processing unit EPU then increases the capacitance of nodes N 1 by connecting them to one or more nodes N 1 of previous pixels, to allow more electrical charges to be collected.

It will be apparent to the skilled person that the present embodiments are susceptible to various other embodiments and applications. In particular, they may be applied to a pixel architecture known as “2T5” which comprises two photosensors coupled to a same capacitive node by two transfer transistors. Color filters may be arranged over the array of pixels to provide filtering of incident light according to the color, for example, according to the Bayer pattern, which comprises green, red, and blue color filters. Dark current prevention means or devices can be supplied, for example, applying a negative voltage to the gate G of transfer transistor TT during the charge accumulation phase.