High voltage offset detection circuit

The present invention is related generally to a high voltage H-bridge driver circuit and, more particularly, to a high voltage offset detection circuit for a high voltage H-bridge driver circuit.

High voltage half-bridge and full-bridge driver circuits are used in various applications such as motors, electronic ballasts, dual-inductor single-capacitor converters, and cold cathode fluorescent lamps (CCFL), and required to convert certain logic signals from low voltage to high voltage in order to control the high-voltage components. For example, in a half-bridge driver circuit as shown in FIG. 1 , control signals Hin and Lin are used to switch a high side switch M 1 and a low side switch M 2 connected in series between a high voltage terminal VIN and a low voltage terminal GND, respectively. The direct-current (DC) supply voltage VIN is very high, maybe up to 600V or above, while the control signal Hin and Lin are generated by a logic circuit with reference to a low voltage power source VCC (e.g. 5V or 12V), and thus the control signal Hin for the high side switch M 1 must be shifted from a low voltage level to a high voltage level. More particularly, in virtue to the operation of a low side circuit 10 , a level shift circuit 12 , and a high side circuit 14 , a control signal S 4 is derived from the control signal Hin for a high voltage driver 20 to generate a control signal UG for controlling the high side switch M 1 . On the other hand, the control signal Lin is directly provided to a low voltage driver 22 to generate a control signal LG for controlling the low side switch M 2 . During the high side switch M 1 is on and the low side switch M 2 is off, the voltage VS at the floating node 24 between the high side switch M 1 and the low side switch M 2 is equal to the DC supply voltage VIN. On the contrary, during the high side switch M 1 is off and the low side switch M 2 is on, the voltage VS at the floating node 24 is equal to the ground voltage GND. Assuming that VS=600V and GND=0V, when the switches M 1 and M 2 are switched, the across voltage thereof can be as high as 600V. Since the on resistance of either of the switches M 1 and M 2 is typically of mΩ order, a high current of kA order may be generated when the switches M 1 and M 2 are switched and likely damages the switch M 1 or M 2 . Such conditions that the switches M 1 and M 2 suffer high across voltage are referred to “hard switching”.

To avoid hard switching, a VS offset detection circuit 16 is used to detect the voltage VS at the floating node 24 , to generate a zero voltage switching (ZVS) signal S 5 for the control signal generator 18 to determine whether a hard switching occurs. If so, a signal S 6 is triggered for the low side circuit 10 to adjust the dead time of the switches M 1 and M 2 . In addition, the signal S 6 may be used to adjust the resonant frequency of the inductor L 1 and the capacitor C 1 , or to turn off the driver circuit. However, in prior arts, for example U.S. Pat. No. 7,049,767, the VS offset detection circuit can detect the voltage VS only when the high side switch is off.

An objective of the present invention is to provide a high voltage offset detection circuit for detecting the voltage at a floating node of a high voltage H-bridge driver circuit.

Another objective of the present invention is to provide a high voltage offset detection circuit for detecting the voltage at a floating node of a high voltage H-bridge driver circuit when a high side switch is on.

According to the present invention, a high voltage offset detection circuit for a high voltage H-bridge driver circuit includes a high voltage device and a ZVS generator. The high voltage H-bridge driver circuit includes a floating node, a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node, a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node, a bootstrap capacitor connected between a high side power source and the floating node, a high voltage driver to provide a first control signal to control the high side switch, and a low voltage driver providing a second control signal to control the low side switch. The high voltage device has an input terminal, an output terminal, a control terminal, and a parasitic capacitance existing between the input terminal and the output terminal of the high voltage device. The input terminal of the high voltage device receives a voltage related to the voltage at the floating node, and the control terminal of the high voltage device receives a voltage to remain the high voltage device off. The ZVS generator detects the voltage at the output terminal of the high voltage device when turning on the high side switch or turning off the low side switch, for triggering a ZVS signal.

According to the present invention, a high voltage offset detection circuit for a high voltage H-bridge driver circuit includes a capacitor and a ZVS generator. The high voltage H-bridge driver circuit includes a floating node, a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node, a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node, a bootstrap capacitor connected between a high side power source and the floating node, a high voltage driver to provide a first control signal to control the high side switch, and a low voltage driver providing a second control signal to control the low side switch. The capacitor has a first terminal to receive a voltage related to the voltage at the floating node, and the ZVS generator detects the voltage at a second terminal of the capacitor when turning on the high side switch or turning off the low side switch, for triggering a ZVS signal.

According to the present invention, a high voltage offset detection circuit for a high voltage H-bridge driver circuit includes a high voltage device and a ZVS generator. The high voltage H-bridge driver circuit includes a floating node, a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node, a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node, a bootstrap capacitor connected between a high side power source and the floating node, a high voltage driver to provide a first control signal to control the high side switch, and a low voltage driver providing a second control signal to control the low side switch. The high voltage device has an input terminal, an output terminal, and a control terminal. The input terminal of the high voltage device receives a voltage related to the voltage at the floating node, and the control terminal of the high voltage device receives a voltage to remain the high voltage device on. The ZVS generator detects the voltage at the output terminal of the high voltage device when turning on the high side switch or turning off the low side switch, for triggering a ZVS signal.

According to the present invention, a high voltage offset detection circuit for a high voltage H-bridge driver circuit includes a high voltage device, a controller, and a ZVS generator. The high voltage H-bridge driver circuit includes a floating node, a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node, a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node, a bootstrap capacitor connected between a high side power source and the floating node, a high voltage driver to provide a first control signal to control the high side switch, and a low voltage driver providing a second control signal to control the low side switch. The high voltage device has an input terminal, an output terminal, and a control terminal. The input terminal of the high voltage device receives a voltage related to the voltage at the floating node, and the ZVS generator detects the voltage at the output terminal of the high voltage device when turning on the high side switch or turning off the low side switch, for triggering a ZVS signal. The controller is connected to the control terminal of the high voltage device for selectively turning off the high voltage device when the ZVS generator detects the voltage at the output terminal of the high voltage device.

According to the present invention, a high voltage offset detection circuit for a high voltage H-bridge driver circuit includes a high voltage device and a ZVS generator. The high voltage H-bridge driver circuit includes a floating node, a high voltage terminal for a high side switch to be connected between the high voltage terminal and the floating node, a low voltage terminal for a low side switch to be connected between the low voltage terminal and the floating node, a bootstrap capacitor connected between a high side power source and the floating node, a high voltage driver to provide a first control signal to control the high side switch, a low voltage driver providing a second control signal to control the low side switch, and a level shift circuit to shift the level of a low voltage logic signal to generate the first control signal. The high voltage device has an input terminal, an output terminal, and a control terminal, and the input terminal and the control terminal are connected to the level shift circuit. The input terminal of the high voltage device receives a voltage related to the voltage at the floating node, and the ZVS generator detects the voltage at the output terminal of the high voltage device when turning on the high side switch or turning off the low side switch, for triggering a ZVS signal.

These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a half-bridge driver circuit;

FIG. 2 is a circuit diagram of a first embodiment according to the present invention;

FIG. 3 is a timing diagram of the half-bridge driver circuit shown in FIG. 1 using the high voltage offset detection circuit shown in FIG. 2 ;

FIG. 4 is a circuit diagram of a first embodiment for the ZVS generator shown in FIG. 2 ;

FIG. 5 is a circuit diagram of a second embodiment for the ZVS generator shown in FIG. 2 ;

FIG. 6 is a circuit diagram of a third embodiment for the ZVS generator shown in FIG. 2 ;

FIG. 7 is a circuit diagram of a second embodiment according to the present invention;

FIG. 8 is a circuit diagram of a third embodiment according to the present invention;

FIG. 9 is a circuit diagram of a fourth embodiment according to the present invention;

FIG. 10 is a circuit diagram of a fifth embodiment according to the present invention;

FIGS. 11A and 11B are waveform diagrams of the circuit shown in FIG. 10 ;

FIG. 12 is a circuit diagram of a sixth embodiment according to the present invention; and

FIG. 13 is a circuit diagram of a seventh embodiment according to the present invention.

FIG. 2 is a circuit diagram of a first embodiment according to the present invention, in which a high voltage offset detection circuit 16 includes an NMOS transistor M 3 , a programmable load element 30 , and a ZVS generator 32 . The NMOS transistor M 3 is a high voltage device, and has a control terminal G grounded, and thus the NMOS transistor M 3 remains off. The NMOS transistor M 3 has an input terminal D connected to the floating node 24 as shown in FIG. 1 , for detecting the voltage VS at the floating node 24 . When the voltage VS at the input terminal D varies, a parasitic capacitance C 2 existing between the input terminal D and an output terminal S of the NMOS transistor M 3 leads the voltage Vdet at the output terminal S to vary accordingly. Therefore, the voltage Vdet may be used to identify the state of the voltage VS at the floating node 24 . The NMOS transistor M 3 can detect the voltage VS no matter the high side switch M 1 is on or off. As shown in FIG. 1 , a bootstrap capacitor CB is connected between the high side power source VB and the floating node 24 , and thus, when the voltage VS at the floating node 24 changes instantly, the voltage VB changes accordingly. Thus, the NMOS transistor M 3 may monitor the voltage VS by detecting the high side power source VB. In this half-bridge driver circuit, the high side power source VB that the bootstrap capacitor CB is connected provides a high side voltage. When VS=0, a power source VCC charges the bootstrap capacitor CB through a diode D 1 , such that the voltage across the capacitor CB reaches VCC−VD 1 . In other embodiments, in addition to the voltages VS and VB, a voltage at any other terminal may be detected for generating the voltage Vdet, provided that the voltage at that terminal is related to the voltage VS. The ZVS generator 32 detects the voltage Vdet to generate a ZVS signal S 5 , and the half-bridge driver circuit identifies whether a hard switching occurs according to the ZVS signal S 5 . A programmable load element 30 is connected to the output terminal S of the NMOS transistor M 3 , and includes a current source 34 connected between the output terminal S of the NMOS transistor M 3 and a ground terminal GND, and a switch SW connected in parallel to the current source 34 . The load value of the programmable load element 30 can be changed by controlling the switch SW. When the switch SW is turned on by a signal S 2 , charges of the output terminal S will be released to the ground terminal GND.

Referring to FIG. 1 and FIG. 2 , during the high side switch M 1 is off and the low side switch M 2 is on, the inductor current IL flows to a ground terminal GND through the floating node 24 and the low side switch M 2 , and then, when the low side switch M 2 is turned off, as shown at time t 1 in FIG. 3 , the inductor current IL still flows to the floating node 24 , thereby boosting the voltage VS. At the same time, the parasitic capacitance C 2 couples the variation of the voltage VS to the output terminal S of the NMOS transistor M 3 , causing the voltage Vdet to increase. When the voltage Vdet reaches a predetermined threshold Vref 1 , the ZVS generator 32 triggers the ZVS signal S 5 . As shown at time t 2 in FIG. 3 , if the ZVS signal S 5 is triggered before the high side switch M 1 is turned on, there is no hard switching. On the contrary, if the ZVS signal S 5 is triggered after the high side switch M 1 is turned on, as shown at time t 3 in FIG. 3 , the half-bridge driver circuit has a hard switching. Likewise, when the high side switch M 1 changes from on to off, the voltages VS and Vdet start to decrease. When the voltage Vdet becomes lower than another predetermined threshold Vref 2 , the ZVS signal S 5 is triggered. If the ZVS signal S 5 is triggered before the low side switch M 2 is turned on, there is no hard switching. On the contrary, if the ZVS signal S 5 is triggered after the low side switch M 2 is turned on, the half-bridge driver circuit has a hard switching.

FIG. 4 is a circuit diagram of a first embodiment for the ZVS generator 32 shown in FIG. 2 , which includes a comparator 36 for comparing the voltage Vdet with the threshold Vref 1 , where the threshold Vref 1 is equal to the result of subtracting a preset voltage VP 1 from the power source voltage VCC provided to the low voltage driver 22 , i.e. Vref 1 =VCC−VP 1 . Thus, in this embodiment, the threshold Vref 1 is related to the power source voltage VCC. When the voltage Vdet rises beyond the threshold Vref 1 , the comparator 36 triggers the ZVS signal S 5 . FIG. 5 is a circuit diagram of a second embodiment for the ZVS generator 32 shown in FIG. 2 , which includes a comparator 36 and a logic circuit 38 . The comparator 36 compares the voltage Vdet with the threshold Vref 2 , where the threshold Vref 2 is equal to the result of subtracting a preset voltage VP 2 from the power source voltage VCC, i.e. Vref 2 =VCC−VP 2 , and thus the threshold Vref 2 is related to the power source voltage VCC. When the voltage Vdet decreases beyond the threshold Vref 2 , the comparator 36 triggers the comparison signal Sc. The logic circuit 38 includes an AND gate 40 that generates the ZVS signal S 5 according to the comparison signal Sc and an inverted signal UG′ of the control signal UG. In other embodiments, it is feasible to use the control signal LG to replace the inverted signal UG′. FIG. 6 is a circuit diagram of a third embodiment for the ZVS generator 32 shown in FIG. 2 . Similar to the circuit shown in FIG. 5 , it also includes a comparator 36 and a logic circuit 38 ; however, the logic circuit 38 includes a D-type flip-flop that generates the ZVS signal S 5 according to the comparison signal Sc and the inverted signal UG′.

The embodiment shown in FIG. 7 is designed by replacing the programmable load element 30 shown in FIG. 2 with a bias circuit 44 . The bias circuit 44 includes voltage sources V 1 , V 2 , and V 3 and a current source I 1 that are connected in series between the power source input terminal VCC and a ground terminal GND. The bias circuit 44 not only provides a bias voltage applied to the output terminal S of the NMOS transistor M 3 , but also provides the threshold Vref 1 or Vref 2 related to the power source voltage VCC for the ZVS generator 32 .

By replacing the bias circuit 44 shown in FIG. 7 with a plurality of resistors R 1 , R 2 , and R 3 connected in series, another embodiment is shown in FIG. 8 . The resistors R 1 , R 2 , and R 3 divide the power source voltage VCC to generate the bias voltage for the output terminal S of the NMOS transistor M 3 and the threshold Vref 1 or Vref 2 related to the power source voltage VCC for the ZVS generator 32 .

FIG. 9 is a circuit diagram of a fourth embodiment according to the present invention, in which a high voltage offset detection circuit 16 includes a capacitor Cr having a first terminal 46 for detecting the voltage VS or VB, a programmable load element 30 or a bias circuit 44 connected to a second terminal 48 of the capacitor Cr, and a ZVS generator 32 for detecting the voltage Vdet at the second terminal of the capacitor Cr to trigger a ZVS signal S 5 . When the voltage VS or VB changes instantly, the voltage Vdet at the second terminal of the capacitor Cr changes accordingly. Thus, the voltage VS at the floating node 24 can be identified from the voltage Vdet.

By replacing the capacitor Cr shown in FIG. 9 with an NMOS transistor M 3 , an embodiment is shown in FIG. 10 . The NMOS transistor M 3 has an input terminal D to receive the voltage VS or VB, the programmable load element 30 or the bias circuit 44 is connected to an output terminal S of the NMOS transistor M 3 , and the ZVS generator 32 detects the voltage Vdet at the output terminal S of the NMOS transistor for triggering a ZVS signal S 5 . FIG. 11 is a waveform diagram of the circuit shown in FIG. 10 . The NMOS transistor M 3 has a gate G to receive the power source voltage VCC, to thereby remain the NMOS transistor M 3 on. Thus, when the high side switch M 1 shown in FIG. 1 is off and the low side switch M 2 is on, the voltage Vdet at the output terminal S of the NMOS transistor M 3 is VCC−V THNM3 , where V THNM3 is the threshold voltage of the NMOS transistor M 3 . During the low side switch M 2 is off and the high side switch M 1 has not been turned on yet, the voltage VS or VB rises, thereby pushing the voltage Vdet to rise. If the high side switch M 1 has not been turned on yet when the voltage Vdet reaches the threshold Vref 1 , there is no hard switching, as shown in FIG. 11A . On the other hand, if the voltage Vdet reaches the threshold Vref 1 after the high side switch M 1 is turned on, a hard switching occurs, as shown in FIG. 11B .

FIG. 12 is a circuit diagram of a sixth embodiment according to the present invention. In this high voltage offset detection circuit 16 , an NMOS transistor M 3 has an input terminal D to receive the voltage VS or VB, a programmable load element 30 or a bias circuit 44 is connected to an output terminal S of the NMOS transistor M 3 , a ZVS generator 32 detects the voltage Vdet at the output terminal S of the NMOS transistor NMOS when the transistor M 3 is off, for triggering a ZVS signal S 5 , a controller 50 provides a control signal Soff to a control terminal G of the NMOS transistor M 3 to selectively turn off the NMOS transistor M 3 . As described previously, when the NMOS transistor M 3 is off, the parasitic capacitance C 2 makes the voltage Vdet vary with the voltage VS or VB at the input terminal D. Thus, the voltage Vdet is useful to identify the voltage VS at the floating node 24 .

FIG. 13 is a circuit diagram of a seventh embodiment according to the present invention. In the high voltage offset detection circuit 16 , an input terminal D of an NMOS transistor M 3 is connected to a drain VB 1 of an NMOS transistor M 4 in a level shift circuit 12 , a control terminal G of the NMOS transistor M 3 is connected to a gate of the NMOS transistor M 4 , a programmable load element 30 or a bias circuit 44 is connected to an output terminal S of the NMOS transistor M 3 , a ZVS generator 32 detects a voltage Vdet at the output terminal S of the NMOS transistor M 3 when the NMOS transistor M 3 is off, for triggering a ZVS signal S 5 . During the NMOS transistors M 3 and M 4 are turned off by the signal S 1 _reset of the low side circuit 10 , the drain voltage VB 1 of the NMOS transistor M 4 is related to the voltage VB, so any instant change of the voltage VS can make the voltage VB 1 vary accordingly. The parasitic capacitance C 2 of the NMOS transistor M 3 makes the voltage Vdet at the output terminal S of the NMOS transistor M 3 vary with the voltage VB 1 at the input terminal D of the NMOS transistor M 3 , so the voltage VS at the floating node 24 can be derived from the voltage Vdet. The NMOS transistor M 3 may be realized with a part of the structure of the NMOS transistor M 4 , to minimize the integrated circuit in area. The operations and principles of the level shift circuit 12 are known in the art and need no to be described at length herein. In other embodiments, the input terminal D and the control terminal G of the NMOS transistor M 3 may be alternatively connected to the drain and gate of an NMOS transistor M 5 in the level shift circuit 12 , and in this case, the NMOS transistor M 3 may be realized with a part of the structure of the NMOS transistor M 5 .

While the above embodiments illustrate the present invention in a half-bridge driver circuit, it is appreciated that the present invention is also applicable to a full-bridge driver circuit.

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.