Circuit arrangement for a data processing system and method for data processing

This application is a 35 U.S.C. §371 National Stage Application of PCT/EP2011/054109, filed on Mar. 18, 2011, which claims the benefit of priority to Ser. No. EP 10158595.8, filed on Mar. 31, 2010 in Europe, the disclosures of which are incorporated herein by reference in their entirety.

For the support of a processing unit, for example of a CPU (Central Processing Unit), for time and position related processes, timers are well known. Such timer units can be arranged as single components or as peripheral devices of the processing unit. They can provide more or less important functions for signal receiving and generation in time dependence of one or several clocks.

Known timer modules are either hardware implementations which have to be operated and configured by a processing unit and are characterized by a high interrupt load of the processing unit, or they are partly programmable and have a small microcontroller implemented which, while reducing the interrupt load of the external processing unit, is limited by its own interrupt load.

Examples for known timers or timer units are the General Purpose Timer Array (GPTA) of Infineon, the Advanced Timer Unit (ATU) from Renesas, the Time Processing Unit (TPU) from Freescale, and the High-End Timer (HET) from Texas Instruments.

Here, a circuit arrangement and a corresponding method are disclosed.

The circuit arrangement can for example be implemented in a data processing architecture, reducing an interrupt load of a data processing unit (CPU, ATU) of the data processing system.

In one embodiment, the circuit arrangement for a data processing system is arranged in several modules. Some of the modules are provided with a clock, a time base or a base of a further physical quantity. The circuit arrangement comprises a routing unit, connected to modules of the circuit arrangement. Via the circuit arrangement, modules periodically exchange data based on the time base or a base of a further physical quantity. Modules are configured to process data individually and in parallel to other modules. The periodical data exchange takes place after a given cycle time or a maximal cycle time.

The circuit arrangement is configured to process different tasks in parallel by the different modules individually and independently from each other. The modules are individually triggered by time or position related events. A high number of tasks are handled and processed in a short time. The modular structure is further configured to shut down a module individually if this module is not needed, e.g. to save energy or reduce temperature.

The central routing unit makes it possible to connect the multiple modules flexibly and configurably. In addition the routing unit uses a new interrupt concept for a timer module with its concept of request handling. Both the timer module and the routing unit lead to a very efficient timer module concept concerning its size, cost and energy consumption. FIG. 1 shows an exemplary circuit arrangement for the modular timer concept.

Further advantages of the disclosed timer (circuit arrangement) can be found in the following description.

In the following, an embodiment of a Timer Module will be described, the Generic Timer Module (GTM). It contains a module framework with sub modules of different functionality. These sub modules can be combined in a configurable manner to form a complex timer module that serves different application domains and different classes within one application domain. Because of this scalability and configurability the timer is called generic.

The scalability and configurability is reached with an architecture philosophy where dedicated hardware sub modules are located around a central routing unit (called Advanced Routing Unit (ARU)). The ARU can connect the sub modules in a flexible manner. The connectivity is software programmable and can be configured during runtime.

Nevertheless, the GTM-IP is designed to unload the CPU or a peripheral core from a high interrupt load. Most of the tasks inside the GTM-IP can run—once setup by an external CPU—independent and in parallel to the software. There may be special situations, where the CPU has to take action but the goal of the GTM design was to reduce these situations to a minimum.

The hardware sub modules have dedicated functionalities, e.g. there are timer input modules where incoming signals can be captured and characterized together with a notion of time. By combination of several sub modules through the ARU complex functions can be established. E.g. the signals characterized at an input module can be routed to a signal processing unit where an intermediate value about the incoming signal frequency can be calculated.

The modules that help to implement such complex functions are called infrastructural components further on. These components are present in all GTM variants. However, the number of these components may vary from device to device. Other sub modules have a more general architecture and can fulfil typical timer functions, e.g. there are PWM generation units. The third class of sub modules are those fulfilling a dedicated functionality for a certain application domain, e.g. the DPLL serves engine management applications. A fourth group of sub modules is responsible for supporting the implementation of safety functions to fulfil a defined safety level. Each GTM-IP is build up therefore with sub modules coming from those four groups. The application class is defined by the amount of components of those sub modules integrated into the implemented GTM-IP.

The structure of this document is motivated out of the aforementioned sub module classes. Chapter 0 describes the dedicated GTM-IP embodiment. It gives an overview about the implemented sub modules and their number within these dedicated devices.

The following chapters 0 up to 0 deal with the so called infrastructural components for routing, clock management and common time base functions. Chapters 0 to 0 describe the signal input and output modules while the following chapter 0 explains the signal processing and generation sub module. Chapter 0 outlines a memory configuration module for the described signal processing and generation sub module. The next sections provide a detailed description of application specific and safety related modules like the MAP, DPLL, SPE, CMP and MON sub modules. Chapter 0 describes a module that bundles several interrupts coming from the other sub modules and connect them to the outside world.

These sub module groups are shown in the following table:

Chapter Sub module Group  3 Advanced Routing Unit (ARU) Infrastructural components  4 Broadcast Module (BRC) Infrastructural components  5 First In First Out Module (FIFO) Infrastructural components  6 AEI-to-FIFO Data Interface (AFD) Infrastructural components  7 FIFO-to-ARU Interface (F2A) Infrastructural components  8 Clock Management Unit (CMU) Infrastructural components  9 Time Base Unit (TBU) Infrastructural components 10 Timer Input Module (TIM) IO Modules 11 Timer Output Module (TOM) IO Modules 12 ARU-connected Timer Output IO Modules Module (ATOM) 13 Multi Channel Sequencer (MCS) Signal generation and processing 14 Memory Configuration Module Infrastructural component (MCFG) for MCS 15 TIM0 Input Mapping Module Dedicated (MAP) 16 Digital PLL (DPLL) Dedicated 17 Interrupt Concentrator Module Interrupt services (ICM) 18 Sensor Pattern Evaluation Module BLDC support (SPE) 19 Output Compare Unit (CMP) Safety features 20 Monitoring Unit (MON) Safety features

Conventions

The following conventions are used within this document.

ARIAL BOLD CAPITALS Names of register and register bits Arial italic Names of signals Courier Extracts of files

Terms and Abbreviations

This document uses the following terms and abbreviations.

Term Meaning GTM Generic Timer Module IRC Interrupt Controller DPLL Digital Phase Locked Loop FULL_SCALE Range in which all positions/values depend on the information of TRIGGER and STATE signals HALF_SCALE Range in which all positions/values depend on the information of TRIGGER signal only; two consecutive HALF_SCALE periods form a FULL_SCALE period TS Time stamp representation PS Position (or value) stamp representation; common description [i] Numbering of Instances of a module (e.g. ATOM[i] references to instance i of module ATOM)

GTM Architecture

Overview

The GTM-IP forms a generic timer platform that serves different application domains and different classes within these application domains. In this section the GTM-IP_103 realization is outlined. The architecture of the GTM-IP_103 is depicted in FIG. 1 . Please note, that the size of the sub modules in the figure does not reflect the die size of the modules in the final RTL implementation.

GTM Architecture Block Diagram

See FIG. 1 .

The central component of the GTM-IP is the Advanced Routing Unit (ARU) where most of the sub modules are located around and connected to. This ARU forms together with the Broadcast (BRC) and the Parameter Storage Module (PSM) the infrastructural part of the GTM. The ARU is able to route data from a connected source sub module to a connected destination sub module. The routing is done in a deterministic manner with a round-robin scheduling scheme of connected channels which receive data from ARU and with a worst case round-trip time.

The routed data word size of the ARU is 53 bit. The data word can logically be split into three parts. These parts are shown in FIG. 1 . Bits 0 to 23 and bits 24 to 47 typically hold data for the operation registers of the GTM-IP. This can be for example the duty cycle and period duration of a measured PWM input signal or the output characteristic of an output PWM to be generated. Another possible content of Data 0 and Data 1 can be two 24 bit values of the GTM-IP time bases TBU_TS 0 , TBU_TS 1 and TBU_TS 2 . Bits 48 to 52 can contain control bits to send control information from one sub module to another. These ARU Control Bits (ACB) can have a different meaning for different sub modules.

It is also possible to route data from a source to a destination and the destination can act later on as source for another destination. These routes through the GTM-IP are further on called data streams. For a detailed description of the ARU sub module please refer to chapter 0 .

ARU Data Word Description

The BRC is able to distribute data from one source module to more than one destination modules connected to the ARU. The PSM sub module consists of three subunits, the AEI-to-FIFO Data Interface (AFD), FIFO-to-ARU Interface (F2A) and the FIFO itself. The PSM can serve as a data storage for incoming data characteristics or as parameter storage for outgoing data. This data is stored in a RAM that is logically located inside the FIFO subunit, but physically the RAM is implemented and integrated by the silicon vendor with his RAM implementation technology. Therefore, the GTM-IP provides the interface to the RAM at its module boundary. The AFD subunit is the interface between the FIFO and the GTM SoC system bus interface AEI (please see section 0 for detailed discussion). The F2A subunit is the interface between the FIFO subunit and the ARU.

Signals are transferred into the GTM-IP at the Timer Input Modules (TIM). These modules are able to filter the input signals and annotate additional information. Each channel is for example able to measure pulse high or low times and the period of a PWM signal in parallel and route the values to ARU for further processing. The internal operation registers of the TIM sub module are 24 bits wide.

The Clock Management Unit (CMU) serves up to 13 different clocks for the GTM and up to three external clock pins GTM_ECLK 0 . . . 2 . It acts as a clock divider for the system clock. The counters implemented inside other sub modules are typically driven from this sub module. Please note, that the CMU clocks are implemented as enable signals for the counters while the whole system runs with the GTM global clock SYS_CLK. This global clock typically corresponds to the microcontroller bus clock the GTM-IP is connected to and should not exceed 100 MHz because of the power dissipation of the used transistors where the GTM is implemented with.

The TBU provides three independent common time bases for the GTM-IP_103. In general, the number of time bases depends on the implemented device. If three time bases are implemented, two of these time bases can also be clocked with the digital PLL (DPLL) sub_inc 1 c and sub_inc 2 c outputs. The DPLL generates the higher frequent clock signals sub_inc 1 , sub_inc 2 , sub_inc 1 c and sub_inc 2 c on behalf of the frequencies of up to two input signals. These two input signals can be selected out of six incoming signals from the TIM 0 sub module. In this sub module the incoming signals are filtered and transferred to the MAP sub module where two of these six signals are selected for further processing inside the DPLL.

Signal outputs are generated with the Timer Output Modules (TOM) and the ARU-connected TOMs (ATOM). Each TOM channel is able to generate a PWM signal at its output. Because of the integrated shadow register even the generation of complex PWM outputs is possible with the TOM channels by serving the parameters with the CPU. In addition each TOM sub module can integrate functions to drive one BLDC engine. This BLDC support is established together with the TIM and Sensor Pattern Evaluation (SPE) sub module.

The ATOMs offer the additional functionality to generate complex output signals without CPU interaction by serving these complex waveform characteristics by other sub modules that are connected to the ARU like the PSM or Multi Channel Sequencer (MCS). While the internal operation and shadow registers of the TOM channels are 16 bit wide, the operation and shadow registers of the ATOM channels are 24 bit wide to have a higher resolution and to have the opportunity to compare against time base values coming from the TBU.

Together with the MCS the ATOM is able to generate an arbitrary predefined output sequence at the GTM-IP output pins. The output sequence is defined by instructions located in RAM connected to the MCS sub module. The instructions define the points were an output signal should change or to react on other signal inputs. The output points can be one or two time stamps (or even angle stamp in case of an engine management system) provided by the TBU. Since the MCS is able to read data from the ARU it is also able to operate on incoming data routed from the TIM. Additionally, the MCS can process data that is located in its connected RAMs. Like in the PSM the MCS RAM is located logically inside the MCS while the silicon vendor has to implement its own RAM technology there.

The two modules Compare Module (CMP) and Monitor Module (MON) implement safety related features. The CMP compares two output channels of an ATOM or TOM and sends the result to the MON sub module were the error is signalled to the CPU. The MON module is also able to monitor the ARU and CMU activities.

In the described implementation the sub modules of the GTM-IP have about 1000 different interrupt sources. These 1000 interrupt sources are grouped and concentrated by the Interrupt Concentrator Module (ICM) to form approx. 100 interrupts that are visible outside of the GTM-IP.

GTM-IP Interfaces

In general the GTM-IP can be divided into four interface groups. Two interface groups represent the ports of the GTM-IP where incoming signals are assembled and outgoing signals are created. These interfaces are therefore connected to the GTM-IP input sub module TIM and to the GTM-IP output sub modules TOM and ATOM. Another interface is the bus interface where the GTM-IP can be connected to the SoC system bus. This generic bus interface is described in more detail in section 0 . The last interface is the interrupt controller interface. The GTM-IP provides several interrupt lines coming from the various sub modules. These interrupt lines are concentrated inside the ICM and have to be adapted to the dedicated microcontroller environment where each interrupt handling can look different. The interrupt concept is described in more detail in section 0 .

GTM-IP Generic Bus Interface (AEI)

The GTM-IP is equipped with a generic bus interface that can be widely adapted to different SoC bus systems. This generic bus interface is called AE-Interface (AEI). The adaptation of the AEI to SoC buses is typically done with a bridge module translating the AEI signals to the SoC bus signals of the silicon vendor. The AEI bus signals are depicted in the following table:

Signal name I/O Description Bit width AEI_SEL I GTM-IP select line 1 AEI_ADDR I GTM-IP address 32 AEI_PIPE I AEI Address phase signal 1 AEI_W1R0 I Read/Write access 1 AEI_WDATA I Write data bus 32 AEI_RDATA O Read data bus 32 AEI_READY O Data ready signal 1 AEI_STATUS O AEI Access status 2

GTM-IP Multi-Master and Multi-Tasking Support

To support multi-master and multi-task access to the registers of the GTM-IP a dedicated write-access scheme is used for critical control bits inside the IP that need such a mechanism. This can be for example a shared register where more than one channel can be controlled globally by one register write access. Such register bits are implemented inside the GTM-IP with a double bit mechanism, where the writing of ‘00’ and ‘11’ has no effect on the register bit and where ‘01’ sets the bit and ‘10’ resets the bit. If the CPU wants to read the status of the bit it always gets a ‘00’ if the bit is reset and it gets a ‘11’ if the bit is set.

ARU Routing Concept

One central concept of the GTM-IP is the routing mechanism of the ARU sub module for data streams. Each data word transferred between the ARU and its connected sub module is 53 bit wide. It is important to understand this concept in order to use the resources of the GTM-IP effectively. Each module that is connected to the ARU may provide an arbitrary number of ARU write channels and an arbitrary number of ARU read channels. In the following, the ARU write channels are named data sources and the ARU read channels are named data destinations.

The concept of the ARU intends to provide a flexible and resource efficient way for connecting any data source to an arbitrary data destination. In order to save resource costs, the ARU does not implement a switch matrix, but it implements a data router with serialized connectivity providing the same interconnection flexibility. FIG. 2 shows the ARU data routing principle. Data sources are marked with underlined numbers in the rectangles and the data destinations are marked with not-underlined numbers in the rectangles. The dashed lines in the ARU depict the configurable connections between data sources and data destinations. A connection between a data source and a data destination is also called a data stream.

Principle of Data Routing Using ARU

See FIG. 2 .

The configuration of the data streams is realized according to the following manner: Each data source has its fixed and unique source address: The fixed address of each data source is pointed out by the underlined numbers in the boxes of FIG. 2 . The address definitions of all available data sources in the GTM-IP can be obtained from the table. The connection from a specific data source to a specific data destination is defined by configuring the corresponding address of a data source in the desired data destination. The configured address of each data destination is pointed out by the not-underlined numbers in the boxes of FIG. 2 .

Normally, the destination is idle and waits for data from the source. If the source offers new data, the destination does a destructive read, processes the data and goes idle again. The same data is never read twice.

There is one sub module for which this destructive read access does not hold. This is the BRC sub module configured in Maximal Throughput Mode. For a detailed description of this module please refer to chapter 0 .

The functionality of the ARU is as follows: The ARU sequentially polls the data destinations of the connected modules in a round-robin order. If a data destination requests new data from its configured data source and the data source has data available, the ARU delivers the data to the destination and it informs both, the data source and destination that the data is transferred. The data source marks the delivered ARU data as invalid which means that the destination consumed the data. It should be noted that each data source should only be connected to a single data destination. This is because the destinations consume the data. If two destinations would reference the same source one destination would consume the data before the other destination could consume it. Since the data transfers are blocking, the second destination would block until it receives new data from the source. If a data source should be connected to more than one data destination the sub module Broadcast (BRC) has to be used. On the other hand, the transfer from a data source to the ARU is also blocking, which means that the source channel can only provide new data to the ARU when an old data word is consumed by a destination. In order to speed up the process of data transfers, the ARU handles two different data destinations in parallel. Therefore, a transfer between source and destination takes two cycles, but since the transfers are pipelined these two cycles have only effect for one round trip of the ARU.

Following table gives an overview about the number of channels for the GTM-IP_103 variant described within this document.

Number of data Number of data Sub module sources destinations ARU 1 0 DPLL 24 24 TIM 0-3 32 0 MCS 0-3 72 72 BRC 22 12 TOM 0 0 ATOM 0-4 40 40 PSM 0 8 8 CMP 0 0 MON 0 0 Total 199 156

ARU Round Trip Time

The ARU uses a round-robin arbitration scheme with a fixed round trip time for all connected data destinations. This means that the time between two adjacent read requests resulting from a data destination channel always takes the round trip time, independently if the read request succeeds or fails.

The worst case round-trip time is defined as 2 us at 40 MHz of the GTM-IP input system clock SYS_CLK. Since the round-trip time depends on the number of destinations the ARU has to ensure that the round-trip time never exceeds the 2 us at a clock speed equal or higher than 40 MHz.

ARU Blocking Mechanism

Another important concept of the ARU is its blocking mechanism that is implemented for transferring data from a data source to a data destination. This mechanism is used by ARU connected sub modules to synchronize the sub modules to the routed data streams. FIG. 3 explains the blocking mechanism.

Graphical Representation of ARU Blocking Mechanism

See FIG. 3 .

If a data destination requests data from a data source over the ARU but the data source does not have any data yet, it has to wait until the data source provides new data. In this case the sub module that owns the data destination may perform other tasks. When a data source produces new data faster than a data destination can consume the data the source raises an error interrupt and signals that the data could not be delivered in time. The new data is marked as valid for further transfers and the old data is overwritten.

In any case, if sources and destinations block or not, the round trip time for the ARU is always fixed.

One exception is the BRC sub module when configured in Maximal Throughput Mode. Please refer to chapter 0 for a detailed description.

GTM-IP Clock and Time Base Management (CTBM)

Inside the GTM-IP several subunits are involved in the clock and time base management of the whole GTM. FIG. 4 shows the connections and sub blocks involved in these tasks. The sub blocks involved are called Clock and Time Base Management (CTBM) modules further on.

GTM-IP Clock and Time Base Management Architecture

See FIG. 4 .

One important module of the CTBM is the Clock Management Unit (CMU) which generates 13 clocks for the sub modules of the GTM and up to three GTM external clocks CMU_ECLK[z] (z: 0.2). For a detailed description of the CMU functionality and clocks please refer to Chapter 0 .

The five (5) CMU_FXCLK[y] (y: 0 . . . 4) clocks are used by the TOM sub module for PWM generation. The eight (8) CMU_CLK[x] (x: 0 . . . 7) clocks are used by other sub modules of the GTM for signal generation.

Inside the Time Base Unit (TBU) one of these eight clocks is used per channel to generate a common time base for the GTM. Besides the CMU_CLK[x] signals, the TBU can use the compensated SUB_INC[i]c (i: 1,2) signals coming from the DPLL sub module for time base generation. This time base then typically represents an angle clock for an engine management system. For the meaning of compensated (SUB_INC[i]c) and uncompensated (SUB_INC[i]) DPLL signals please refer to the DPLL chapter 0 . The SUB_INC[i]c signals in combination with the two direction signal lines DIR[i] the TBU time base can be controlled to run forwards or backwards. The TBU functionality is described in Chapter 0 .

In this device the TBU sub module generates the three time base signals TBU_TS 0 , TBU_TS 1 and TBU_TS 2 which are widely used inside the GTM as common time bases for signal characterization and generation.

As stated before, the DPLL sub module provides the four clock signals SUB_INC[i] and SUB_INC[i]c which can be seen as a clock multiplier generated out of the two input signal vectors TRIGGER and STATE coming from the MAP sub module. For a detailed description of the DPLL functionality please refer to chapter 0 .

The MAP sub module is used to select the TRIGGER and STATE signals for the DPLL out of six input signals coming from TIM 0 sub module. Besides this, the MAP sub module is able to generate a TDIR (TRIGGER Direction) and SDIR (STATE Direction) signal for the DPLL and TBU coming from the SPE 0 and SPE 1 signal lines. The direction signals are generated out of a defined input pattern. For a detailed description of the MAP sub module please refer to section 0 .

GTM-IP Interrupt Concept

The sub modules of the GTM-IP can generate thousands of interrupts on behalf of internal events. This high amount of interrupt lines is combined inside the Interrupt Concentrator Module (ICM) into interrupt groups. In this interrupt groups the GTM-IP sub module interrupt signals are bundled to a smaller set of interrupts. Out of these interrupt sets a smaller amount of interrupt lines is created and signalled outside of the GTM-IP.

The enabling, disabling and detailed identification of the interrupt source is done inside the sub modules and their channels. If a sub module consists of several channels that are most likely to work independent from each other each channel has its own interrupt control register set. The GTM-IP interrupt concept is shown in FIG. 5 .

The interrupt control register set consists of four registers. One register, IRQ_EN, is used for enabling and disabling each individual interrupt and a second register, IRQ_NOTIFY, is for interrupt source identification purposes. There, each interrupt line has a dedicated bit, which is set when the interrupt was raised. The third register FORCINT inside each sub module channel can be used to trigger an interrupt by software. This trigger is or-combined with the hardware interrupt event and is visible also inside the IRQ_NOTIFY register bit. The last register, IRQ_MODE, determines the interrupt signal output characteristic and GTM internal interrupt bit control.

In any case, the interrupt has to be enabled if the interrupt should be visible outside of the GTM. Thus, the IRQ_NOTIFY register bit can be used by the software to poll for the interrupt request. Interrupt request bits written to FORCINT always result in a setting of the corresponding IRQ_NOTIFY bit and are reset by the hardware immediately after IRQ_NOTIFY is set. Therefore, a read to register FORCINT always results in reading a ‘0’.

The interrupt bit inside the IRQ_NOTIFY register is set as long as the Clear line (see FIG. 5 ) is not raised. This can be done by writing explicitly a ‘1’ to the IRQ_NOTIFY register bit. Thus, the interrupt bit is not altered especially when a software debugger reads the register for debugging purposes. In the case of a simultaneous clear and interrupt event from the channel hardware the channel hardware interrupt will be dominant.

The behaviour of notify clear is shown in the following table:

To support a wide variety of microcontroller architectures and interrupt systems the GTM-IP offers a configurable interrupt signal output characteristic and internal interrupt bit handling specified by the IRQ_MODE register on a per channel basis. These four interrupt modes are:

Level mode Pulse mode Pulse-Notify mode Single-Pulse mode

These interrupt modes are described in more details in the following sections:

Level Interrupt Mode

The default interrupt generation mode is the Level Interrupt Mode. In this mode a channel interrupt sets the output high if the interrupt is enabled and the hardware interrupt or a force event occurred. The interrupt generation mechanism is shown in FIG. 5 .

Level Interrupt Mode Scheme

See FIG. 5 .

As it can be seen from the figure the interrupt once raised by the hardware or the IRQ_FORCINT register is held until the IRQ_NOTIFY register is cleared by an explicit write access from the CPU or an internal hardware signal. The internal clearing mechanism is described later on. The IRQ_occurred line is used for the STATUS flag of the ICM.

Pulse Interrupt Mode

In Pulse Interrupt Mode each occurrence of an interrupt event will generate a pulse on the IRQ_bit signal line if IRQ_EN is enabled. The Pulse interrupt mode behaviour can be seen from FIG. 6 .

Pulse Interrupt Mode Scheme

See FIG. 6 .

As it can be seen from the figure, IRQ_NOTIFY register is always cleared if IRQ_EN is enabled. The IRQ_occurred signal line will be permanently low in this mode.

Pulse-Notify Interrupt Mode

In Pulse-notify Interrupt mode, the active interrupt sources are registered in the IRQ_NOTIFY register. Each occurrence of an interrupt event will generate a pulse on the IRQ_bit signal line, when the IRQ_EN register is enabled. The IRQ_occurred will be high if interrupt IRQ_EN is high a the IRQ_NOTIFY register bit is set. The Pulse-notify interrupt mode is shown in FIG. 7 .

Pulse-notify Interrupt Mode Scheme

See FIG. 7 .

Single-pulse Interrupt Mode

In Single-pulse Interrupt Mode, additional pulses triggered by interrupt events of any interrupt source are suppressed. The active interrupt sources are registered in the corresponding IRQ_NOTIFY register bit. The IRQ_occurred signal line will be high, if the IRQ_EN and the IRQ_NOTIFY register bits are set. The Single-pulse interrupt mode is shown in FIG. 8 .

Single-pulse Interrupt Mode Scheme

See FIG. 8 .

GTM-IP Interrupt Concept with Hardware Clear

The GTM-IP supports HW_clear input lines (GTM_<MOD>_JRQ_CLR) to support a hardware internal clearing of the IRQ_NOTIFY bits. This input line can be used by the surrounding microcontroller system to:

from DMA controller as DMA_ACK from ADC as ADC_VALID from an GTM-external interrupt controller to do an atomic clear while entering an ISR routine

GTM-IP Interrupt Concentration Method

Because of the grouping of interrupts inside the ICM, it can be necessary for the software to access the ICM sub module first to determine the sub module channel that is responsible for an interrupt. A second access to the sub module channel interrupt registers is then necessary to identify the interrupt, serve it and to reset the interrupt flag afterwards. The interrupt flags are never reset by an access to the ICM.

GTM-IP Software Debugger Support

For software debugger support the GTM-IP comes with several features. E.g. status register bits must not be altered by a read access from a software debugger. To avoid this behaviour to reset a status register bit by software, the CPU has to write a ‘1’ explicitly to the register bit to reset its content.

Further on, some important states inside the GTM-IP sub module have to be signalled to the outside world, when reached and should for example trigger the software debugger to stop program execution. For this internal state signalling please refer to the GTM-IP module integration guide.

GTM-IP TOP-Level Configuration Registers Overview

GTM-IP TOP-level contains following configuration registers:

Details in Register name Description Section GTM_REV GTM-IP Version control register 0 GTM_RST GTM-IP Global reset register 0 GTM_CTRL GTM-IP Global control register 0 GTM_AEI_ADDR_XPT GTM-IP AEI Timeout exception 0 address register GTM_IRQ_NOTIFY GTM-IP Interrupt notification 0 register GTM_IRQ_EN GTM-IP Interrupt enable register 0 GTM_IRQ_FORCINT GTM-IP Software interrupt 0 generation register GTM_IRQ_MODE GTM-IP top level interrupts mode 0 selection. Please note that this mode selection is only valid for the three interrupts described in section 0

GTM-IP TOP-Level Configuration Registers Description

Advanced Routing Unit (ARU)

Overview

The Advanced Routing Unit (ARU) is a flexible infrastructure component for transferring 53 bit wide data (five control bits and two 24 bit values) between several sub modules of the GTM core in a configurable manner.

Since the concept of the ARU has already been described in section 0 , this section only describes additional ARU features that can be used by the software for configuring and debugging ARU related data streams.

Also the definition of ‘streams’ and ‘channels’ in the ARU context is done in section 0 .

Special Data Sources

Besides the addresses of the sub module related data sources as described in Table 0, the ARU provides two special data sources that can be used for the configuration of data streams. These data sources are defined as follows:

Address 0x1FF: Data source that provides always a 53 bit data word with zeros. A read access to this memory location will never block a requesting data destination.

Address 0x1FE: Data source that never provides a data word. A read access to this memory location will always block a requesting data destination. This is the reset value of the read registers inside the data destinations.

Address 0x000: This address is reserved and can be used to bring data through the ARU registers ARU_DATA_H and ARU_DATA_L into the system by writing the write address 0x000 into the ARU_ACCESS register. This means that software test data can be brought into the GTM-IP by the CPU.

Besides the data transfer between the connected sub modules, there are two possibilities to access ARU data via the AEI.

ARU Access Via AEI

Default ARU Access

The default ARU access incorporates the registers ARU_ACCESS, which is used for initiation of a read or write request and the registers ARU_DATA_H and ARU_DATA_L that provide the ARU data word to be transferred.

The status of a read or write transfer can be determined by polling specific bits in register ARU_ACCESS. Furthermore the acc_ack bit in the interrupt notify register is set after the read or write access is performed to avoid data loss e.g. on access cancelation.

A pending read or write request may also be cancelled by clearing the associated bit. In the case of a read request, the AEI access behaves as a read request initiated by a data destination of a module. The read request is served by the ARU immediately when no other destination has a pending read request. This means, that an AEI read access does not take part in the scheduling of the destination channels and that the time between two consecutive read accesses is not limited by the round trip time.

On the other hand, the AEI access has the lowest priority behind the ARU scheduler that serves the destination channels. Thus, in worst case, the read request is served after one round trip of the ARU, when all destination channels would request data at the same point in time.

In the case of the write request, the ARU provides the write data at the address defined by the ADDR bit field inside the ARU_ACCESS register.

To avoid data loss, the reserved ARU address 0x0 has to be used to bring data into the system. Otherwise, in case the address specified inside the ADDR bit field is defined for another sub module that acts as a source at the ARU data loss may occur and no deterministic behaviour is guaranteed.

This is because the regular source sub module is not aware that its address is used by the ARU itself to provide data to a destination.

It is guaranteed that the ARU write data is send to the destination in case of both modules want to provide data at the same time.

Configuring both read and write request bits results in a read request. Then the write request bit is cleared automatically.

Debug Access

The debug access mode enables to inspect routed data of configured data streams during runtime.

The ARU provides two independent debug channels, whereas each is configured by a dedicated ARU read address in register ARU_DBG_ACCESS 0 and ARU_DBG_ACCESS 1 respectively.

The registers ARU_DBG_DATA 0 _H and ARU_DBG_DATA 0 _L (ARU_DBG_DATA 1 _H and ARU_DBG_DAT 1 _L) provide read access to the latest data word that the corresponding data source sent through the ARU.

Any time when data is transferred through the ARU from a data source to the destination requesting the data the interrupt signal ARU_NEW_DATA 0 _IRQ (ARU_NEW_DATA 1 _IRQ) is raised.

For advanced debugging purposes, the interrupt signal can also be triggered by software using the register ARU_IRQ_FORCINT.

The debug mechanism should not be used by application, when the HW-Debugger is access the debug registers of the ARU.

ARU Interrupt Signals

The following table describes ARU interrupt signals:

Signal Description ARU_NEW_DATA0_IRQ Indicates that data is transferred through the ARU using debug channel ARU_DBG_ACCESS0. ARU_NEW_DATA1_IRQ Indicates that data is transferred through the ARU using debug channel ARU_DBG_ACCESS1. ACC_ACK_IRQ ARU access acknowledge IRQ.

ARU Configuration Registers Overview

The following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register name Description Section ARU_ACCESS ARU access register 0 ARU_DATA_H ARU access register upper data 0 word ARU_DATA_L ARU access register lower data 0 word ARU_DBG_ACCESS0 Debug access channel 0 0 ARU_DBG_DATA0_H Debug access 0 transfer 0 register upper data word ARU_DBG_DATA0_L Debug access 0 transfer 0 register lower data word ARU_DBG_ACCESS1 Debug access channel 0 0 ARU_DBG_DATA1_H Debug access 1 transfer 0 register upper data word ARU_DBG_DATA1_L Debug access 1 transfer 0 register lower data word ARU_IRQ_NOTIFY ARU Interrupt notification 0 register ARU_IRQ_EN ARU Interrupt enable register 0 ARU_IRQ_FORCINT Register for forcing the 0 ARU_NEW_DATA_IRQ interrupt ARU_IRQ_MODE IRQ mode configuration register 0

ARU Configuration Registers Description

Broadcast Module (BRC)

Overview

Since each write address for the sub module channels of the GTM-IP that are able to write to the ARU can only be read by a single module, it is impossible to provide a data stream to different modules in parallel (This statement holds not for sources, which do not invalidate their data after the data were read by any consumer, e.g. DPLL).

To overcome this issue for regular modules, the sub module Broadcast (BRC) enables to duplicate data streams multiple times.

The BRC sub module provides 12 input channels as well as 22 output channels. In order to clone an incoming data stream, the corresponding input channel can be mapped to zero or more output channels.

When mapped to zero no channel is read.

To destroy an incoming data stream, the EN_TRASHBIN bit inside the BRC_SRC_[x]_DEST register has to be set.

The total number of output channels that are assigned to a single input channel is variable. However, the total number of assigned output channels must be less than or equal to 22.

BRC Configuration

As it is the case with all other sub modules connected to the ARU, the input channels can read arbitrary ARU address locations and the output channels provide the broadcast data to fixed ARU write address locations.

The associated write addresses for the BRC sub module are fixed and can be obtained later on.

The read address for each input channel is defined by the corresponding register BRC_SRC_[x]_CTRL (x: 0 . . . 11).

The mapping of an input channel to several output channels is defined by setting the appropriate bits in the register BRC_SRC_[x]_DEST (x: 0 . . . 11). Each output channel is represented by a single bit in the register BRC_SRC_[x]_DEST. The address of the output channel is defined later on.

If no output channel bit is set within a register BRC_SRC_N_DEST, no data is provided to the corresponding ARU write address location from the defined read input specified by BRC_SRC_[x]_CTRL. This means that the channel does not broadcast any data and is disabled (reset state).

Besides the possibility of mapping an input channel to several output channels, the bit EN_TRASHBIN of register BRC_SRC_[x]_DEST may be set, which results in dropping an incoming data stream. In this case the data of an input channel defined by BRC_SRC_[x]_CTRL is consumed by the BRC module and not routed to any succeeding sub module. In consequence, the output channels defined in the register BRC_SRC_[x]_DEST are ignored.

In general, the BRC sub module can work in two independent operation modes. In the first operation mode the data consistency is guaranteed since a BRC channel requests only new data from a source when all destination channels for the BRC have consumed the old data value. This mode is called Data Consistency Mode (DCM).

In a second operation mode the BRC channel always requests data from a source and distributes this data to the destination regardless whether all destinations have already consumed the old data. This mode is called Maximum Throughput Mode (MTM).

MTM ensures, that always the newest available data is routed through the system, while it is not guaranteed data consistency since some of the destination channels can be provided with the old data while some other destination channels are provided with the new data. If this is the case, the Data Inconsistency Detected Interrupt BRC_DID_IRQ[x] is raised but the channel continues to work.

Furthermore in MTM mode it is guaranteed that it is not possible to read a data twice by a read channel. This is blocked.

The channel mode can be configured inside the BRC_SRC_[x]_CTRL register.

To avoid invalid configurations of the registers BRC_SRC_[x]_DEST, the BRC also implements a plausibility check for these configurations. If the software assigns an already used output channel to a second input channel, BRC performs an auto correction of the lastly configured register BRC_SRC_[x]_DEST and it triggers the interrupt BRC_DEST_ERR.

Consider the following example for clarification of the auto correction mechanism. Assume that the following configuration of the 22 lower significant bits for the registers BRC_SRC_[x]_DEST:

BRC_SRC_ 0 _DEST: 00 0000 0000 1000 1000 0000 (binary) BRC_SRC_ 1 _DEST: 00 0000 0000 0100 0000 0100 (binary) BRC_SRC_ 2 _DEST: 00 0000 0000 0001 0100 0010 (binary) BRC_SRC_ 3 _DEST: 00 0000 0000 0010 0001 1001 (binary)

If the software overwrites the value for register BRC_SRC_ 2 _DEST with

BRC_SRC_ 2 _DEST: 00 0000 0000 1 001 0 01 0 0010 (binary)

(changed bits are underlined), then the BRC releases a BRC_DEST_ERR interrupt since bit 11 is already assigned in register BRC_SRC_ 0 _DEST. The auto correction forces bit 11 to be cleared. The modifications of the bits 5 and 6 are accepted, since there is no violation with previous configurations. So the result of the write access mentioned above results in the following modified register configuration:

BRC_SRC_ 2 _DEST: 00 0000 0000 0001 0010 0010 (binary)

For debug purposes, the interrupt BRC_DEST_ERR can also be released by writing to register BRC_IRQ_FORCINT. Nevertheless, the interrupt has to be enabled to be visible outside of the GTM-IP.

BRC Interrupt Signals

Interrupt signals are defined in following table:

Signal Description BRC_DEST_ERR_IRQ Indicating configuration errors for BRC module BRC_DID_IRQ[x] Data inconsistency occurred in MTM mode (x: 0 . . . 11)

BRC Configuration Registers Overview

Following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register Name Description Section BRC_SRC_[x]_CTRL Read address for input 0 channel x (x: 0 . . . 11) BRC_SRC_[x]_DEST Destination channels for input 0 channel x (x: 0 . . . 11) BRC_IRQ_NOTIFY BRC Interrupt notification 0 register BRC_IRQ_EN BRC Interrupt enable register 0 BRC_IRQ_FORCINT Register for forcing the 0 BRC_DEST_ERR interrupt BRC_RST Software reset 0 BRC_IRQ_MODE IRQ mode configuration 0 register

BRC Configuration Registers Description

First In First Out Module (FIFO)

Overview

The FIFO unit is the storage part of the FIFO sub module. The F2A described in chapter 0 and the AFD described in chapter 0 implement the interface part of the FIFO sub module to the ARU and the AEI bus. Each FIFO unit embeds eight logical FIFOs. These logical FIFOs are configurable in the following manner:

FIFO size (defines start and end address) FIFO operation modes (normal mode or ring buffer operation mode) Fill level control/memory region read protection

Each logical FIFO represents a data stream between the sub modules of the GTM and the microcontroller connected to AFD sub module (see section 0 ). The FIFO RAM counts 1K words, where the word size is 29 bit. This gives the freedom to program or receive 24 bit of data together with the five control bits inside an ARU data word.

The FIFO unit provides three ports for accessing its content. One port is connected to the F2A interface, one port is connected to the AFD interface and one port has its own AEI bus interface.

The AFD interface has always the highest priority. Accesses to the FIFO from AFD interface and direct AEI interface in parallel—which means at the same time—is not possible, because both interfaces are driven from the same AEI bus interface of the GTM.

The priority between F2A and direct AEI interface can be defined by software. This can be done by using the register FIFO[i]_CH[x]_CTRL for all FIFO channels of the sub module.

The FIFO is organized as a single RAM that is also accessible through the FIFO AEI interface connected to one of the FIFO ports. To provide the direct RAM access, the RAM is mapped into the address space of the microcontroller.

After reset, the FIFO RAM is filled with zeros ( 0 ).

The FIFO channels can be flushed individually. Each of the eight FIFO channels can be used whether in normal FIFO operation mode or in ring buffer operation mode.

Operation Modes

Normal Operation Mode

In normal FIFO operation mode the content of the FIFO is written and read in first-in first-out order, where the data is destroyed after it is delivered to the system bus or the F2A sub module (see section 0 ).

The upper and lower watermark registers (registers FIFO[i]_CH[x]_UPPER_VM and FIFO[i]_CH[x]_LOWER_WM) are used for controlling the FIFO's fill level. If the fill level declines the lower watermark or it exceeds the upper watermark, an interrupt signal is triggered by the FIFO sub module if enabled inside the FIFO[i]_IRQ_EN.

The interrupt signals are sending to the Interrupt Concentrator Module (ICM) (see chapter 0 ). The ICM can also initiate specific DMA transfers.

Ring Buffer Operation Mode

The ring buffer mode is a powerful tool to provide a continuous data or configuration stream to the other GTM sub modules without CPU interaction. In ring buffer mode the FIFO provides a continuous data stream to the F2A sub module. The first word of the FIFO is delivered first and after the last word is provided by the FIFO to the ARU, the first word can be obtained again.

There could be the requirement that the user must be able to change some data inside the continuous data stream to the GTM sub modules or system bus. This is possible through direct memory access provided by the FIFO AEI interface.

FIFO Interrupt Signals

Interrupt signals are defined in following table:

Signal Description FIFO[i]_CH[x]_EMPTY Indicating empty FIFO x (x: 0 . . . 7) was reached FIFO[i]_CH[x]_FULL Indicating full FIFO x (x: 0 . . . 7) was reached FIFO[i]_CH[x]_LOWER_WM Indicating FIFO x (x: 0 . . . 7) reached lower watermark. FIFO[i]_CH[x]_UPPER_WM Indicating FIFO x (x: 0 . . . 7) reached upper watermark.

FIFO Configuration Registers Overview

The following table shows a conclusion of configuration registers address offsets and initial values:

Details in Register Name Description Section FIFO[i]_CH[x]_CTRL FIFO Channel x control 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_END_ADDR FIFO Channel x end address 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_START_ADDR FIFO Channel x start address 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_UPPER_WM FIFO Channel x upper 0 watermark register (x: 0 . . . 7) FIFO[i]_CH[x]_LOWER_WM FIFO Channel x lower 0 watermark register (x: 0 . . . 7) FIFO[i]_CH[x]_STATUS FIFO Channel x status register 0 (x: 0 . . . 7) FIFO[i]_CH[x]_FILL_LEVEL FIFO Channel x fill level 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_WR_PTR FIFO Channel x write pointer 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_RD_PTR FIFO Channel x read pointer 0 register (x: 0 . . . 7) FIFO[i]_CH[x]_IRQ_NOTIFY FIFO x interrupt notification 0 (x: 0 . . . 7) register FIFO[i]_CH[x]_IRQ_EN FIFO x interrupt enable 0 (x: 0 . . . 7) register FIFO[i]_CH[x]_IRQ_FORCINT FIFO x register to force 0 (x: 0 . . . 7) interrupt by software FIFO[i]_CH[x]_IRQ_MODE FIFO x IRQ mode control 0 (x: 0 . . . 7) register

FIFO Configuration Registers Description

AEI to FIFO Data Interface (AFD)

Overview

The AFD sub module implements a data interface between the AEI bus and the FIFO sub module, which consists of eight logical FIFO channels.

The AFD sub module provides a set of registers that are dedicated to the logical channels of the FIFO. These registers enable configuration of a channel (i.e. data direction) and the corresponding data transfer by reading or writing the registers AFD[i]_CH[x]_BUFF_ACC.

The AFD sub module does never block AEI accesses longer then 1 clock cycle.

AFD Register Overview

Following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register Name Description Section AFD[i]_CH[x]_BUFF_ACC AFD FIFO x buffer access 0 register (x: 0 . . . 7) AFD[i]_CH[x]_CTRL_STATUS AFD FIFO x control status 0 register (x: 0 . . . 7)

AFD Register Description

FIFO to ARU Unit (F2A)

Overview

The F2A is the interface between the ARU and the FIFO sub module. Since the data width of the ARU (ARU word) is 53 bit (two 24 bit values and five control bits) and the data width of the FIFO is only 29 bit, the F2A has to distribute the data from and to the FIFO channels in a configurable manner.

The data transfer between FIFO and ARU is organized with eight different streams that are connected to the eight different channels of the corresponding FIFO module. A stream represents a data flow from/to ARU to/from the FIFO via the F2A.

The general definition of ‘channels’ and ‘streams’ in the ARU context is done in section 0 .

Each FIFO channel can act as a write stream (data flow from FIFO to ARU) or as a read stream (data flow from ARU to FIFO).

Within these streams the F2A can transmit/receive the lower, the upper or both 24 bit values of the ARU together with the ARU control bits according to the configured transfer modes as described in section 0

Transfer Modes

The F2A unit provides several transfer modes to map 29 bit data of the FIFO from/to 53 bit data of the ARU. E.g. it is configurable that the 24 bit FIFO data is written to the lower ARU data entry (means bits 0 to 23 ) or to the higher 24 bit ARU data entry (means bits 24 to 47 ). Bits 24 to 28 of the FIFO data entry (the five control bits) are written/read in both cases to/from bits 48 to 52 of the ARU entry.

When both values of the ARU have to be stored in the FIFO the values are stored behind each other inside the FIFO if the FIFO is not full.

If there is only space for one 24 bit data word plus the five control bits, the F2A transfers one part of the 53 bits first and than waits for transferring the second part before new data is requested from the ARU.

When two values from the FIFO have to be written to one ARU location the words have to be located behind each other inside the FIFO.

The transfer to ARU is only established when both parts could be read out of the FIFO otherwise if only one 29 bit word was provided by the FIFO the F2A waits until the second part is available before the data is made available at the ARU.

FIG. 9 shows the data ordering of the FIFO when both ARU values must be transferred between ARU and FIFO.

When reading from the ARU the F2A first writes the lower word to the FIFO.

In case of writing to the ARU the F2A reads the lower word first from the FIFO, thus the lower word must be written first to the FIFO through the AFD interface.

Please note, that the five control bits (bits 48 to 52 of the ARU data word) are duplicated as bit 24 to 28 of both FIFO words in case of reading from ARU.

In the case of writing to the ARU, bits 24 to 28 of the last written FIFO word (the higher ARU word) are copied to bits 48 to 52 of the corresponding ARU location.

The transfer modes can be configured with the TMODE bits of registers F2A[i]_CH[x]_STR_CFG (x: 0 . . . 7).

Data Transfer of Both ARU Words Between ARU and FIFO

See FIG. 9 .

F2A Configuration Registers Overview

The following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register name Description Section F2A[i]_ENABLE F2A stream activation register 0 F2A[i]_CH[x]_ARU_RD_FIFO F2A read channel address 0 register (x: 0 . . . 7) F2A[i]_CH[x]_STR_CFG F2A stream x configuration 0 register (x: 0 . . . 7)

F2A Configuration Registers Description

Clock Management Unit (CMU)

Overview

The Clock Management Unit (CMU) is responsible for clock generation of the counters and of the GTM-IP. The CMU consists of three subunits that generate different clock sources for the whole GTM-IP. FIG. 10 shows a block diagram of the CMU.

The Configurable Clock Generation (CFGU) subunit provides eight dedicated clock sources for the following GTM sub modules: TIM, ATOM, TBU, and MON. Each instance of such a sub module can choose an arbitrary clock source, in order to specify wide-ranging time bases.

The Fixed Clock Generation (FXU) subunit generates predefined non-configurable clocks CMU_FXCLK[y] (y: 0 . . . 4) for the TOM sub modules and the MON sub module. The CMU_FXCLK[y] signals are derived from the CMU_GCLK_EN signal generated by the Global Clock Divider. The dividing factors are defined as 2 0 , 2 4 , 2 8 , 2 12 , and 2 16 .

The External Clock Generation (EGU) subunit is able to generate up to three chip external clock signals visible at CMU_ECLK[z] (z: 0 . . . 2) with a duty cycle of about 50%.

The clock source signals CMU_CLK[x] (x: 0 . . . 7) and CMU_FXCLK[y] are implemented in form of enable signals for the corresponding registers, which means that the actual clock signal of all registers always use the CMU_GCLK_EN signal.

The four configurable clock signals CMU_CLK 0 , CMU_CLK 1 , CMU_CLK 6 and CMU_CLK 7 are connected to the TIM filter counters.

CMU Block Diagram

See FIG. 10 .

Global Clock Divider

The sub block Global Clock Divider can be used to divide the GTM-IP global input clock signal SYS_CLK into a common subdivided clock signal.

The divided clock signal of the sub block Global Clock Divider is implemented as an enable signal that enables dedicated clocks from the SYS_CLK signal to generate the user specified divided clock frequency.

The resulting fractional divider (Z/N) specified through equation:

is implemented according the following algorithm

(Z: CMU_GCLK_NUM(23:0); N: CMU_GCLK_DEN(23:0); Z,N>0):

(1) Set remainder (R), operand 1 (OP 1 ) and operand 2 (OP 2 ) register during init-phase (with implicit conversion to signed): R=Z, OP 1 =N, OP 2 =N−Z; (2) After leaving init-phase (at least one CMU_CLK[x] has been enabled) the sign of remainder R for each SYS_CLK cycle will be checked: (3) If R>0 keep updating remainder and keep CMU_GCLK_EN=‘0’: R=R−OP 1 ; (4) If R<0 update remainder and set CMU_GCLK_EN=‘1’: R=R−OP 2 ;

After at most (Z/N+1) subtractions (3) there will be a negative R and an active phase of the generated clock enable (for one cycle) will be triggered (4). The remainder R is a measure for the distance to a real Z/N clock and will be regarded for the next generated clock enable cycle phase. The new R value will be R=R+(Z−N). In the worst case the remainder R will sum up to an additional cycle in the generated clock enable period after Z-cycles. In the other cases equally distributed additional cycles will be inserted for the generated clock enable. If Z is an integer multiple of N no additional cycles will be included for the generated clock enable at all.

Note that for a better resource sharing all arithmetic has been reduced to subtractions and the initialization of the remainder R uses the complement of (Z−N).

Configurable Clock Generation Subunit (CFGU)

The CMU subunit CFGU provides eight configurable clock divider blocks that divide the common CMU_GCLK_EN signal into dedicated enable signals for the GTM-IP sub blocks.

The configuration of the eight different clock signals CMU_CLK[x] (x: 0 . . . 7) always depends on the configuration of the global clock enable signal CMU_GCLK_EN. Additionally, each clock source has its own configuration data, provided by the control register CMU_CLK_[x]_CTRL (x: 0 . . . 7).

According to the configuration of the Global Clock Divider, the configuration of the Clock Source x Divider is done by setting an appropriate value in the bit field CLK_CNT[x] of the register CMU_CLK_[x]_CTRL.

The frequency f x =1/T x of the corresponding clock enable signal CMU_CLK[x] can be determined by the unsigned representation of CLK_CNT[x] of the register CMU_CLK_[x]_CTRL in the following way:

T CMU _ CLK[x] =(CLK_CNT[ x]+ 1)* T CMU _ GCLK _ EN

The corresponding wave form is shown in FIG. 11 .

Each clock signal CMU_CLK[x] can be enabled individually by setting the appropriate bit field EN_CLK[x] in the register CMU_CLK_EN. Except for CMU_CLK 6 and CMU_CLK 7 individual enabling and disabling is active only if CLK 6 _SEL and CLK 7 _SEL is unset.

Alternatively, clock source six and seven (CMU_CLK 6 and CMU_CLK 7 ) may provide the signal SUB_INC 1 and SUB_INC 2 coming from sub module DPLL as clock enable signal depending on the bit field CLK 6 _SEL of the register CMU_CLK_ 6 _CTRL and on the bit field CLK 7 _SEL of the register CMU_CLK_ 7 _CTRL.

To avoid unexpected behaviour of the hardware, the configuration of a register CMU_CLK_[x]_CTRL can only be changed, when the corresponding clock signal CMU_CLK[x] is disabled.

Further, any changes to the registers CMU_GCLK_NUM and CMU_GCLK_DEN can only be performed, when all clock enable signals CMU_CLK[x] and the EN_FXCLK bit inside the CMU_CLK_EN register are disabled.

The hardware guarantees that all clock signals CMU_CLK[x], which were enabled simultaneous, are synchronized to each other. Simultaneous enabling does mean that the bits EN_CLK[x] in the register CMU_CLK_EN are set by the same write access.

Wave Form of Generated Clock Signal CMU_CLK[x]

See FIG. 11 .

Fixed Clock Generation (FXU)

The FXU subunit generates fixed clock enables out of the CMU_GCLK_EN enable signal generated by the Global Clock Divider sub block. These clock enables are used for the PWM generation inside the TOM sub modules.

All clock enables CMU_FXCLK[y] can be enabled or disabled simultaneous by setting the appropriate bit field EN_FXCLK in the register CMU_CLK_EN.

The dividing factors are defined as 2 0 , 24, 2 8 , 2 12 , and 2 16 . The signals CMU_FXCLK[y] are implemented in form of enable signals for the corresponding registers (see also Chapter 0)

External Generation Unit (EGU)

The EGU subunit generate three separate clock output signals CMU_ECLK[z] (z: 0 . . . 2).

Each of these clock signals is derived from the corresponding External Clock Divider z sub block, which generates a clock signal derived from the GTM-IP input clock SYS_CLK.

In contrast to the signals CMU_CLK[x] and CMU_FXCLK[y], which are treated as simple enable signals for the registers, the signals CMU_ECLK[z] have a duty cycle of about 50% that is used as a true clock signal for external peripheral components. Each of the external clocks are enabled and disabled by setting the appropriate bit field EN_ECLK[z] in the register CMU_CLK_EN.

The clock frequencies f CMU _ ECLK[z] =1/T CMU _ ECLK[z] of the external clocks are controlled with the registers CMU_ECLK_[z]_NUM and CMU_ECLK_[z]_DEN as follows:

T CMU _ ECLK[z] =2*( E CLK[ z] _NUM/ E CLK[ z] _ DEN )* T SYS _ CLK

and is implemented according the following algorithm

(Z: CMU_ECLK_[z]_NUM(23:0); N: CMU_ECLK_[z]_DEN(23:0); Z,N>0; Z>=N; CMU_ECLK[z]=‘0’): (1) Set remainder (R), operand 1 (OP 1 ) and operand 2 (OP 2 ) register during init-phase (with implicit conversion to signed): R=Z, OP 1 =N, OP 2 =N−Z; (2) After leaving init-phase (CMU_ECLK[z] has been enabled) the sign of remainder R for each SYS_CLK cycle will be checked: (3) If R>0 keep updating remainder and keep CMU_ECLK[z]: R=R−OP 1 ; (4) If R<0 update remainder and toggle CMU_ECLK[z]: R=R−OP 2 ;

After at most (Z/N+1) subtractions (3) there will be a negative R and an active phase of the generated clock enable (for one cycle) will be triggered (4). The remainder R is a measure for the distance to a real Z/N clock and will be regarded for the next generated clock toggle phase. The new R value will be R=R+(Z−N). In the worst case the remainder R will sum up to an additional cycle in the generated clock toggle period after Z-cycles. In the other cases equally distributed additional cycles will be inserted for the generated clock toggle. If Z is an integer multiple of N no additional cycles will be included for the generated clock toggle at all.

Note that for a better resource sharing all arithmetic has been reduced to subtractions and the initialization of the remainder R uses the complement of (Z−N). The default value of the CMU_ECLK[z] output is low.

CMU Configuration Registers Overview

Following configuration registers are considered in CMU sub module:

Details in Register Name Description Section CMU_CLK _EN Clock enable 0 CMU_GCLK_NUM Global clock control numerator 0 CMU_GCLK_DEN Global clock control denominator 0 CMU_CLK_0_CTRL Control for clock source 0 0 CMU_CLK_1_CTRL Control for clock source 1 0 CMU_CLK_2_CTRL Control for clock source 2 0 CMU_CLK_3_CTRL Control for clock source 3 0 CMU_CLK_4_CTRL Control for clock source 4 0 CMU_CLK_5_CTRL Control for clock source 5 0 CMU_CLK_6_CTRL Control for clock source 6 0 CMU_CLK_7_CTRL Control for clock source 7 0 CMU_ECLK_0_NUM External clock 0 control numerator 0 CMU_ECLK_0_DEN External clock 0 control denominator 0 CMU_ECLK_1_NUM External clock 1 control numerator 0 CMU_ECLK_1_DEN External clock 1 control denominator 0 CMU_ECLK_2_NUM External clock 2 control numerator 0 CMU_ECLK_2_DEN External clock 2 control denominator 0

CMU Configuration Register Description

Time Base Unit (TBU)

Overview

The Time Base Unit TBU provides common time bases for the GTM-IP. The TBU sub module is organized in channels, where the number of channels is device dependent. There are at most three channels implemented inside the TBU. Each of these time base channels has a time base register TBU_CH[z]_BASE (z: 0 . . . 2) of 24 bit length.

The time base register value TBU_TS[z] and the time base register update event TBU_UP[z] are provided to subsequent sub modules of the GTM. The time base channels can run independently of each other and can be enabled and disabled synchronously by control bits in a global TBU channel enable register TBU_CHEN. Chapter 0 shows a block diagram of the Time Base Unit.

TBU Block Diagram

See FIG. 12 .

Dependent on the device a third TBU channel exists which offers the same functionality as the time base channel 1 .

The configuration of the independent time base channels TBU_BASE_[z] is done via the AEI interface. Each TBU channel may select one of the eight CMU_CLK[x] (x: 0 . . . 7) signals coming from the CMU sub module.

For TBU channels 1 and 2 an additional clock signal SUB_INC[y]c (y: 1, 2) coming from the DPLL can be selected as input clock for the TBU_BASE_[y]. This clock in combination with the DIR[y] signals determines the counter direction of the TBU_BASE_[y]. The downward counter can be disabled inside the TBU_CH[y]_CTRL register by selecting upward counter mode only.

The selected time stamp clock signal for the TBU_BASE_0 subunit is served via the TS_CLK signal line to the DPLL sub module. The TS_CLK signal equals the signal TBU_UP 0 .

TBU Time Base Channels

The time base values are generated within the TBU time base channels in two independent operation modes.

TBU Channel Modes

TBU channel 0 provides only a free running counter mode. TBU channel 1 and channel 2 can run in two modes; the free running counter mode also present in channel 0 and forward/backward counter mode, where the time base can run backwards dependent on the DIR[y] input signal values.

In both modes, the time base register TBU_CH[z]_BASE can be initialized with a start value just before enabling the corresponding TBU channel.

Moreover, the time base register TBU_CH[z]_BASE can always be read in order to determine the actual value of the counter.

Free Running Counter Mode

In TBU Free running counter mode, the time base register TBU_CH[z]_BASE is updated on every specified incoming clock event by the selected signal CMU_CLK[x] (dependent on TBU_CH[z]_CTRL register). In general the time base register TBU_CH[z]_BASE is incremented on every CMU_CLK[x] clock tick.

Forward/Backward Counter Mode

As mentioned above TBU channels 1 and 2 can also be configured to run in Forward/Backward Counter Mode. In this mode the DIR[y] signal provided by the DPLL is taken into account.

The value of the time base register TBU_CH[z]_BASE is incremented in case when the DIR[y] signal equals ‘0’ and decremented in case when the DIR[y] signal is T.

TBU Configuration Registers Overview

Following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register Name Description Section TBU_CHEN TBU global channel enable 0 TBU_CH0_CTRL TBU channel 0 control 0 TBU_CH0_BASE TBU channel 0 base 0 TBU_CH1_CTRL TBU channel 1 control 0 TBU_CH1_BASE TBU channel 1 base 0 TBU_CH2_CTRL TBU channel 2 control 0 TBU_CH2_BASE TBU channel 2 base 0 Note: In a typical application the Time Base Unit (TBU) considers channels 0 and 1 only. In this case register addresses 0 × 20 . . . 0 × 2C are reserved and shall be read as zero. Channel 2 can be additionally implemented on special high-end application requirements.

TBU Registers Description

Timer Input Module (TIM)

Overview

The Timer Input Module (TIM) is responsible for filtering and capturing input signals of the GTM. Several characteristics of the input signals can be measured inside the TIM channels. For advanced data processing the detected input characteristics of the TIM module can be routed through the ARU to subsequent processing units of the GTM.

Input characteristics mean either time stamp values of detected input rising or falling edges together with the new signal level or the number of edges received since channel enable together with the actual time stamp or PWM signal durations for a whole PWM period.

The architecture of TIM is shown in FIG. 13 .

TIM Block Diagram

See FIG. 13 .

Each of the eight (8) dedicated input signals is filtered inside the FLTx subunit of the TIM Module. It should be noted that the incoming input signals are synchronized to the clock SYS_CLK, resulting in a delay of two SYS_CLK periods for the incoming signals.

The sub module TIM provides different filter mechanisms described in more detail in Chapter 0 . After filtering, the signal is routed to the corresponding TIM channel.

The measurement values can be read by the CPU directly via the AEI-Bus or they can be routed through the ARU to other sub modules of the GTM.

For timeout detection of an incoming signal (no subsequent edge detected during a specified duration) each individual channel has a Timeout Detection Unit (TDU).

Two adjacent channels can be combined by setting the CICTRL bit field in the corresponding TIM[i]_CH[x]_CTRL register. This allows for a combination of complex measurements on one input signal with two TIM channels.

For the GTM-IP TIM 0 sub module only, the dashed signal outputs TIM[i]_CH[x] (23:0), TIM[i]_CH[x] (47:24) and TIM[i]_CH[x] (48) come from the TIM 0 sub module channels zero ( 0 ) to five ( 5 ) and are connected to MAP sub module. There, they are used for further processing and for routing to the DPLL.

TIM Filter Functionality (FLT)

Overview

The TIM sub module provides a configurable filter mechanism for each input signal. These filter mechanism is provided inside the FLT subunit.

FLT architecture is shown in FIG. 14 .

The filter includes a clock synchronisation unit (CSU), an edge detection unit (EDU), and a filter counter associated to the filter unit (FLTU).

The CSU is synchronizing the incoming signal F_IN to the selected filter clock frequency, which is controlled with the bit field FLT_CNT_FRQ of register TIM[i]_CH[x]_CTRL.

The synchronized input signal F_IN_SYNC is used for further processing within the filter.

It should be noted that glitches with a duration less than the selected CMU clock period are lost.

The filter modes can be applied individually to the falling and rising edges of an input signal. The following filter modes are available:

immediate edge propagation mode, individual de-glitch time mode (up/down counter), and individual de-glitch time mode (hold counter).

FLT Architecture

See FIG. 14 .

The filter parameters (De-Glitch and acceptance time) for the rising and falling edge can be configured inside the two filter parameter registers FLT_RE (rising edge) and FLT_FE (falling edge). The exact meaning of the parameter depends on the filter mode.

However the delay time T of both filter parameters FLT_xE can always be determined by:

T =( FLT _ xE+ 1)* T FLT _ CLK ,

whereas T FLT _ CLK is the clock period of the selected CMU clock signal in bit field FLT_CNT_FRQ of register TIM[i]_CH[x]_CTRL.

When a glitch is detected on an input signal a status flag GLITCHDET is set inside the TIM[i]_CH[x]_IRQ_NOTIFY register.

Table 0 gives an overview about the meanings for the registers FLT_RE and FLT_FE. In the individual De-Glitch time modes, the actual filter threshold for a detected regular edge is provided on the TIM[i]_CH[x] (47:24) output line. In the case of immediate edge propagation mode, a value of zero is provided on the TIM[i]_CH[x] (47:24) output line.

The TIM[i]_CH[x] (47:24) output line is used by the MAP sub module for further processing (please see chapter 0 ).

Filter Parameter Summary for the Different Filter Modes

A counter FLT_CNT is used to measure the glitch and acceptance times.

The frequency of the FLT_CNT counter is configurable in bit field FLT_CNT_FRQ of register TIM[i]_CH[x]_CTRL.

The counter FLT_CNT can either be clock with the CMU_CLK 0 , CMU_CLK 1 , CMU_CLK 6 or the CMU_CLK 7 signal. This signals are coming from the CMU sub module.

The FLT_CNT, FLT_FE and FLT_RE registers are 24-bit width. For example, when the resolution of the CMU_CLK 0 signal is 50 ns this allows maximal de-glitch and acceptance times of about 838 ms for the filter.

TIM Filter Modes

Immediate Edge Propagation Mode

In immediate edge propagation mode after detection of an edge the new signal level on F_IN_SYNC is propagated to F_OUT with a delay of one T FLT _ CLK period and the new signal level remains unchanged until the configured acceptance time expires.

For each edge type the acceptance time can be specified separately in the FLT_RE and FLT_FE registers.

Each signal change on the input F_IN_SYNC during the duration of the acceptance time has no effect on the output signal level F_OUT of the filter but it sets the glitch GLITCHDET bit in the TIM[i]_CH[x]_IRQ_NOTIFY register.

After an acceptance time expires the input signal F_IN_SYNC is observed and on signal level change the filter raises a new detected edge and the new signal level is propagated to F_OUT.

Independent of a signal level change the value of F_OUT is always set to F_IN_SYNC when the acceptance time expires (see also 0 ).

FIG. 15 shows an example for the immediate edge propagation mode, in the case of rising edge detection. Both, the signal before filtering (F_IN) and after filtering (F_OUT) are shown. The acceptance time at 1 is specified in the register FLT_RE.

Immediate Edge Propagation Mode in the Case of a Rising Edge

See FIG. 15 .

In immediate edge propagation mode the glitch measurement mechanism is not applied to the edge detection. Detected edges on F_IN_SYNC are transferred directly to F_OUT.

The counter FLT_CNT is incremented until acceptance time threshold is reached.

FIG. 16 shows a more complex example of the TIM filter, in which both, rising and falling edges are configured in immediate edge propagation mode.

Immediate Edge Propagation Mode in the Case of a Rising and Falling Edge

See FIG. 16 .

If the FLT_CNT has reached the acceptance time for a specific signal edge and the signal F_IN_SYNC has already changed to the opposite level of F_OUT, the opposite signal level is set to F_OUT and the acceptance time measurement is started immediately. FIG. 16 shows this scenario at the detection of the first rising edge and the second falling edge.

Individual De-Glitch Time Mode (Up/Down Counter)

In individual de-glitch time mode (up/down counter) each edge of an input signal can be filtered with an individual de-glitch threshold filter value mentioned in the registers FLT_RE and FLT_FE, respectively.

The filter counter register FLT_CNT is incremented when the signal level on F_IN_SYNC is unequal to the signal level on F_OUT and decremented if F_IN_SYNC equals F_OUT.

If After FLT_CNT has reached a value of zero during decrementation the counter is stopped immediately.

If a glitch is detected a glitch detection bit GLITCHDET is set in the TIM[i]_CH[x]_IRQ_NOTIFY register.

The detected edge signal together with the new signal level is propagated to F_OUT after the individual de-glitch threshold is reached. FIG. 17 shows the behaviour of the filter in individual de-glitch time (up/down counter) mode in the case of the rising edge detection.

Individual De-Glitch Time Mode (up/Down Counter) in the Case of a Rising Edge

See FIG. 17 .

Individual De-Glitch Time Mode (hold Counter)

In individual de-glitch time mode (hold counter) each edge of an input signal can be filtered with an individual de-glitch threshold filter value mentioned in the registers FLT_RE and FLT_FE, respectively.

The filter counter register FLT_CNT is incremented when the signal level on F_IN_SYNC is unequal to the signal level on F_OUT and the counter value of FLT_CNT is hold if FIN equals F_OUT.

If a glitch is detected the glitch detection bit GLITCHDET is set in the TIM[i]_CH[x]_IRQ_NOTIFY register.

The detected edge signal together with the new signal level is propagated to F_OUT after the individual de-glitch threshold is reached. FIG. 18 shows the behaviour of the filter in individual de-glitch time (hold counter) mode in the case of the rising edge detection.

Individual De-Glitch Time Mode (Hold Counter) in the Case of a Rising Edge

See FIG. 18 .

Immediate Edge Propagation and Individual De-Glitch Mode

As already mentioned, the three different filter modes can be applied individually to each edge of the measured signal.

However, if one edge is configured with immediate edge propagation and the other edge with an individual De-Glitch mode (whether up/down counter or hold counter) a special consideration has to be applied.

Assume that the rising edge is configured for immediate edge propagation and the falling edge with individual De-Glitch mode (up/down counter) as shown in FIG. 19 . If the falling edge of the incoming signal already occurs during the measuring of the acceptance time of the rising edge, the measurement of the De-Glitch time on the falling edge is started delayed, but immediately after the acceptance time measurement phase of the rising edge has finished.

Consequently, the De-Glitch counter can not measure the time T ERROR , as shown in FIG. 0 .

Mixed Mode Measurement

See FIG. 19 .

Timeout Detection Unit (TDU)

The Timeout Detection Unit (TDU) is responsible for timeout detection of the TIM input signals.

Each channel of the TIM sub module has its own Timeout Detection Unit (TDU) where a timeout event can be set up on the filtered input signal of the corresponding channel.

The TDU architecture is shown in FIG. 20 .

Architecture of the TDU Subunit

See FIG. 20 .

It is possible to detect timeouts with the resolution of the specified CMU_CLKx input signal selected with the bit field TCS of the register TIM[i]_CH[x]_TDU. The individual timeout values have to be specified in number of ticks of the selected input clock signal and have to be specified in the field TOV of timeout value register TIM[i]_CH[x]_TDU of the TIM channel x (x:0 . . . 7).

The exact time out value T TDU can be calculated with:

T TDU =(TOV+1)* T CMU _ GCLKx ,

whereas T CMU ♯ GCLKx is the clock period of the selected CMU clock signal.

Timeout detection can be enabled or disabled individually inside the TIM[i]_CH[x]_TDU register by setting/resetting the TO_EN bit.

The counter TO_CNT is reset by each detected input edge coming either from the filtered input signal or when the timeout value TOV is reached by the counter TO_CNT.

After such a reset or by enabling the channel inside the TIM[i]_CH[x]_CTRL register the counter TO_CNT starts counting again with the specified clock input signal.

Otherwise, timeout measurements starts immediately after the TO_EN bit inside the TIM[i]_CH[x]_TDU register is written.

The TDU generates an interrupt signal TIM_TODETx_IRQ whenever a timeout is detected for an individual input signal, and the TODET bit is set inside the TIM[i]_CH[x]_IRQ_NOTIFY register.

TIM Channel Architecture

Overview

Each TIM channel consist of an input edge counter ECNT, a Signal Measurement Unit (SMU) with a counter CNT, a counter shadow register CNTS for SMU counter and two general purpose registers GPR 0 and GPR 1 for value storage.

The value TOV of the timeout register TIM[i]_CH[x]_TDU is provided to TDU subunit of each individual channel for timeout measurement. The architecture of the TIM channel is depicted in FIG. 21 .

TIM Channel Architecture

See FIG. 21 .

Each TIM channel receives both input trigger signals REDGE_DETx and FEDGE_DETx, generated by the corresponding filter module in order to signalize a detected echo of the input signal F_INx. The signal F_OUTx shows the filtered signal of the channel's input signal F_INx.

The ECNT counts every incoming filtered edge (rising and falling). The counter value is uneven in case of detected rising, and even in case of detected falling edge. Thus, the input signal level is part of the counter and can be obtained by bit 0 of ECNT

Thus, the whole 8 bit counter value is always odd, when a positive edge was received and always even, when a negative edge was received.

The current ECNT register content is made visible on the bits 31 down to 24 of the GPRx and CNTS registers. This allows the software to detect inconsistent read accesses to registers GPR 0 , GPR 1 , and CNTS.

When new data is written into GPR 0 and GPR 1 the NEWVAL bit is set in TIM[i]_CH[x]_IRQ_NOTIFY register and depending on corresponding enable bit value the NEWVALx_IRQ interrupt is raised.

If new data was produced by the TIM channel while the old data is not consumed by the CPU (bit NEWVAL is still set inside TIM[i]_CH[x]_IRQ_NOTIFY register), the TIM channel raises a TIM_GPRXOFLx_IRQ interrupt depending on GPRXOFL_IRQ_EN bit, sets the GPRXOFL bit inside the status register TIM[i]_CH[x]_IRQ_NOTIFY and overwrites the data inside the GPRx registers.

Each TIM input channel has an ARU connection for providing data via the ARU to the other GTM sub modules. The data provided to the ARU depends on the TIM channel mode and its corresponding adjustments (e.g. multiplexer configuration).

To guarantee a consistent delivery of data from the GPR 0 and GPR 1 registers to the ARU or the CPU each TIM channel has to ensure that the data valid signal is raised after both registers have been updated with new and valid data.

The data inside the GPRx registers is marked invalid (DVAL is reset) either the data is read out by the ARU (only if ARU_EN=1) or while the data of register GPR 0 is read by CPU (only if ARU_EN=0).

When new values have been calculated inside the CNT and CNTS registers and the DVAL signal is still set, which means the ARU or CPU has not read out the data of GPR 0 yet in, the TIM channel raises the data overflow interrupt TIM_GPRXOFLx_IRQ, and it overwrites GPR 0 and GPR 1 with the new data and sets the DVAL signal valid again.

TIM Channel Modes

The TIM provides five different measurement modes that can be configured with the bit field TIM_MODE of register TIM[i]_CH[x]_CTRL. The measurement modes are described in the following subsections. Besides these different basic measurement modes, there exist distinct configuration bits in the register TIM[i]_CH[x]_CTRL for a more detailed controlling of each mode. The meanings of these bits are as follows:

DSL: control the signal level for the measurement modes (e.g. if a measurement is started with rising edge or falling edge, or if high level pulses or low level pulses are measured. GPR 0 _SEL and GPR 1 _SEL: control the actual content of the registers GPR 0 and GPR 1 after a measurement has finished. CNTS_SEL: control the content of the registers CNTS. The actual time for updating the CNTS register is mode dependent. OSM: activate measurement in one-shot mode or continuous mode. In one-shot mode only one measurement cycle is performed and after that the channel is disabled. NEWVAL: The NEWVAL IRQ interrupt is triggered at the end of a measurement cycle, signalling that the registers GPR 0 and GPR 1 are updated. ARU_EN: enables sending of the registers GPR 0 and GPR 1 together with the actual signal level (in bit 48 ) and the overflow signal GPRxOFL (in bit 49 ) to the ARU.

TIM PWM Measurement Mode (TPWM)

In TIM PWM Measurement Mode the TIM channel measures duty cycle and period of an incoming PWM signal. The DSL bit defines the polarity of the PWM signal to be measured.

When measurement of pulse high time and period is requested (PWM with a high level duty cycle, DSL=1), the channel starts measuring after the first rising edge is detected by the filter.

Measurement is done with the CNT register counting with the configured clock coming from CMU_CLKx until a falling edge is detected.

Then the counter value is stored inside the shadow register CNTS (if CNTS_SEL=0) and the counter CNT counts continuously until the next rising edge is reached.

On this following rising edge the content of the CNTS register is transferred to GPR 0 and the content of CNT register is transferred to GPR 1 , assuming settings for the selectors GPR 0 _SEL=1 and GPR 1 _SEL=1. By this, GPR 0 contains the duty cycle length and GPR 1 contains the period.

In addition the CNT register is cleared NEWVAL status bit inside of TIM[i]_CH[x]_IRQ_NOTIFY status register and depending on corresponding interrupt enable condition TIM_NEWVALx_IRQ interrupt is raised.

If a PWM with a low level duty cycle should be measured (DSL=0), the channel waits for a falling edge until measurement is started. On this edge the low level duty cycle time is stored first in CNTS and then finally in GPR 0 and the period is stored in GPR 1 .

When a PWM period was successfully measured, the data in GPRx registers is marked as valid for reading by the ARU when the ARU_EN bit is set inside TIM[i]_CH[x]_CTRL register, the NEWVAL bit is set inside the TIM[i]_CH[x]_IRQ_NOTIFY register, and a new measurement is started.

If the preceding PWM values were not consumed by a reader attached to the ARU (ARU_EN bit enabled) or by the CPU the TIM channel set GPRXOFL status bit in TIM[i]_CH[x]_IRQ_NOTIFY and depending on corresponding interrupt enable bit value raises a GPRXOFLx_IRQ and overwrites the old values in GPR 0 and GPR 1 . A new measurement is started afterwards.

TIM Pulse Integration Mode (TPIM)

In TIM Pulse Integration Mode each TIM channel is able to measure a sum of pulse high or low times on an input signal, depending on the selected signal level bit DSL of register TIM[i]_CH[x]_CTRL register.

The pulse times are measured by incrementing the TIM channel counter CNT whenever the pulse has the specified signal level DSL. The counter is stopped whenever the input signal has the opposite signal level.

The counter CNT counts with the CMU_CLKx clock specified by the CLK_SEL bit field of the TIM[i]_CH[x]_CTRL register.

The CNT register is reset at the time the channel is activated (enabling via AEI write access) and it accumulates pulses while the channel is staying enabled.

Whenever the counter is stopped, the registers CNTS, GPR 0 and GPR 1 are updated according to settings of its corresponding input multiplexers, using the bits GPR 0 _SEL, GPR 1 _SEL, and CNTS_SEL.

When the ARU_EN bit is set inside the TIM[i]_CH[x]_CTRL register the measurement results of the registers GPR 0 and GPR 1 can be send to subsequent sub modules attached to the ARU.

TIM Input Event Mode (TIEM)

In TIM Input Event Mode the TIM channel is able to count edges.

It is configurable if rising, falling or both edges should be counted. This can be done with the bit fields DSL and ISL in TIM[i]_CH[x]_CTRL register.

In addition, a TIM[i]_NEWVAL[x]_IRQ interrupt is raised when the configured edge was received and this interrupt was enabled.

The counter register CNT is used to count the number of edges, and the bit fields GPR 0 _SEL, GPR 1 _SEL, and CNTS_SEL can be used to configured the desired update values for the registers GPR 0 , GPR 1 and CNTS. These register are updated whenever the edge counter CNT is incremented due to the arrival of a desired edge. If the preceding data was not consumed by a reader attached to the ARU or by the CPU the TIM channel sets GPRXOFL status bit and raises a GPRXOFL[x]_IRQ if it was enabled in TIM[i]_CH[x]_IRQ_EN register and overwrites the old values in GPR 0 and GPR 1 with the new ones.

On CNT counter overflow a TIM_CNTOFL[x]_IRQ interrupt is raised (if it was enabled) and a corresponding status bit is set inside the channel interrupt status register TIM[i]_CH[x]_IRQ_NOTIFY.

TIM Input Prescaler Mode (TIPM)

In the TIM Input Prescaler Mode the number of edges which should be detected before a TIM[i]_NEWVAL[x]_IRQ is raised is programmable. In this mode it must be specified in the CNTS register after how many edges the interrupt has to be raised. A value of 0 in CNTS means that after one edge an interrupt is raised, and a value of 1 means that after two edges an interrupt is raised, and so on.

The edges to be counted can be selected by the bit fields DSL and ISL of register TIM[i]_CH[x]_CTRL.

With each triggered interrupt, the registers GPR 0 and GPR 1 are updated according to bits GPR 0 _SEL and GPR 1 _SEL.

TIM Bit Compression Mode (TBCM)

The TIM Bit Compression Mode can be used to combine all filtered input signals of a TIM sub module to a parallel 8 bit data word, which can be routed to the ARU. Since this mode uses all eight input signals with its input filters, it is only available within TIM channel 0 of each TIM sub module. FIG. 22 gives an overview of the TIM bit compression mode.

TIM Bit Compression Mode

See FIG. 22 .

A meaningful usage of the TBCM configures all input filters properly, enables TIM channel 0 in bit compression mode and it disables the channels 1 to 7 .

The register CNTS of TIM channel 0 is used to configure the event that releases the NEWVAL_IRQ and samples the input signals F_IN( 0 ) to F_IN( 7 ) in ascending order as a parallel data word in GPR 1 .

The bits 0 to 7 of the CNTS register are used to select the REDGE_DET signals of the TIM filters 0 to 7 as a sampling event, and the bits 8 to 15 are used to select the FEDGE_DET signals of the TIM filters 0 to 7 , respectively. If multiple events are selected, the events are OR-combined (see also FIG. 22 ).

GRP 0 _SEL selects the timestamp value, which is routed through the ARU.

GRP 1 _SEL is not applicable in TBCM mode.

If the bit ARU_EN of register TIM[i]_CH 0 _CTRL is set, the sampled data of register GPR 1 is routed together with a time stamp of register GPR 0 to the ARU, whenever the NEWVAL_IRQ is released.

MAP Sub Module Interface

The GTM-IP provides one dedicated TIM sub module TIM 0 where channels zero (0) to five (5) are connected to the MAP sub module described in Chapter 0 . There, the TIM 0 sub module channels provide the input signal level together with the actual filter value and the annotated time stamp for the edge together in a 49 bit wide signal to the MAP sub module. This 49 bit wide data signal is marked as valid with a separate valid signal tim 0 _map_dval[x] (x:0 . . . 5).

tim0_map_data0 (48) signal level bit from tim0_ch0 tim0_map_data0 (47:24) actual filter value TIM0_CH0_FLT_ RE/TIM0_CH0_FLT_FE tim0_map_data0 (23:0) time stamp value of GRP0 register tim0_map_dval0 mark tim0_map_data0 valid for one clock cycle

TIM Interrupt Signals

TIM provides 6 interrupt lines per channel. These interrupts are shown below:

Signal Description TIM[i]_NEWVAL[x]_IRQ New measurement value detected by SMU of channel x (x: 0. . . 7) TIM[i]ECNTOFL[x]_IRQ ECNT counter overflow of channel x (x: 0 . . . 7) TIM[i]_CNTOFL[x]_IRQ SMU CNT counter overflow of channel x (x: 0 . . . 7) TIM[i]_GPRXOF[x]_IRQ GPRx data overflow, old data was not read out before new data has arrived at input pin (x: 0 . . . 7) TIM[i]_TODET[x]_IRQ Time out reached for input signal of channel x (x: 0 . . . 7) TIM[i]_GLITCHDET_IRQ A glitch was detected by the TIM filter of channel (x: 0 . . . 7).

TIM Configuration Registers Overview

TIM contains following configuration registers:

Detail in Register Name Description Section TIM[i]_CH[x]_CTRL channel x (x: 0 . . . 7) 0 control TIM[i]_CH[x]_FLT_FE channel x (x: 0 . . . 7) 0 filter parameter 0 TIM[i]_CH[x]_FLT_RE channel x (x: 0 . . . 7) 0 filter parameter 1 TIM[i]_CH[x]_TDU channel x (x: 0 . . . 7) 0 TDU control. TIM[i]_CH[x]_GPRO channel x (x: 0 . . . 7) 0 general purpose 0 TIM[i]_CH[x]_GPR1 channel x (x: 0 . . . 7) 0 general purpose 1 TIM[i]_CH[x]_CNT channel x (x: 0 . . . 7) 0 SMU counter TIM[i]_CH[x]_CNTS channel x (x: 0 . . . 7) 0 SMU shadow counter TIM[i]_CH[x]_IRQ_NOTIFY channel x (x: 0 . . . 7) 0 interrupt notification TIM[i]_CH[x]_IRQ_EN channel x (x: 0 . . . 7) 0 interrupt enable TIM[i]_CH[x]_IRQ_FORCINT channel x (x: 0 . . . 7) 0 software interrupt force TIM[i]_RST TIM global software 0 reset TIM[i]_CH[x]_IRQ_MODE IRQmode 0 configuration register (x = 0 . . . 7)

TIM Configuration Registers Description

Timer Output Module (TOM)

Overview

The Timer Output Module (TOM) offers 16 independent channels to generate simple PWM signals at each output pin TOM[i]_CH[x]_OUT (x=0 . . . 15).

Additionally, at TOM output TOM[i]_CH15_OUT a pulse count modulated signal can be generated.

The architecture of the TOM sub module is depicted in FIG. 23 .

TOM Block Diagram

See FIG. 23 .

The two sub modules TGC 0 and TGC 1 are global channel control units that control the enabling/disabling of the channels and their outputs as well as the update of their period and duty cycle register.

The module TOM receives two (three) timestamp values TBU_TS 0 , TBU_TS 1 (and TBU_TS 2 ) in order to realize synchronized output behaviour on behalf of a common time base.

The 5 dedicated clock line inputs CMU_FXCLK are providing divided clocks that can be selected to clock the output pins.

TOM Global Channel Control (TGCx)

Overview

There exist two global channel control units (TGC 0 and TGC 1 ) to drive a number of individual TOM channels synchronously by external or internal events.

One TGCx can drive up to eight TOM channels where TGC 0 controls TOM channels 0 to 7 and TGC 1 controls TOM channels 8 to 15 .

The TOM sub module supports four different kinds of signalling mechanisms:

Global enable/disable mechanism for each TOM channel with control register TOM[i]_TGC[x]_ENDIS_CTRL and status register TOM[i]_TGC[x]_ENDIS_STAT (with x=0,1) Global output enable mechanism for each TOM channel with control register TOM[i]_TGC[x]_OUTEN_CTRL and status register TOM[i]_TGC[x]_OUTEN_STAT (with x=0,1) Global force update mechanism for each TOM channel with control register TOM[i]_TGC[x]_FUPD_CTRL (with x=0,1) Update enable of the register CM 0 , CM 1 and CLK_SRC_STAT for each TOM channel with the control bit field UPEN_CTRL[y] of TOM[i]_TGC[x]_GLB_CTRL (with y=0 . . . 7; x=0,1)

TGC Subunit

Each of the first three individual mechanisms (enable/disable of the channel, output enable and force update) can be driven by three different trigger sources. The three trigger sources are:

the host CPU (bit HOST_TRIG of register TOM[i]_TGC[x]_GLB_CTRL) the TBU time stamp (signal TBU_TS[x] with x=0 . . . 2) the internal trigger signal TRIG (bunch of trigger signals TRIG_[y], y=0 . . . 7/8 . . . 15)

The first way is to trigger the control mechanism by a direct register write access via host CPU (bit HOST_TRIG of register TOM[i]_TGC[x]_GLB_CTRL).

The second way is provided by a compare match trigger on behalf of a specified time base coming from the module TBU (selected by bits TBU_SEL) and the time stamp compare value defined in the bit field ACT_TB of register TOM[i]_TGC[x]_ACT_TB (with x=0,1).

The third possibility is the input TRIG (bunch of trigger signals TRIG_[y], y=0 . . . 7/8 . . . 15) coming from the TOM channels 0 to 7 / 8 to 15 .

The corresponding trigger signal TRIG_y coming from channel y can be masked by the register TOM[i]_TGC[x]_INT_TRIG (x=0,1).

To enable or disable each individual TOM channel, the registers TOM[i]_TGC[x]_ENDIS_CTRL and TOM[i]_TGC[x]_ENDIS_STAT have to be used.

The register TOM[i]_TGC[x]_ENDIS_STAT controls directly the signal ENDIS. A write access to this register is possible.

The register TOM[i]_TGC[x]_ENDIS_CTRL is a shadow register that overwrites the value of register TOM[i]_TGC[x]_ENDIS_STAT if one of the three trigger conditions matches.

TOM Global Channel Control Mechanism

See FIG. 24 .

The output of the individual TOM channels can be controlled using the register TOM[i]_TGC[x]_OUTEN_CTRL and TOM[i]_TGC[x]_OUTEN_CTRL.

The register TOM[i]_TGC[x]_OUTEN_STAT controls directly the signal OUTEN. A write access to this register is possible.

The register TOM[i]_TGC[x]_OUTEN_CTRL is a shadow register that overwrites the value of register TOM[i]_TGC[x]_OUTEN_STAT if one of the three trigger conditions matches.

TOM[i]_TGC[x]_If a TOM channel is disabled by the register TOM[i]_TGC[x]_OUTEN_STAT, the actual value of the channel is defined by the signal level bit (SL) defined in the channel control register TOM[i]_CH[x]_CTRL (x=0 . . . 7).

The register TOM[i]_TGC[x]_FUPD_CTRL defines which of the TOM channels receive a FORCE UPDATE event if the trigger signal CTRL_TRIG is raised.

The register bits UPEN_CTRL[x] (with x=0 . . . 7) defines for which TOM channel the update of the working register CM 0 , CM 1 and CLK_SRC by the corresponding shadow register SR 0 , SR 1 and CLK_SRC_SR is enabled. If update is enabled, the register CM 0 , CM 1 and CLK_SRC will be updated on reset of counter register CN 0 (see FIG. 25 ).

The whole control logic is doubled by means of the two TOM global control units TGC 0 and TGC 1 .

TOM Channel (TOM_CHx)

Each individual TOM channel comprises a Counter Compare Unit 0 (CCU 0 ), a Counter Compare Unit 1 (CCU 1 ) and the Signal Output Generation Unit (SOU). The architecture is depicted in FIG. 25 .

TOM Channel Architecture

See FIG. 25 .

The CCU 0 contains a counter CN 0 which is clocked with one of the selected input frequencies (CMU_FXCLK) provided from outside of the sub module.

The counter can be reset either when the counter value is equal to the compare value CM 0 or when signalled by the Trigger signal TRIG_[y−1] of the preceding channel y−1 or sub module (depending on configuration bits RST_CCU 0 of register TOM[i]_CH[c]_CTRL with c=0 . . . 15).

When the counter register CN 0 is greater or equal than the register CM 0 , the subunit CCU 0 triggers the SOU subunit and the succeeding TOM sub module channel (signal TRIG_CCU 0 ).

In the subunit CCU 1 the counter register CN 0 is compared with the value of register CM 1 . If CN 0 is greater or equal than CM 1 the subunit CCU 1 triggers the SOU subunit (signal TRIG_CCU 1 ).

The configuration of CM 1 =0 represents 0% duty cycle at the output, the configuration of CM 1 >=CM 0 represents 100% duty cycle. If both registers are configured to 0 (CM0=CM1=0), the output is 0% duty cycle.

The hardware ensures that for both 0% and 100% duty cycle no glitch occurs at the output of the TOM channel.

The SOU subunit is responsible for output signal generation. On a trigger TRIG_CCU 0 from subunit CCU 0 or TRIG_CCU 1 from subunit CCU 1 a SR-Flip-Flop of subunit SOU is either set or reset. If it is set or reset depends on the configuration bit SL of the control register TOM[i]_CH[c]_CTRL (with c=0 . . . 15).The initial signal output level for the channel is the reverse value of the bit SL.

FIG. 28 clarifies the PWM output behaviour with respect to the SL bit definition. The output level on the TOM channel output pin TOM[i]_CH[x]_OUT is captured in bit OL of register TOM[i]_CH[c]_STAT (c=0 . . . 15).

Duty Cycle, Period and Selected Counter Clock Frequency Update Mechanisms

The two action registers CM 0 and CM 1 can be reloaded with the content of the shadow registers SR 0 and SR 1 . The register CLK_SRC that determines the clock frequency of the counter register CN 0 can be reloaded with its shadow register CLK_SRC_SR (bit field in register TOM[i]_CH[c]_CTRL, c=0 . . . 15)

The update of the register CM 0 , CM 1 and CLK_SRC with the content of its shadow register is done when the reset of the counter register CN 0 is requested (via signal RESET). This reset of CN 0 is done if the comparison of CN 0 greater or equal than CM 0 is true or when the reset is triggered by another TOM channel c−1 via the signal TRIG_[c−1].

With the update of the register CLK_SRC at the end of a period a new counter CN 0 clock frequency can easily be adjusted.

An update of duty cycle, period and counter CN 0 clock frequency becoming effective synchronously with start of a new period can easily be reached by performing following steps:

1. disable the update of the action register with the content of the corresponding shadow register by setting the channel specific configuration bit UPEN_CTRL[c] (c=0 . . . 7) of register TOM[i]_TGC[x]_GLB_CTRL to ‘0’ (x=0,1). 2. write new desired values to SR 0 , SR 1 , CLK_SRC_SR 3. enable update of the action register by setting the channel specific configuration bit UPEN_CTRL[c] of register TOM[i]_TGC[x]_GLB_CTRL to ‘1’.

Synchronous Update of Duty Cycle Only

A synchronous update of only the duty cycle can be done by simply writing the desired new value to register SR 1 without preceding disable of the update mechanism (as described in the chapter above). The new duty cycle is then applied in the period following the period where the update of register SR 1 was done.

Synchronous Update of Duty Cycle

See FIG. 26 .

Asynchronous Update of Duty Cycle Only

If the update of the duty cycle should be performed independent of the start of a new period (asynchronous), the desired new value can be written directly to register CM 1 . In this case it is recommended to additionally either disable the synchronous update mechanism as a whole (i.e. clearing bits UPEN[x] of corresponding channel x in register TOM[i]_TGX[x]_GLB_CTRL) or updating SR 1 with the same value as CM 1 before writing to CM 1 .

Depending on the point of time of the update of CM 1 in relation to the actual value of CN 0 and CM 1 , the new duty cycle is applied in the current period or the following period (see Figure In any case the creation of glitches are avoided. The new duty cycle may jitter from update to update by a maximum of one period (given by CM 0 ). However, the period remains unchanged.

Asynchronous Update of Duty Cycle

See FIG. 27 .

TOM Continuous Mode

In continuous mode the TOM channel starts incrementing the counter register CN 0 once it is enabled by setting the corresponding bits in register TOM[i]_TGC[x]_ENDIS_STAT (refer to chapter 0 for details of enabling a TOM channel).

The signal level of the generated output signal can be configured with the configuration bit SL of the channel configuration register TOM[i]_CH[c]_CTRL (c=0 . . . 15).

If the counter CN 0 is reset from CM 0 back to zero, the first edge of a period is generated at TOM[i]_CH[x]_OUT.

The second edge of the period is generated if CN 0 has reached CM 1 .

Every time the counter CN 0 has reached the value of CM 0 it is reset back to zero and proceeds with incrementing.

PWM Output with Respect to Configuration Bit SL in Continuous Mode

See FIG. 28 .

TOM One Shot Mode

In One-shot mode, the TOM channel generates one pulse with a signal level specified by the configuration bit SL in the channel c configuration register TOM[i]_CH[c]_CTRL.

First the channel has to be enabled by setting the corresponding TOM[i]_TGC[x]_ENDIS_STAT value and the one-shot mode has to be enabled by setting bit OSM in register TOM[i]_CH[x]_CTRL.

In one-shot mode the counter CN 0 will not be incremented once the channel is enabled.

A write access to the register CN 0 triggers the start of pulse generation (i.e. the increment of the counter register CN 0 ).

If SPE mode of TOM[i] channel 2 is enabled (set bit SPEM of register TOM[i]_CH 2 _CTRL), also the trigger signal SPE[i]_NIPD can trigger the reset of register CN 0 to zero and a start the pulse generation.

The new value of CN 0 determines the start delay of the first edge. The delay time of the first edge is given by (CM 0 -CN 0 ) multiplied with period defined by current value of CLK_SRC.

If the counter CN 0 is reset from CM 0 back to zero, the first edge at TOM[i]_CH[x]_OUT is generated.

The second edge is generated if CN 0 is greater or equal than CM 1 (i.e. CN 0 was incremented until it has reached CM 1 or CN 0 is greater than CM 1 after an update of CM 1 ).

If the counter CN 0 has reached the value of CM 0 a second time, the counter stops.

PWM Output with Respect to Configuration Bit SL in One-Shot Mode

See FIG. 29 .

Further output of single periods can be started by a write access to register CN 0 .

Pulse Count Modulation

At the output TOM_CH 15 _OUT a pulse count modulated signal can be generated instead of the simple PWM output signal.

FIG. 31 outlines the circuit for Pulse Count Modulation.

The PCM mode is enabled by setting bit BITREV to 1 .

With the configuration bit BITREV=1a bit-reversing of the counter output CN 0 is configured. In this case the bits LSB and MSB are swapped, the bits LSB+1 and MSB−1 are swapped, the bits LSB+2 and MSB−2 are swapped and so on.

The effect of bit-reversing of the CN 0 register value is shown in the following FIG. 30 .

Bit Reversing of Counter CN 0 Output

See FIG. 30 .

In the PCM mode the counter register CN 0 is incremented by every clock tick depending on configured CMU clock (CMU_FXCLK).

The output of counter register CN 0 is first bit-reversed and than compared with the configured register value CM 1 .

If the bit-reversed value of register CN 0 is greater than CM 1 , the SR-FlipFlop of sub module SOU is set (depending on configuration register SL) otherwise the SR-FlipFlop is reset. This generates at the output TOM_CH 15 _OUT a pulse count modulated signal.

In PCM mode the CM 0 register always has to be set to its maximum value 0xFFFF.

PCM Generation on TOM Channel 15

See FIG. 31 .

TOM BLDC Support

The TOM sub module offers in combination with the SPE sub module a BLDC support. To drive a BLDC engine TOM channels 0 to 7 can be used.

The BLDC support can be configured by setting the SPEM bit inside the TOM[i]_CH[c]_CTRL register (c: 0 . . . 7). When this bit is set the TOM channel output is controlled through the SPE_OUT(x) signal coming from the SPE sub module (see FIG. 56 ). Please refer to chapter 0 for a detailed description of the SPE sub module. The TOM[i]_CH 2 with i=0 . . . 3 can be used together with the SPE module to trigger a delayed update of the SPE_OUT_CTRL register after new input pattern detected by SPE (signalled by SPE[i]_NIPD). For details please refer to chapter of SPE sub module description.

TOM Gated Counter Mode

Each TOM-SPE module combination provides also the feature of a gated counter mode. This is reached by using the FSOI input of a TIM module to gate the clock of a CCU 0 sub module.

To configure this mode, registers of module SPE should be set as following:

the SPE should be enabled (bit SPE_EN=1), all three TIM inputs should be disabled (SIE 0 =SIE 1 =SIE 2 =0), SPE[i]_OUT_CTRL should be set to 00005555h (set SPE_OUT( ) to ‘0’), mode FSOM should be enabled (FSOM=1), set in bit field FSOL bit c if channel c of module TOM is chosen for gated counter mode

Additionally in module TOM

the SPE mode should be disabled (SPEM=0) and

the gated counter mode should be enabled (GCM=1)

As a result of this configuration, the counter CN 0 in sub module CCU 0 of TOM channel c counts as long as input FSOI is ‘0’.

TOM Interrupt Signals

The following table describes TOM interrupt signals:

Signal Description TOM_CCU0TCx_IRQ CCU0 Trigger condition interrupt for channel x TOM_CCU1TCx_IRQ CCU1 Trigger condition interrupt for channel x

TOM Configuration Register Overview

The following table shows a conclusion of configuration registers address offsets and initial values.

Details in Register name Description Section TOM[i]_TGC0_GLB_CTRL TGC0 global control reg 0 TOM[i]_TGC0_ENDIS_CTRL TGC0 enable/disable control reg 0 TOM[i]_TGC0_ENDIS_STAT TGC0 enable/disable status reg 0 TOM[i]_TGC0_ACT_TB TGC0 action time base register 0 TOM[i]_TGC0_OUTEN_CTRL TGC0 output enable control reg 0 TOM[i]_TGC0_OUTEN_STAT TGC0 output enable status regi 0 TOM[i]_TGC0_FUPD_CTRL TGC0 force update control reg 0 TOM[i]_TGC0_INT_TRIG TGC0 internal trigger control 0 TOM[i]_TGC1_GLB_CTRL TGC1 global control register 0 TOM[i]_TGC1_ENDIS_CTRL TGC1 enable/disable control reg 0 TOM[i]_TGC1_ENDIS_STAT TGC1 enable/disable status reg 0 TOM[i]_TGC1_ACT_TB TGC0 action time base register 0 TOM[i]_TGC1_OUTEN_CTRL TGC1 output enable control reg 0 TOM[i]_TGC1_OUTEN_STAT TGC1 output enable status reg 0 TOM[i]_TGC1_FUPD_CTRL TGC1 force update control reg 0 TOM[i]_TGC1_INT_TRIG TGC1 internal trigger control 0 TOM[i]_CH[x]_CTRL TOM Channel x control register 0 (x = 0 . . . 14) TOM[i]_CH15_CTRL TOM Channel 15 control reg 0 TOM[i]_CH[x]_CN0 TOM Channel x CCU0 counter 0 register (x = 0 . . . 15) TOM[i]_CH[x]_CM0 TOM Channel x CCU0 compare 0 register (x = 0 . . . 15) TOM[i]_CH[x]_SR0 TOM Channel x CCU0 compare 0 shadow register (x = 0 . . . 15) TOM[i]_CH[x]_CM1 TOM Channel x CCU1 compare 0 register (x = 0 . . . 15) TOM[i]_CH[x]_SR1 TOM Channel x CCU1 compare 0 shadow register (x = 0 . . . 15) TOM[i]_CH[x]_STAT TOM channel status (x = 0 . . . 15) 0 TOM[i]_CH[x]_IRQ_NOTIFY TOM channel x interrupt 0 notification register (x = 0 . . . 15) TOM[i]_CH[x]_IRQ_EN TOM channel x interrupt enable 0 register (x = 0 . . . 15) TOM[i]_CH[x]_IRQ_FORCINT TOM channel x software interrupt 0 generation (x = 0 . . . 15) 0 TOM[i]_CH[x]_IRQ_MODE IRQ mode configuration register 0 (x = 0 . . . 15)

TOM Configuration Registers Description

Register TOM[i]_TGC 1 _GLB_CTRL

Controls channel 8 to 15 : Address offset 0x0040 For description see 0

Register TOM[i]_TGC 1 _ENDIS_CTRL

Controls channel 8 to 15 : Address offset 0x0044 For description see 0

Register TOM[i]_TGC 1 _ENDIS_STAT

Controls channel 8 to 15 : Address offset 0x0048 For description see 0

Register TOM[i]_TGC 1 _ACT_TB

Controls channel 8 to 15 : Address offset 0x004C For description see 0

Register TOM[i]_TGC 1 _OUTEN_CTRL

Controls channel 8 to 15 : Address offset 0x0050 For description see 0

Register TOM[i]_TGC 1 _OUTEN_STAT

Controls channel 8 to 15 : Address offset 0x0054 For description see 0

Register TOM[i]_TGC 1 _FUPD_CTRL

Controls channel 8 to 15 : Address offset 0x0058 For description see 0

Register TOM[i]_TGC 1 _INT_TRIG

Controls channel 8 to 15 : Address offset 0x005C For description see 0

ARU-connected Timer Output Module (ATOM)

Overview

The ARU-connected Timer Output Module (ATOM) is able to generate complex output signals without CPU interaction due to its connectivity to the ARU. Typically, output signal characteristics are provided over the ARU connection through sub modules connected to ARU like e.g. the MCS, DPLL or PSM. Each ATOM sub module contains eight output channels which can operate independently from each other in several configurable operation modes. A block diagram of the ATOM sub module is depicted in FIG. 32 .

ATOM Block Diagram

See FIG. 32 .

The architecture of the ATOM sub module is similar to the TOM sub module, but there are some differences. First, the ATOM integrates only eight output channels. Hence, there exists one ATOM Global Control subunit (AGC) for the ATOM channels. The ATOM is connected to the ARU and can set up individual read requests from the ARU and write requests to the ARU. Furthermore, the ATOM channels are able to generate signals on behalf of time stamps and the ATOM channels are able to generate a serial output signal on behalf of an internal shift register.

Each ATOM channel provides four modes of operation:

ATOM Signal Output Mode Immediate (SOMI) ATOM Signal Output Mode Compare (SOMC) ATOM Signal Output Mode PWM (SOMP) ATOM Signal Output Mode Serial (SOMS)

These modes are described in more detail in section 0 .

In contrast to the TOM channels the ATOM channels' operation registers (e.g. counter, compare registers) are 24 bit wide. Moreover, the input clocks for the ATOM channels come from the configurable CMU_CLKx signals of the CMU sub module. This gives the freedom to select a programmable input clock for the ATOM channel counters. The ATOM channel is able to generate a serial bit stream, which is shifted out at the ATOM[i]_CH[x]_OUT output. When configured in this serial shift mode (SOMS) the selected CMU clock defines the shift frequency.

Each ATOM channel provides a so called operation and shadow register set. With this architecture it is possible to work with the operation register set, while the shadow register set can be reloaded with new parameters over CPU and/or ARU. When update via ARU is selected, it is possible to configure if both shadow registers are updated via ARU or only one of the shadow registers is updated.

On the other hand, the shadow registers can be used to provide data to the ARU when one or both of the compare units inside an ATOM channel match.

In TOM channels it is possible to reload the content of the operation registers with the content of the corresponding shadow registers and change the clock input signal for the counter register simultaneously. This simultaneous change of the input clock frequency together with reloading the operation registers is also implemented in the ATOM channels. In addition to the feature that the CPU can select another CMU_CLKx during operation (i.e. updating the shadow register bit field ACB of the ATOM[i]_CH[x]_CTRL register), the selection can also be changed via the ARU. Then, for the clock source update, the ACBI register bits of the ATOM[i]_CH[x]_STAT register are used as a shadow register for the CLK_SRC bit field inside the ATOM[i]_CH[x]_CTRL register.

In general, the behaviour of the compare units CCU 0 and CCU 1 and the output signal behaviour is controlled with the ACB bit field inside the ATOM[i]_CH[x]_CTRL register when the ARU connection is disabled and the behaviour is controlled via ARU through the ACBI bit field of the ATOM[i]_CH[x]_STAT register, when the ARU is enabled.

Since the ATOM is connected to the ARU, the shadow registers of an ATOM channel can be reloaded via the ARU connection or via CPU over its AEI interface. When loaded via the ARU interface, the shadow registers act as a buffer between the ARU and the channel operation registers. Thus, a new parameter set for a PWM can be reloaded via ARU into the shadow registers, while the operation registers work on the actual parameter set.

ATOM Global Control (AGC)

Synchronous start and stop of more then one output channel is possible with the AGC subunit. This subunit has the same functionality as the TGC subunit of the TOM sub module. For a description of the AGC subunit functionality, please refer therefore to chapter 0 .

ATOM Channel Mode Overview

As mentioned above, each ATOM channel offers four different operation modes.

In ATOM Signal Output Mode Immediate (SOMI), the ATOM channels generate an output signal immediately after receiving an ARU word according to the two signal level output bits of the ARU word received through the ACBI bit field. Due to the fact, that the ARU destination channels are served in a round robin order, the output signal can jitter in this mode with a jitter of the ARU round trip time.

In ATOM Signal Output Mode Compare (SOMC), the ATOM channel generates an output signal on behalf of time stamps that are located in the ATOM operation registers. These time stamps are compared with the time stamps, the TBU generates. The ATOM is able to receive new time stamps either by CPU or via the ARU. The new time stamps are directly loaded into the channels operation register. The shadow registers are used as capture registers for the two time base values, when a compare match of the channels operation registers occurs.

In ATOM Signal Output Mode PWM (SOMP), the ATOM channel is able to generate simple and complex PWM output signals like the TOM sub module by comparing its operation registers with a sub module internal counter. In difference to the TOM, the ATOM shadow registers can be reloaded by the CPU and by the ARU in the background, while the channel operates on the operation registers.

In ATOM Signal Output Mode Serial (SOMS), the ATOM channel generates a serial output bit stream on behalf of a shift register. The number of bits shifted and the shift direction is configurable. The shift frequency is determined by one of the CMU_CLKx clock signals. Please refer to section 0 for further details.

ATOM Channel Architecture

Each ATOM channel is able to generate output signals according to four operation modes. The architecture of the ATOM channels is similar to the architecture of the TOM channels. The general architecture of an ATOM channel is depicted in FIG. 33 .

ATOM Channel Architecture

See FIG. 33 .

Differences between the TOM and ATOM channels are the 24 bit width of the operation registers CN 0 , CM 0 and CM 1 and the shadow registers SR 0 and SR 1 . The comparators inside CCU 0 and CCU 1 provide a selectable signed greater/equal or less/equal comparison to compare against the GTM time bases TBU_TS 0 and TBU_TS 1 . If there is a third time base TBU_TS 2 implemented inside the GTM, this time base can also be selected inside the ATOM channel with the TB 12 _SEL bit inside the ATOM[i]_CH[x]_CTRL register for comparison. Please refer to TBU chapter 0 for further details. For an overview of the implemented TBU sub module version please refer to chapter 0 . The CCU 0 and CCU 1 units have different tasks for the different ATOM channel modes.

The signed compare is used to detect time base overflows and to guarantee, that a compare match event can be set up for the future even when the time base will first overflow and then reach the compare value. Please note, that for a correct behaviour of this signed compare, the new compare value must not be specified larger/smaller than half of the range of the total time base value (0x7FFFFF).

In SOMC mode, the two compare units CCUx can be used in combination to each other. When used in combination, the trigger lines TRIG_CCU 0 and TRIG_CCU 1 can be used to enable/disable the other compare unit on a match event. Please refer to section 0 for further details.

The Signal Output Unit (SOU) generates the output signal for each ATOM channel. This output signal level depends on the ATOM channel mode and on the SL bit of the ATOM[i]_CH[x]_CTRL register in combination with the two control bits. This two control bits ACB( 1 ) and ACB( 0 ) can either be received via CPU in the ACB register field of the ATOM[i]_CH[x]_CTRL register or via ARU in the ACBI bit field of the ATOM[i]_CH[x]_STAT register.

The SL bit in the ATOM[i]_CH[x]_CTRL register defines in all modes the initial signal level after the channel is enabled by the software. The default signal level when the channel is disabled is ‘ 0 ’.

In SOMI and SOMC mode the output signal level depends on the SL, ACB 0 and ACB 1 bits. In SOMP mode the output signal level depends on the two trigger signals TRIG_CCU 0 and TRIG_CCU 1 since theses two triggers define the PWM timing characteristics and the SL bit defines the level of the duty cycle. In SOMS mode the output signal level is defined by the bit pattern that has to be shifted out by the ATOM channel. The bit pattern is located inside the CM 1 register.

The ARU Communication Interface (ACI) subunit is responsible for requesting data routed through ARU to the ATOM channel in SOMI, SOMP and SOMS modes, and additionally for providing data to the ARU in SOMC mode. In SOMC mode the ACI shadow registers have a different behaviour and are used as output buffer registers for data send to ARU.

ARU Communication Interface

The ATOM channels have an ARU Communication Interface (ACI) subunit. This subunit is responsible for data exchange from and to the ARU. This is done with the two implemented registers SR 0 , SR 1 , and the ACBI and ACBO bit fields that are part of the ATOM[i]_CH[x]_STAT register. The ACI architecture is shown in FIG. 34 .

ACI Architecture Overview

See FIG. 34 .

Incoming ARU data (53 bit width signal ARU_CHx_IN) is split into three parts by the ACI and communicated to the ATOM channel registers.

In SOMI, SOMP and SOMS modes incoming ARU data ARU_CHx_IN is split in a way that the lower 24 bits of the ARU data ( 23 down to 0 ) are stored in the SR 0 register, the bits 47 down to 24 are stored in the SR 1 register and the bits 52 down to 48 (CTRL_BIT) are stored in the ACBI bit field the register ATOM[i]_CH[x]_STAT. The ATOM channel has to ensure, that in a case when the channel operation registers CM 0 and CM 1 are updated with the SR 0 and SR 1 register content and an ARU transfer to these shadow registers happens in parallel that either the old data in both shadow registers is transferred into the operation registers or both new values from the ARU are transferred.

In SOMC mode incoming ARU data ARU_CHx_IN is written directly to the ATOM channel operation register in the way that the lower 24 bits (23 down to 0) are written to CM 0 , and the bits 47 down to 24 are written to register CM 1 . The bits 52 down to 48 are stored in the ACBI bit field of the ATOM[i]_CH[x]_STAT register and control the behaviour of the compare units and the output signal of the ATOM channel.

In SOMC mode the SR 0 and SR 1 registers serve as capture registers for the time stamps coming from TBU whenever a compare match event is signalled by the CCU 0 and/or CCU 1 subunits via the CAP signal line. These two time stamps are then provided together with actual ATOM channel status information located in the ACBO bit field to the ARU at the dedicated ARU write address of the ATOM channel. The encoding of the ARU control bits in the different ATOM operation modes is described in more detail in the following chapters.

ATOM Channel Modes

As described above, each ATOM channel can operate independently from each other in one of four dedicated output modes:

ATOM Signal Output Mode Immediate (SOMI) ATOM Signal Output Mode Compare (SOMC) ATOM Signal Output Mode PWM (SOMP) ATOM Signal Output Mode Serial (SOMS)

The Signal Output Mode PWM (SOMP) is principally the same like the output mode for the TOM sub module except the bit reverse mode which is not included in the ATOM. In addition, it is possible to reload the shadow registers over the ARU without the need of a CPU interaction. The three other modes provide additional functionality for signal output control. All operation modes are described in more detail in the following sections.

ATOM Signal Output Mode Immediate (SOMI)

In ATOM Signal Output Mode Immediate (SOMI), the ATOM channel generates output signals on the ATOM[i]_CH[x]_OUT output port immediate after update of the bit ACBI( 0 ) of register ATOM[i]_CH[x]_STAT via the associated ARU data input stream (bits 52 down to 48 of ARU_CHx_IN) received at the ACI subunit. The remaining 48 ARU bits (47 down to 0) have no meaning in this mode.

The initial ATOM channel port pin ATOM[i]_CH[x]_OUT signal level has to be specified by the SL bit field (OPD= 0 defined in this mode, see FIG. 33 ) of the ATOM[i]_CH[x]_CTRL register when OUTEN_CTRL register bit field OUTEN_CTRLx is disabled (see section 0 ) for details.

In SOMI mode only bit 48 of signal ARU_CHx_IN ARU is meaningful for the output behaviour of the channel. The output behaviour depends on the SL bit of register ATOM[i]_CH[x]_CTRL and the ACBI( 0 ) bit of the ATOM[i]_CH[x]_STAT register:

The signal level bit ACBI( 0 ) is transferred to the SOU subunit of the ATOM and made visible at the output port according to the table above immediately after the data was received by the ACI. This can introduce a jitter on the output signal since the ARU channels are served in a time multiplexed fashion.

Register ATOM[i]_CH[x]_CTRL in SOMI mode (x: 0 . . . 7) Address Offset: 0x0080 + x * 0x0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Reserved Not used Reserved Not used Reserved Not used Reserved Not used Mode R R R R R R R R Initial 0 0 0 0 0 0 0 0 Value Initial Value: 0x0000_0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Reserved Not used SL Reserved Not used ARU_EN Not used MODE Mode R R RW R R RW R RW Initial 0 0 0 0 0 0 0 0 Value Bit 1:0 MODE: ATOM channel mode select. 00: ATOM Signal Output Mode Immediate (SOMI) Bit 2 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 3 ARU_EN: ARU Input stream enable 0 = ARU Input stream disabled 1 = ARU Input stream enabled Bit 8:4 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 10:9 Reserved: Read as zero, should be written as zero (OPD = 0) Bit 11 SL: Initial signal level after channel is enabled 0 = Low signal level 1 = High signal level Note: After reset and if channel is disabled, the register SOUR is set to the inverse reset value of bit SL (i.e. ‘1’). If the channel is disabled or the output is disabled, the output ATOM_OUT[x] is set to inverse value of SL. Bit 14:12 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 15 Reserved: Read as zero, should be written as zero. Bit 16 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 19:17 Reserved: Read as zero, should be written as zero Bit 20 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 23:21 Reserved: Read as zero, should be written as zero Bit 24 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 25 Reserved: Read as zero, should be written as zero Bit 26 Not used: Not used in this mode Note: Read as zero, should be written as zero Bit 31:27 Reserved: Read as zero, should be written as zero

ATOM Signal Output Mode Compare (SOMC)

In ATOM Signal Output Mode Compare (SOMC) the output action is performed in dependence of the comparison between input values located in CM 0 and/or CM 1 registers and the two (three) time base values TBU_TS 0 or TBU_TS 1 (or TBU_TS 2 ) provided by the TBU. For a description of the time base generation please refer to the TBU specification in chapter 1 . It is configurable, which of the two (three) time bases is to be compared with one or both values in CM 0 and CM 1 .

The behaviour of the two compare units CCU 0 and CCU 1 can be controlled either with the bits 4 down to 2 of bit field ACB inside the ATOM[i]_CH[x]_CTRL register, when the ARU connection is disabled or with the ACBI bit field of the ATOM[i]_CH[x]_STAT register, when the ARU is enabled.

If three time bases exist for the GTM-IP there must be a preselection between TBU_TS 1 and TBU_TS 2 for the ATOM channel. This can be done with TB 12 _SEL bit in the ATOM[i]_CH[x]_CTRL register.

The time base comparison can be done on a greater/equal or less/equal compare according to the CMP_CTRL flag. This flag is part of the ATOM[i]_CH[x]_CTRL register.

In principal, there are two input possibilities to provide the compare values to the ATOM channel. The first possible solution is to write the compare values over the AEI bus interface. The second possibility is to reload the parameters via ARU. For this the ACI subunit has to be enabled with the ARU_EN bit in the ATOM[i]_CH[x]_CTRL register.

The behaviour of an ATOM channel in SOMC mode is visualized in FIG. 35 .

SOMC State Diagram

See FIG. 35 .

If ARU access is enabled, data received via the ARU is continuously transferred to the register CM 0 and CM 1 and the bit field ACBI of register ATOM[i]_CH[x]_STAT as long as no specified compare match event occurs. The ATOM channel continuously receives data via the ARU and updates the register CM 0 and CM 1 until the specified compare match event happens.

On a compare match event the shadow register SR 0 and SR 1 are used to capture the TBU time stamp values. SR 0 always holds TBU_TS 0 and SR 1 either holds TBU_TS 1 or TBU_TS 2 dependent on the TB 12 _SEL bit in the ATOM[i]_CH[x]_CTRL register.

The output of the ATOM channel is set on a compare match event depending on the bit field ACBI in register ATOM[i]_CH[x]_STAT if ARU is enabled or depending on the ABC bit field in register ATOM[i]_CH[x]_CTRL if ARU is disabled.

After a compare match event the update of the register CM 0 , CM 1 and the ACBI bit field in register ATOM[i]_CH[x]_STAT as well as the bit field ACB in register ATOM[i]_CH[x]_CTRL is blocked until the data captured in the shadow registers SR 0 SR 1 is transmitted successfully via the ARU to another module or the CPU reads out at least one of the register SR 0 or SR 1 .

If the register SR 0 and SR 1 holding the captured TBU time stamp values are read by either the ARU or the CPU, the next write access to or update of the register CM 0 or CM 1 via ARU or the CPU enables the new compare match check.

The captured content in SR 0 and SR 1 is made available together with the compare result in the ACBO bit field of the ATOM[i]_CH[x]_STAT register. Bit three ( 3 ) of the ACBO bit field is set on a compare match event in CCU 0 , bit four ( 4 ) of the ACBO bit field is set on a compare match event in CCU 1 . The signal D_VAL indicates valid data for the ARU. Additionally, an ATOM capture interrupt ACAP_IRQ is raised.

The CPU can check at any time if the ATOM channel has received valid data from the ARU and waits for a compare event to happen. This is signalled by the DV bit inside the ATOM[i]_CH[x]_STAT register.

Although the ATOM channel may be controlled by data received via the ARU, the CPU is able to request at any time a late update of the compare register. This can be initiated by setting the WR_REQ bit inside the ATOM[i]_CH[x]_CTRL register. By doing this, the ATOM will request no further data from ARU (if ARU access was enabled). The channel will in any case continue to compare against the values stored inside the compare registers (if bit DV was set). The CPU can now update the new compare values until the compare event happens by writing to the shadow registers, and force the ATOM channel to update the compare registers by writing to the force update register bits in the AGC register.

If the WR_REQ bit is set and a compare match event happens, any further access to the shadow registers SR 0 , SR 1 or the compare register CM 0 , CM 1 is blocked and the force update of this channel is blocked. In addition, the WRF bit is set in the ATOM[i]_CH[x]_STAT register. Thus, the CPU can determine that the late update failed by reading the WRF bit.

The WR_REQ bit and the DV bit will be reset on a compare match event.

A blocked force update mechanism will be enabled again after a read access to the register SR 0 or SR 1 by either the ARU or the CPU.

When the ARU_EN bit is reset, the (one) two compare values for CM 0 and/or CM 1 have to be provided by the CPU. The ATOM channel waits for the compare match event and then disables the channel. The channel has to be enabled again by the CPU when new compare values were provided.

When CCU 0 and CCU 1 is used for comparison it is possible to generate very small spikes on the output pin by loading CM 0 and CM 1 with two time stamp values for TBU_TS 0 , TBU_TS 1 or TBU_TS 2 close together. The output pin will then be set or reset dependent on the SL bit and the specified ACB( 0 ) and ACB( 1 ) bits in the ACB bit field of the ATOM[i]_CH[x]_CTRL register or the ACBI bit field of the ATOM[i]_CH[x]_STAT register on the first match event and the output will toggle on the second compare event.

It is important to note, that the bigger (smaller) time stamp has to be loaded into the CM 1 register, since the CCU 0 will enable the CCU 1 once it has reached its comparison time stamp. The order of the comparison time stamps depends on the defined greater/equal or less/equal comparison of the CCUx units.

The CCUx trigger signals TRIG_CCU 0 and TRIG_CCU 1 always create edges, dependent on the predefined signal level in SL bit when both CCUx units are used. When only CCU 0 is used then the output is set to the specified signal level defined with the SL bit in combination with the ACBI( 0 ) and ACBI( 1 ) bits of the ARU control bits on a compare match between the selected time base and CM 0 .

When configured in SOMC mode, the channel port pin has to be initialized to an initial signal level. This initial level after enabling the ATOM channel is determined by the SL bit field in the ATOM[i]_CH[x]_CTRL register.

If the channel receives its compare values via ARU the signal output level on compare match events is configurable with the ACBI( 0 ) and ACBI( 1 ) bits in combination with the SL bit setting:

The capture/compare units can be controlled with the three ACBI bits ACBI( 2 ), ACBI( 3 ) and ACBI( 4 ). The meaning these bits is shown in the following table:

The behaviour of the ACB 42 bit combinations ‘000’ and ‘001’ is described in more detail in table 0.

ATOM CCUx Serve First Definition

It is important to note that the bit combination “111” for the ACBI( 4 ), ACBI( 3 ) and ACBI( 2 ) bits forces the channel to request new compare values from another destination read address defined in the ATOM_RDADDR 1 bit field of the ATOM[i]_CH[x]_RDADDR register. After data was successfully received and the compare event occurred the ATOM channel switches back to ATOM_RDADDR 0 to receive the next data from there.

In SOMC mode the channel is always disabled after the compare match event occurred when the ARU_EN bit is disabled (compare values are reloaded via CPU) in the ATOM[i]_CH[x]_CTRL register. When the ARU_EN bit is set, the ATOM channel first waits for the compare event to happen, then disables the CCUx units, provides the captured time stamps to the ARU and request new compare values via ARU in parallel. Thus, a compare event happens only once and when no new data is provided via ARU or CPU the ATOM channel will not create any further signal at the output port.

In addition to the two time stamps, the ATOM channel provides the result of the compare match event in the ACBO( 4 ) and ACBO( 3 ) bits of the ATOM[i]_CH[x]_STAT register. These bits are also transferred via ARU. The meaning of the bits is shown in the following table:

ATOM Signal Output Mode PWM (SOMP)

In ATOM Signal Output Mode PWM (SOMP) the ATOM sub module channel is able to generate complex PWM signals with different duty cycles and periods. Duty cycles and periods can be changed synchronously and asynchronously. Synchronous change of the duty cycle and/or period means that the duty cycle or period duration changes after the end of the preceding period or duty cycle. An asynchronous change of period and/or duty cycle means that the duration changes during the actual running PWM period.

The signal level of the pulse generated inside the period can be configured inside the channel control register (SL bit of ATOM[i]_CH[x]_CTRL register). The initial signal output level for the channel is the reverse pulse level defined by the SL bit (OPD=1 defined in this mode, see FIG. 33 ). FIG. 36 clarifies this behaviour.

PWM Output Behaviour with Respect to the SL Bit in the ATOM[i]_CH[x]_CTRL Register

See FIG. 36 .

On an asynchronous update, it is guaranteed, that no spike occurs at the output port of the channel to a too late update of the operation registers. The behaviour of the output signal due to the different possibilities of an asynchronous update during a PWM period is shown in FIG. 37 .

PWM Output Behaviour in Case of an Asynchronous Update of the Duty Cycle

See FIG. 37 .

The duration of the pulse high or low time and period is measured with the counter in subunit CCU 0 . The trigger of the counter is one of the eight CMU clock signals configurable in the channel control register ATOM[i]_CH[x]_CTRL. The register CM 0 holds the duration of the period and the register CM 1 holds the duration of the duty cycle in clock ticks of the selected CMU clock.

In case of a synchronous update mechanism, the values of the registers CM 0 and CM 1 are updated with the content of the shadow registers SR 0 and SR 1 after the counter value CN 0 reaches the compare value in register CM 0 or the channel receives an external update trigger via the FUPD(x) signal.

In addition, the clock source for the counter can be changed synchronously at the end of a period. This is done by using the AC 2 to AC 0 bits in the ATOM[i]_CH[x]_CTRL as shadow registers for the next CMU clock source. Please note, that due to this feature the PWM clock source has to be defined twice inside the ATOM[i]_CH[x]_CTRL register before the channel is enabled in SOMP mode.

For the synchronous update mechanism the generation of a complex PWM output waveform is possible without CPU interaction by reloading the shadow registers SR 0 , SR 1 and the ACBI bit field over the ACI subunit from the ARU, while the ATOM channel operates on the CM 0 and CM 1 registers.

This internal update mechanism is established, when the old PWM period ends. The shadow registers are loaded into the operation registers, the counter register is reset, the new clock source according to the AC 42 or ACBI( 4 ), ACBI( 3 ) and ACBI( 2 ) bits is selected and the new PWM generation starts. In parallel, the ATOM channel issues a read request to the ARU to reload the shadow registers with new values while the ATOM channel operates on the operation registers. To guarantee the reloading, the PWM period must not be smaller than the worst case ARU round trip time and source for the PWM characteristic must provide the new data within this time. Otherwise, the old PWM values are used from the shadow registers.

When updated over the ARU the user has to ensure that the new period duration is located in the lower (bits 23 to 0 ) and the duty cycle duration is located in the upper (bits 47 to 24 ) ARU data word and the new clock source is specified in the ARU control bits 52 to 50 .

This pipelined data stream character is shown in FIG. 38 .

ARU Data Input Stream Pipeline Structure for SOMP Mode

See FIG. 38 .

When an ARU transfer is in progress which means the ARU_RREQ is served by the ARU, the ACI locks the update mechanism of CM 0 , CM 1 and CLK_SRC until the read request has finished. The CCU 0 and CCU 1 operate on the old values when the update mechanism is locked.

The shadow registers SR 0 and SR 1 can also be updated over the AEI bus interface. When updated via the AEI bus the CM 0 and CM 1 update mechanism has to be locked via the AGC_GLB_CTRL register with the UPENx signal in the AGC subunit. To select the new clock source in this case, the CPU has to write ACB 42 bit field of the ATOM[i]_CH[x]_CTRL register.

For an asynchronous update of the duty cycle and/or period the new values must be written directly into the compare registers CM 0 and/or CM 1 while the counter CN 0 continues counting. This update can be done only via the AEI bus interface immediately by the CPU or by the FUPD(x) trigger signal triggered from the AGC global trigger logic. Values received through the ARU interface are never loaded asynchronously into the operation registers CM 0 and CM 1 . Therefore, the ATOM channel can generate a PWM signal on the output port pin ATOM[i]_CH[x]_OUT on behalf of the content of the CM 0 and CM 1 registers, while it receives new PWM values via the ARU interface ACI in its shadow registers.

On a compare match of CN 0 and CM 0 or CM 1 the output signal level of ATOM[i]_CH[x]_OUT is toggled according to the signal level output bit SL in the ATOM[i]_CH[x]_CTRL register.

Thus, the duty cycle output level can be changed during runtime by writing the new duty cycle level into the SL bit of the channel configuration register. The new signal level becomes active for the next trigger CCU_TRIGx (since bit SL is written).

Since the ATOM[i]_CH[x]_OUT signal level is defined as the reverse duty cycle output level when the ATOM channel is enabled, a PWM period can be shifted earlier by writing an initial offset value to CN 0 register. By doing this, the ATOM channel first counts until CN 0 reaches CM 0 and then it toggles the output signal at ATOM[i]_CH[x]_OUT.

SOMP One-Shot Mode

The ATOM channel can operate in One-shot mode when the OSM bit is set in the channel control register. One-shot mode means that a single pulse with the pulse level defined in bit SL is generated on the output line (OPD= 1 defined in this mode, see FIG. 33 ).

First the channel has to be enabled by setting the corresponding ENDIS_STAT value.

In One-shot mode the counter CN 0 will not be incremented once the channel is enabled.

A write access to the register CN 0 triggers the start of pulse generation (i.e. the increment of the counter register CN 0 ).

If the counter CN 0 is reset from CM 0 back to zero, the first edge at ATOM[i]_CH[x]_OUT is generated.

The second edge is generated if CN 0 is greater or equal than CM 1 (i.e. CN 0 was incremented until it has reached CM 1 or CN 0 is greater than CM 1 after an update of CM 1 ).

If the counter CN 0 has reached the value of CM 0 a second time, the counter stops. FIG. 39 clarifies the pulse generation in SOMP One-shot mode.

PWM Output with Respect to Configuration Bit SL in One-Shot Mode

See FIG. 39 .

Further output of single pulses can be started by a write access to register CN 0 .

ATOM Signal Output Mode Serial (SOMS)

In ATOM Signal Output Mode Serial (SOMS) the ATOM channel acts as a serial output shift register where the content of the CM 1 register in the CCU 1 unit is shifted out whenever the unit is triggered by the selected CMU_CLK input clock signal. The shift direction is configurable with the ACB( 0 ) bit inside the ATOM[i]_CH[x]_CTRL register when ARU is disabled and the ACBI( 0 ) bit inside the ATOM[i]_CH[x]_STAT register when ARU is enabled.

The data inside the CM 1 register has to be aligned according to the selected shift direction in the ACB( 0 )(ACBI( 0 ) bit. This means that when a right shift is selected, that the data word has to be aligned to bit 0 of the CM 1 register and when a left shift is selected, that the data has to be aligned to bit 23 of the CM 1 register.

In SOMS mode CCU 0 runs in counter/compare mode and counts the number of bits shifted out so far. The total number of bits that should be shifted is defined as CM 0 + 1 .

If the ARU_EN bit is set and the contents of the CM 0 register equals the counter CN 0 , the CM 0 and CM 1 registers are reloaded with the SR 0 and SR 1 content and new values are requested from the ARU. If the update of the shadow registers does not happen before CN 0 reaches CM 0 the old values of SR 0 and SR 1 is used to reload the operation registers.

It is recommended to configure the ATOM channel in One-shot mode when the ARU_EN bit is not set, since the ATOM channel would reload new values from the shadow registers when CN 0 reaches CM 0 .

Otherwise, the ATOM channel reloads the operation registers from the shadow registers when the UPEN bit is set for the channel. Shifting can be stopped by disabling the UPEN bit.

If the ATOM channel is configured in One-shot mode and the ARU_EN bit is not set the ATOM channel stops shifting when CN 0 reaches CM 0 . No update of CM 0 and CM 1 is performed in this configuration.

In the case of the One-shot mode and ARU disabled, the shifting of the channel can be restarted again by writing a zero ( 0 ) to the CN 0 register again. Please note, that the CN 0 register should be written with a zero since the CN 0 register counts the number of bits shifted out be the ATOM channel.

When the serial data to be shifted is provided via ARU the number of bits that should be shifted has to be defined in the lower 24 bits of the ARU word ( 23 to 0 ) and the data that is to be shifted has to be defined in the ARU bits 47 to 24 aligned according to the shift direction. This shift direction has to be defined in the ARU word bit 48 (SL 0 bit).

ATOM Interrupt Signals

The following table describes ATOM interrupt signals:

Signal Description CCU0TCx_IRQ CCU0 Trigger condition interrupt for channel x CCU1TCx_IRQ CCU1 Trigger condition interrupt for channel x ACAPx_IRQ ATOM Capture event occurred in SOMS mode

ATOM Register Overview

The following table shows a conclusion of ATOM register address offset and initial values.

Details in Register name Description Section ATOM[i]_AGC_GLB_CTRL AGC Global control register 0 ATOM[i]_AGC_ENDIS_CTRL AGC0 Enable/disable control 0 register ATOM[i]_AGC_ENDIS_STAT AGC Enable/disable status 0 register (represents status of ATOM channels) ATOM[i]_AGC_ACT_TB AGC Action time base register 0 ATOM[i]_AGC_OUTEN_CTRL AGC Output enable control 0 register ATOM[i]_AGC_OUTEN_STAT AGC Output enable status 0 register ATOM[i]_AGC_FUPD_CTRL AGC Force update control 0 register ATOM[i]_AGC_INT_TRIG AGC Internal trigger control 0 register ATOM[i]_CH[x]_CTRL ATOM Channel x control register 0 (x = 0 . . . 7) ATOM[i]_CH[x]_STAT ATOM Channel x status register 0 (x = 0 . . . 7) ATOM[i]_CH[x]_RDADDR ATOM Channel x ARU read 0 address register (x = 0 . . . 7) ATOM[i]_CH[x]_CN0 ATOM Channel x CCU0 counter 0 register (x = 0 . . . 7) ATOM[i]_CH[x]_CM0 ATOM Channel x CCU0 compare 0 register (x = 0 . . . 7) ATOM[i]_CH[x]_SR0 ATOM Channel x CCU0 compare 0 shadow register (x = 0 . . . 7) ATOM[i]_CH[x]_CM1 ATOM Channel x CCU1 compare 0 register (x = 0 . . . 7) ATOM[i]_CH[x]_SR1 ATOM Channel x CCU1 compare 0 shadow register (x = 0 . . . 7) ATOM[i]_CH[x]_IRQ_NOTIFY ATOM channel x interrupt 0 notification register (x = 0 . . . 7) ATOM[i]_CH[x]_IRQ_EN ATOM channel x interrupt enable 0 register (x = 0 . . . 7) ATOM[i]_CH[x]_IRQ_FORCINT ATOM channel x software 0 interrupt generation (x = 0 . . . 7) ATOM[i]_CH[x]_IRQ_MODE IRQ mode configuration register 0 (x = 0 . . . 7)

ATOM Register Description

Multi Channel Sequencer (MCS)

Overview

The Multi Channel Sequencer (MCS) sub module is a generic data processing module that is connected to the ARU.

One of its major applications is to calculate complex output sequences that may depend on the time base values of the TBU and are processed in combination with the ATOM sub module.

Other applications can use the MCS sub module to perform extended data processing of input data resulting from the TIM sub module that are provided to the CPU (e.g. using the PSM sub module).

Moreover, some applications may process data provided by the CPU within the MCS sub module, and the calculated results are sent to the outputs using the ATOM sub modules.

Architecture

FIG. 40 gives an overview of the MCS architecture.

MCS Architecture

See FIG. 40 .

The MCS sub module mainly embeds a single data path with four pipeline stages, consisting of a simple Arithmetic Logic Unit (ALU), several decoders, and a connection to two RAM pages located outside of the MCS sub module.

The data path of the MCS is shared by eight so called MCS-channels, whereas each MCS-channel executes a dedicated micro-program that is stored inside the RAM pages connected to the MCS sub module.

Both RAM pages may contain arbitrary sized code and data sections that are accessible by all MCS-channels and the CPU via AEI.

The MCS sub module supports a memory layout of up to 2 14 memory locations each 32 bit wide leading to a maximum address range from 0 to 2 16 −4.

This address space of the MCS is divided into two seamless memory pages. Memory page 0 begins from address 0 ranges to address MP 0 - 4 and memory page 1 ranges from MP 0 to MP 1 - 4 .

The parameters MP 0 and MP 1 are defined externally by the memory configuration sub module MCFG of section 0 .

An MCS-channel can also be considered as an individual task of a processor that is scheduled at a specific point in time.

A more detailed description of the scheduling can be found in section 0 .

Moreover, each MCS-channel has a dedicated ARU interface for communication with other ARU connected modules, an Instruction Register (IR), a Program Counter Register (PC), a Status Register (STA), an ARU Control Bit Register (ACB), and a Register Bank with eight 24 bit general purpose registers (R 0 , R 1 , . . . R 7 ).

All the registers, mentioned above, are only visible within its dedicated MCS-channel and thus the MCS-channels cannot exchange data using registers.

The only exception are the trigger registers (STRG and CTRG) that can be accessed by each MCS sub module and the CPU in order to trigger several MCS-channels located in the same sub module.

Whenever data has to be exchanged between different MCS-channels or the CPU, the connected RAM pages, which are accessible by all MCS-channels and the CPU, can be used.

However, since the data registers are writable by the CPU, an MCS channel may also exchange data with the CPU using its data registers.

The main actions of the different pipeline stages are as follows:

Pipeline stage 0 performs a setup of address, input data, and control signals for the next RAM access of a specific MCS-channel.

The actual RAM access of a specific MCS-channel is executed in pipeline stage 1 .

The RAM priority decoder arbitrates RAM accesses that are requested by the CPU via AEI and by the active MCS-channel of pipeline stage 1 .

If both, CPU and an MCS-channel request a memory access to the same memory page the MCS-channel is prioritized.

Pipeline stage 2 performs pre-decoding of instruction and data resulting from the RAM.

Finally, in pipeline stage 3 the current instruction is executed.

Scheduling

The MCS sub module provides two different scheduling schemes: round-robin schedule and accelerated schedule.

The scheduling scheme can be selected by the SCHED bit in the global MCS[i]_CTRL register.

The round-robin order scheduling assigns all MCS-channels an equal amount of time slices.

In addition, the scheduler also assigns one time slice to the CPU, in order to guarantee at least one memory access by the CPU within each round-trip cycle.

FIG. 41 shows the round-robin scheduling with 8 MCS-channels (C 0 to C 7 ) that are scheduled together with a single CPU access.

Scheduling

See FIG. 41 .

The figure also shows which MCS-channel is activated in specific pipeline stage at a specific point in time.

The execution time of an MCS-channel in a specific pipeline stage is always one clock cycle.

The index t marks all instruction parts of the corresponding MCS-channels belonging to the same round-trip cycle.

Consequently, a single cycle instruction of an MCS-channel requires an effective execution time of 9 clock cycles, ignoring the four clock cycles of pipeline latency.

In order to improve memory bandwidth between CPU and MCS memory, the time slices of any suspended MCS-channel is also granted to the CPU.

An MCS-channel can be suspended due to the following reasons:

An MCS-channel is executing a blocking read or write request to an ARU connected sub module. An MCS-channel waits on a trigger event generated by another MCS-channel (initiated by MCS instruction WTRG). An MCS-channel is disabled.

The round-robin scheduling leads to a deterministic round trip time for the whole sub module, however it may waste clock cycles by scheduling MCS-channels that are not able to run at a specific point in time assuming that there is no high CPU bandwidth required.

In order to improve computational performance of the MCS, the round-robin scheduling can be improved in the accelerated scheduling mode, whenever one or more MCS-channels are suspended.

If the accelerated scheduling scheme is selected, the scheduler acts as follows:

Whenever the scheduler cannot schedule a specific MCS-channel due to its suspended state (or it is already scheduled in stage 0 , 1 , or 2 ), the scheduler is selecting the next non-suspended MCS-channel that would follow if round-robin scheduling is continued.

Considering the example of FIG. 41 in conjunction with the accelerated scheduling scheme, a single cycle instruction of an MCS-channel requires an effective execution time between four and 9 clock cycles, depending on the number of suspended MCS-channels.

In summary, the round-robin scheduling mode grants time slices of suspended MCS-channels to the CPU and the accelerated scheduling mode grants time slices of suspended MCS-channels to non-suspended MCS-channels.

Instruction Set

This section describes the entire instruction set of the MCS sub module.

After the introduction of the different instruction formats in section 0 , the individual instructions are described in sections 0 to 0 .

In general, each instruction is 32 bit wide but the duration of each instruction varies between several instruction cycles. An instruction cycle is defined as the time in SYS_CLK clock cycles that rest between two consecutive instructions of a channel. As already described in section 0 , the number of required clock cycles for a single instruction cycle can vary in the range of four to 9 clock cycles, depending on the number suspended MCS-channels, when the accelerated scheduling scheme is selected inside the MCS[i]_CTRL register.

In the round robin scheduling scheme, each instruction takes exactly 9 clock cycles. Before the instruction formats and the actual instructions are described, some commonly used terms, abbreviations and expressions are introduced:

REG: The general purpose register set REG={R 0 , R 1 , R, . . . , R 7 } identifies the number of allocated general purpose registers of an MCS-channel. XREG: The extended register set XREG=REG∪{STA, STRG, CTRG, ACB} extends the set REG by the Status Register (STA), the Set Trigger Bit Register (STRG), the Clear Trigger Bit Register (CTRG) and the ARU control register ACB. OPER: The operation set OPER=XREG∪{TBU_TS 0 , TBU_TS 1 , TBU_TS 2 } extends the extended register set XREG by the time bases TBU_TS 0 , TBU_TS 1 , and TBU_TS 2 . LIT 4 : The set LIT 4 ={ 0 , 1 , . . . , 15 } is an unsigned 4 bit literal. LIT 16 : The set LIT 16 ={ 0 , 1 , . . . , 2 16 −1} is an unsigned 16 bit literal. LIT 24 : The set LIT 24 ={ 0 , 1 , . . . 2 24 −1} is an unsigned 24 bit literal. BIT SELECTION: The expression VAR[i] represents the i-th bit of a variable VAR. BIT RANGE SELECTION: The expression VAR[m:n] represents the bit slice of variable VAR that is ranging from bit n to bit m. MEMORY ADRESSING: The expression MEM(X) represents the 32 bit value at address X of the memory.

Address X ranges between 0 and 2 16 −4, whereas X must be an integral multiple of 4 .

The expression MEM(X)[m:n] represents the bit slice ranging from bit n to m of the 32 bit word at memory location X.

ARU ADRESSING: In the case of ARU reading, the expression ARU(X) represents the 53 bit ARU word of ARU channel at address X.

The read address X ranges between 0 and 2 9 −1.

In the case of ARU writing, the expression ARU(X) represents a 53 bit ARU word that is written to an ARU channel indexed by the index X.

The index X selects a single ARU write channel from the pool of the MCS sub module's allocated ARU write channels.

An MCS sub module has 24 ARU write channels, indexed by values 0 to 23 .

The expression ARU(X)[m:n] represents the bit slice ranging from bit n to m of the 53 bit ARU word.

Instruction Format

The first instruction format, called literal instruction format, embeds a primary 4 bit opcode OPC 0 , a 24 bit literal value CεLIT 24 , and a 4 bit value A, which may be an element of set REG, XREG or OPER, depending on the actual instruction.

The following table shows the bit alignment of the literal instruction format.

Literal Instruction Format

The literal instruction format is primarily used for instructions that are accessing a 24 bit literal and a single 24 bit register as operands.

In the following subsections the binary codes of a 24 bit literal instruction is defined as “xxxxaaaacccccccccccccccccccccccc”, whereas the digits ‘x’ encode the field OPC 0 , the digits ‘a’ encode the operand field A, and the digits ‘c’ encode the 24 bit literal field C.

If an instruction ignores several bits of field, the bits are defined as ‘−’ in its code. The second instruction format, called double operand instruction format, embeds a 4 bit primary opcode OPC 0 , a 4 bit secondary opcode OPC 1 , an 16 bit literal CεLIT 16 and two 4 bit values A and B, which may be an element of set REG, XREG, OPER, or LIT 4 depending on the actual instruction.

The following table shows the bit alignment of the double operand instruction format.

Double Operand Instruction Format

The double operand instruction format is primarily used for instructions that are accessing two operands stored in the 24 bit registers.

In the following subsections the binary codes of a 16 bit literal instruction is defined as “xxxxaaaabbbbyyyycccccccccccccccc”, whereas the digits ‘x’ encode the bit field OPC 0 , ‘y’ the digits of field OPC 2 , the digits ‘a’ encode the operand field A, the digits ‘b’ the operand field B, and the digits ‘c’ encode the 16 bit literal field C.

If an instruction ignores several bits of field, the bits are defined as ‘−’ in its code.

Data Transfer Instructions

MOVL Instruction

Syntax: MOVL A, C

Operation: A←C

Status: Z

Duration: 1 instruction cycle

Code: 0001aaaacccccccccccccccccccccccc

Description: Transfer literal value C (CεLIT 24 ) to register A (AεXREG).

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

MOV Instruction

Syntax: MOV A, B

Operation: A←B

Status: Z

Duration: 1 instruction cycle

Code: 1010aaaabbbb0000 - - -

Description: Transfer value B (BεOPER) to register A (AεXREG).

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

MRD Instruction

Syntax: MRD A, C

Operation: A←MEM(C)[23:0]

Status: Z

Duration: 2 instruction cycles

Code: 1010aaaa - - - 0001cccccccccccccccc

Description: Transfer 24 bit value of memory at address C (CεLIT 16 ) to register A (AεXREG).

The 24 bit value is received from the lower significant bits (bit 0 to 23 ) of the memory location.

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

MWR Instruction

Syntax: MWR A, C

Operation: MEM(C)[23:0]←A; MEM(C)[28:24]←ACB; MEM(C)[31:29]←0

Status: —

Duration: 2 instruction cycles

Code: 1010aaaa - - - 0010cccccccccccccccc

Description: Transfer 24 bit value of register A (AεOPER) together with the five ACB bits from register ACB to memory at address C (CεLIT 16 ).

The 24 bit value of register A is stored in the lower significant bits (bit 0 to 23 ) of the memory location and the five ACB bits are stored in bits 24 to 28 .

The bits 29 to 31 of the memory location are cleared.

The program counter PC is incremented by the value 4.

MWR24 Instruction

Syntax: MWR24 A, C

Operation: MEM(C)[23:0]←A

Status: —

Duration: 2 instruction cycles

Code: 1010aaaa - - - 0111cccccccccccccccc

Description: Transfer 24 bit value of register A (AεOPER) to memory at address C (CεLIT 16 ).

The 24 bit value of register A is stored in the lower significant bits (bit 0 to 23 ) of the memory location and the bits 24 to 31 are left unchanged. The program counter PC is incremented by the value 4.

MWR16 Instruction

Syntax: MWR16 A, C

Operation: MEM(C)[15:0]→A[15:0]

Status: —

Duration: 2 instruction cycles

Code: 1010aaaa - - - 1001cccccccccccccccc

Description: Transfer 16 bit value of register A (AεOPER) to memory at address C (CεLIT 16 ).

The lower significant 16 bits of register A is stored in the lower significant bits (bit 0 to 15 ) of the memory location and the bits 16 to 31 are left unchanged.

The program counter PC is incremented by the value 4 .

MRDI Instruction

Syntax: MRDI A, B

Operation: A←MEM(B[15:0])[23:0]

Status: Z

Duration: 2 instruction cycles

Code: 1010aaaabbbb0011 - -

Description: Transfer 24 bit value of memory to register A (AεXREG) using indirect addressing.

The memory location where to read from is defined by the bits 0 to 15 of register B (BεREG).

The 24 bit value is received from the lower significant bits (bit 0 to 23 ) of the memory location.

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

MWRI Instruction

Syntax: MWRI A, B

Operation: MEM(B[15:0])[23:0]←A; MEM(B[15:0])[28:24]←ACB; MEM(B[15:0])[31:29]←0

Status: —

Duration: 2 instruction cycles

Code: 1010aaaabbbb0100 - -

Description: Transfer 24 bit value of A (AεOPER) together with the five ACB bits from register ACB to memory using indirect addressing.

The memory location where to write to is defined by the bits 0 to 15 of register B (BεREG).

The 24 bit value is stored in the lower significant bits (bit 0 to 23 ) of the memory location and the five ACB bits are stored in bits 24 to 28 .

The bits 29 to 31 of the memory location are cleared.

The program counter PC is incremented by the value 4 .

MWRI24 Instruction

Syntax: MWRI24 A, B

Operation: MEM(B[15:0])[23:0]←A;

Status: —

Duration: 2 instruction cycles

Code: 1010aaaabbbb1000 - -

Description: Transfer 24 bit value of A (AεOPER) to memory using indirect addressing.

The memory location where to write to is defined by the bits 0 to 15 of register B (BεREG).

The 24 bit value is stored in the lower significant bits (bit 0 to 23 ) of the memory location and the bits 24 to 31 are left unchanged.

The program counter PC is incremented by the value 4 .

MWRI16 Instruction

Syntax: MWRI16 A, B

Operation: MEM(B[15:0])[15:0]←A[15:0];

Status: —

Duration: 2 instruction cycles

Code: 1010aaaabbbb1010 - -

Description: Transfer 16 bit value of A (AεOPER) to memory using indirect addressing.

The memory location where to write to is defined by the bits 0 to 15 of register B (BεREG).

The lower significant 16 bits of A are stored in the lower significant bits (bit 0 to 15 ) of the memory location and the bits 16 to 31 are left unchanged.

The program counter PC is incremented by the value 4 .

POP Instruction

Syntax: POP A

Operation: A←MEM(R 7 [ 15 : 0 ])[23:0]; R 7 ←R 7 −4; SP_CNT←SP_CNT−1

Status: EN

Duration: 2 instruction cycles

Code: 1010aaaa - - - 0101 - -

Description: Transfer 24 bit value from the top of stack to register A (AεXREG), followed by decrementing the stack pointer register R 7 with the value 4 .

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

The 24 bit value of the stack is received from the lower significant bits (bit 0 to 23 ) of the memory.

The program counter PC is incremented by the value 4 .

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is decremented.

If an underflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an underflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the current MCS-channel is disabled by clearing the EN bit of STA.

PUSH Instruction

Syntax: PUSH A

Operation: R 7 ←R 7 +4; SP_CNT←SP_CNT+1; MEM(R 7 [15:0])[23:0]←A; MEM(R 7 [15:0])[28:24]←ACB

Status: EN

Duration: 2 instruction cycles

Code: 1010aaaa - - - 0110 - -

Description: Increment the stack pointer register R 7 with the value 4 , followed by transferring a 24 bit value of operand A (AεOPER) to the new top of the stack.

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

The 24 bit values of the stack are stored in the lower significant bits (bit 0 to 23 ) of the memory and the five ACB register bits are stored in bits 24 to 28 of the RAM.

The program counter PC is incremented by the value 4 .

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is incremented.

If an overflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the current MCS-channel is disabled by clearing the EN bit of STA.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the memory write operation for the A and ACB is discarded.

ARU Instructions

ARD Instruction

Syntax: ARD A, B, C

Operation: A←ARU(C)[23:0]; B←ARU(C)[47:24]; ACB[4:0]←ARU(C)[52:48]

Status: —

Duration: suspends current MCS-channel

Code: 1011aaaabbbb0000cccccccccccccccc

Description: Perform a blocking read access to the ARU and transfer both 24 bit values received at the ARU port to the registers A and B (AεREG, BεREG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

The received ARU control bits are stored in the register ACB.

The lower significant bits of the literal C (CεLIT 16 ) define the ARU address where to read from.

The program counter PC is incremented by the value 4 .

ARDI Instruction

Syntax: ARDI A, B

Operation: A←ARU(ACB[16:8])[23:0]; B←ARU(ACB[16:8])[47:24]; ACB[4:0]←ARU (ACB[16:8])[52:48]

Status: —

Duration: suspends current MCS-channel

Code: 1011aaaabbbb0100

Description: Perform a blocking read access to the ARU and transfer both 24 bit values received at the ARU port to the registers A and B (AεREG, B E REG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

The received ARU control bits are stored in the register ACB.

The read address is obtained from the bits 16 down to 8 of the channels ACB register.

The program counter PC is incremented by the value 4 .

ARDH Instruction

Syntax: ARDH B, C

Operation: B←ARU(C)[47:24]; ACB[4:0]←ARU(C)[52:48]

Status: —

Duration: suspends current MCS-channel

Code: 1011 - - - abbbb0010cccccccccccccccc

Description: Perform a blocking read access to the ARU and transfer upper 24 bit value received at the ARU port to the register B (BεREG).

The received ARU control bits are stored in the register ACB.

The lower significant bits of the literal C (CεLIT 16 ) define the ARU address where to read from.

The program counter PC is incremented by the value 4 .

ARDHI Instruction

Syntax: ARDHI B

Operation: B←ARU(ACB[16:8])[47:24]; ACB[4:0]←ARU(ACB[16:8])[52:48]

Status: —

Duration: suspends current MCS-channel

Code: 1011 - - - bbbb0110 - -

Description: Perform a blocking read access to the ARU and transfer upper 24 bit value received at the ARU port to the register B (BεREG).

The received ARU control bits are stored in the register ACB.

The read address is obtained from the bits 16 down to 8 of the channels ACB register.

The program counter PC is incremented by the value 4 .

ARDL Instruction

Syntax: ARDL A, C

Operation: A←ARU(C)[23:0]; ACB[4:0]←ARU(ACB[16:8])[52:48] Status: — Duration: suspends current MCS-channel Code: 1011aaaa - - - 0011cccccccccccccccc Description: Perform a blocking read access to the ARU and transfer lower 24 bit value received at the ARU port to the register A (AεREG).

The received ARU control bits are stored in the register ACB.

The lower significant bits of the literal C (CεLIT 16 ) define the ARU address where to read from.

The program counter PC is incremented by the value 4 .

ARDLI Instruction Syntax: ARDLI A Operation: A←ARU(ACB[16:8])[23:0]; ACB[4:0]←ARU(ACB[16:8])[52:48] Status: — Duration: suspends current MCS-channel Code: 1011aaaa - - - 0111 - - Description: Perform a blocking read access to the ARU and transfer lower 24 bit value received at the ARU port to the register A (AεREG).

The received ARU control bits are stored in the register ACB.

The read address is obtained from the bits 16 down to 8 of the channels ACB register.

The program counter PC is incremented by the value 4 .

AWR Instruction

Syntax: AWR A, B, C

Operation: ARU(C)[23:0]←A; ARU(C)[47:24]←B; ARU(C)[52:48]←ACB[4:0];

Status: —

Duration: suspends current MCS-channel

Code: 1011aaaabbbb0001cccccccccccccccc

Description: Perform a blocking write access to the ARU and transfer two 24 bit values to the ARU port using the registers A and B (AεREG, BεREG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

The ARU control bits to be sent are taken from the register ACB.

The lower significant bits (bit 0 to bit 3 ) of the literal C (CεLIT 16 ) define an index into the pool of ARU write address that is used for writing data.

Each MCS sub module has a pool of several write addresses that can be shared between all MCS-channels arbitrarily.

The program counter PC is incremented by the value 4 .

AWRI Instruction

Syntax: AWRI A, B

Operation: ARU(ACB[11:8])[23:0]←A; ARU(ACB[11:8])[47:24]←B; ARU(ACB[11:8])[52:48]←ACB[4:0];

Status: —

Duration: suspends current MCS-channel

Code: 1011aaaabbbb0101 - -

Description: Perform a blocking write access to the ARU and transfer two 24 bit values to the ARU port using the registers A and B (AεREG, BεREG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

The ARU control bits to be sent are taken from the register ACB.

The bits 11 down to 8 of the ACB register define an index into the pool of ARU write address that is used for writing data.

Each MCS sub module has a pool of several write addresses that can be shared between all MCS-channels arbitrarily.

The program counter PC is incremented by the value 4 .

Arithmetic Logic Instructions

ADDL Instruction

Syntax: ADDL A, C

Operation: A←A+C

Status: Z, CY, N, V

Duration: 1 instruction cycle

Code: 0010aaaacccccccccccccccccccccccc

Description: Perform addition operation of a register A (AεREG) with a 24 bit literal value C (CεLIT 24 ) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during addition, otherwise the bit is cleared.

The overflow bit V of status register STA is set, if a signed overflow occurred during subtraction, otherwise the bit is cleared.

The negative bit N of status register STA is set, if a calculated result is negative, otherwise the bit is cleared.

The program counter PC is incremented by the value 4 .

ADD Instruction

Syntax: ADD A, B

Operation: A←A+B

Status: Z, CY, N, V

Duration: 1 instruction cycle

Code: 1100aaaabbbb0000 - -

Description: Perform addition operation of a register A (AεREG) with an operand B (BεOPER) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during addition, otherwise the bit is cleared.

The overflow bit V of status register STA is set, if a signed overflow occurred during subtraction, otherwise the bit is cleared.

The negative bit N of status register STA is set, if a calculated result is negative, otherwise the bit is cleared.

The program counter PC is incremented by the value 4 .

SUBL Instruction

Syntax: SUBL A, C

Operation: A←A−C

Status: Z, CY, N, V

Duration: 1 instruction cycle

Code: 0011aaaacccccccccccccccccccccccc

Description: Perform subtraction operation of a register A (AεREG) with a 24 bit literal value C (CεLIT 24 ) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during subtraction, otherwise the bit is cleared.

The overflow bit V of status register STA is set, if a signed overflow occurred during subtraction, otherwise the bit is cleared.

The negative bit N of status register STA is set, if a calculated result is negative, otherwise the bit is cleared.

The program counter PC is incremented by the value 4 .

SUB Instruction

Syntax: SUB A, B

Operation: A←A−B

Status: Z, CY, N, V

Duration: 1 instruction cycle Code: 1100aaaabbbb0001 - -

Description: Perform subtraction operation of a register A (AεREG) with an operand B (BεOPER) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during subtraction, otherwise the bit is cleared.

The overflow bit V of status register STA is set, if a signed overflow occurred during subtraction, otherwise the bit is cleared.

The negative bit N of status register STA is set, if a calculated result is negative, otherwise the bit is cleared.

The program counter PC is incremented by the value 4 .

NEG Instruction

Syntax: NEG A, B

Operation: A←−B

Status: Z, CY, N, V

Duration: 1 instruction cycle

Code: 1100aaaabbbb0010 - -

Description: Perform negation operation (2's Complement) with an operand B (BεOPER) and store the result in a register A (AεREG).

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during subtraction, otherwise the bit is cleared.

The overflow bit V of status register STA is set, if a signed overflow occurred during subtraction, otherwise the bit is cleared.

The negative bit N of status register STA is set, if a calculated result is negative, otherwise the bit is cleared.

The program counter PC is incremented by the value 4 .

ANDL Instruction

Syntax: ANDL A, C

Operation: A←A AND C

Status: Z

Duration: 1 instruction cycle

Code: 0100aaaacccccccccccccccccccccccc

Description: Perform bitwise AND conjunction of a register A (AεXREG) with a 24 bit literal value C (CεLIT 24 ) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

AND Instruction

Syntax: AND A, B

Operation: A←A AND B

Status: Z

Duration: 1 instruction cycle

Code: 1100aaaabbbb0011 - -

Description: Perform bitwise AND conjunction of a register A (AεXREG) with an operand B (BεOPER) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

ORL Instruction

Syntax: ORL A, C

Operation: A←A OR C

Status: Z

Duration: 1 instruction cycle

Code: 0101aaaacccccccccccccccccccccccc

Description: Perform bitwise OR conjunction of a register A (AεXREG) with a 24 bit literal value C (CεLIT 24 ) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

OR Instruction

Syntax: OR A, B

Operation: A←A OR B

Status: Z

Duration: 1 instruction cycle

Code: 1100aaaabbbb0100 - -

Description: Perform bitwise OR conjunction of a register A (AεXREG) with an operand B (BεOPER) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

XORL Instruction

Syntax: XORL A, C

Operation: A←A XOR C

Status: Z

Duration: 1 instruction cycle

Code: 0110aaaacccccccccccccccccccccccc

Description: Perform bitwise XOR conjunction of a register A (AεXREG) with a 24 bit literal value C (CεLIT 24 ) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

XOR Instruction

Syntax: XOR A, B

Operation: A←A XOR B

Status: Z

Duration: 1 instruction cycle

Code: 1100aaaabbbb0101 - -

Description: Perform bitwise XOR conjunction of a register A (AεXREG) with an operand B (BεOPER) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

SHR Instruction

Syntax: SHR A, C

Operation: A←A>>C

Status: Z

Duration: 1 instruction cycle

Code: 1100aaaa - - - 0110cccccccccccccccc

Description: Perform right shift operation C (CεLIT 16 ) times of register A (AεREG).

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

SHL Instruction

Syntax: SHL A, C

Operation: A←A<<C

Status: Z

Duration: 1 instruction cycle

Code: 1100aaaa - - - 0111cccccccccccccccc

Description: Perform left shift operation C (CεLIT 16 ) times of register A (AεREG).

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

ROR Instruction

Syntax: ROR A

Operation: A←A>>1

Status: Z, CY

Duration: 1 instruction cycle

Code: 1100aaaa - - - 1000

Description: Perform rotate right operation of register A (AεREG).

In registers A, the bit a i is moved to the bit a i−1 (with i=0 to 23).

The carry bit CY of the status register STA is moved to bit a 23 and bit a 0 is moved to bit CY.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

ROL Instruction

Syntax: ROL A

Operation: A←A<< 1

Status: Z, CY

Duration: 1 instruction cycle

Code: 1100aaaa - - - 1001 - -

Description: Perform rotate left operation of register A (AεREG).

In registers A, the bit a i−1 is moved to the bit a i (with i=0 to 23).

The carry bit CY of the status register STA is moved to bit a 0 and bit a 23 is moved to bit CY.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

Test Instructions

LTL Instruction

Syntax: LTL A, C

Operation: A<C

Status: Z, CY

Duration: 1 instruction cycle

Code: 0111aaaacccccccccccccccccccccccc

Description: Less-than-comparison of an operand A (AεOPER) with a 24 bit literal value C (CεLIT 24 ).

The carry bit CY of status register STA is set if operand A is less than literal C.

Otherwise, the carry bit CY of status register STA is cleared if operand A is greater than or equal to literal C.

The zero bit Z of status register STA is set, if A equals to C.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to C.

The program counter PC is incremented by the value 4 .

LT Instruction

Syntax: LT A, B

Operation: A<B

Status: Z, CY

Duration: 1 instruction cycle

Code: 1101aaaabbbb0000 - -

Description: Less-than-comparison of an operand A (AεOPER) with an operand B (BεOPER).

The carry bit CY of status register STA is set if operand A is less than operand B. Otherwise, the carry bit CY of status register STA is cleared if operand A is greater than or equal to operand B.

The zero bit Z of status register STA is set, if A equals to B.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to B.

The program counter PC is incremented by the value 4 .

GTL Instruction

Syntax: GTL A, C

Operation: A>C

Status: Z, CY

Duration: 1 instruction cycle

Code: 1000aaaacccccccccccccccccccccccc

Description: Greater-than-comparison of an operand A (AεOPER) with a 24 bit literal value C (CεLIT 24 ).

The carry bit CY of status register STA is set if operand A is greater than literal C.

Otherwise, the carry bit CY of status register STA is cleared if operand A is less than or equal to literal C.

The zero bit Z of status register STA is set, if A equals to C.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to C.

The program counter PC is incremented by the value 4 .

GT Instruction

Syntax: GT A, B

Operation: A>B

Status: Z, CY

Duration: 1 instruction cycle

Code: 1101aaaabbbb0001 - -

Description: Greater-than-comparison of an operand A (AεOPER) with an operand B (BεOPER).

The carry bit CY of status register STA is set if operand A is greater than operand B.

Otherwise, the carry bit CY of status register STA is cleared if operand A is less than or equal to operand B.

The zero bit Z of status register STA is set, if A equals to B.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to B.

The program counter PC is incremented by the value 4 .

BTL Instruction

Syntax: BTL A, C

Operation: A AND C

Status: Z

Duration: 1 instruction cycle

Code: 1001aaaacccccccccccccccccccccccc

Description: Bit test of an operand A (AεOPER) with a 24 bit literal bit mask C (CεLIT 24 ).

The bit test is performed by applying a bitwise logical AND operation with operand A and the bit mask C without storing the result.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

BT Instruction

Syntax: BT A, B

Operation: A AND B

Status: Z

Duration: 1 instruction cycle

Code: 1101aaaabbbb0010 - -

Description: Bit test of an operand A (AεOPER) with an operand B (BεOPER), whereas usually one of the operands is a register holding a bit mask.

The bit test is performed by applying a bitwise logical AND operation with register A and register B without storing the result.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4 .

Control Flow Instructions

JMP Instruction

Syntax: JMP C

Operation: PC←C

Status: —

Duration: 1 instruction cycle

Code: 1110 - - -0000cccccccccccccccc

Description: Execute unconditional jump to the memory location C (CεLIT 16 ).

The program counter PC is loaded with literal C.

JBS Instruction

Syntax: JBS A, B, C

Operation: PC←C if A[B] is set

Status: —

Duration: 1 instruction cycle

Code: 1110aaaabbbb0001cccccccccccccccc

Description: Execute conditional jump to the memory location C (CεLIT 16 ).

The program counter PC is loaded with literal C, if the bit at position B (BεLIT 4 ) of operand A (AεOPER) is set.

Otherwise, if the bit is cleared, the program counter PC is incremented by the value 4 .

JBC Instruction

Syntax: JBC A, B, C

Operation: PC←C if A[B] is cleared

Status: —

Duration: 1 instruction cycle

Code: 1110aaaabbbb0010cccccccccccccccc

Description: Execute conditional jump to the memory location C (CεLIT 16 ).

The program counter PC is loaded with literal C, if the bit at position B (BεLIT 4 ) of operand A (AεOPER) is cleared.

Otherwise, if the bit is set, the program counter PC is incremented by the value 4 .

CALL Instruction

Syntax: CALL C

Operation: R7←R7+4; MEM(SP[15:0])[15:0]←PC+4; PC←C; SP_CNT←SP_CNT+1

Status: EN

Duration: 2 instruction cycles

Code: 1110 - - -0011cccccccccccccccc

Description: Call subprogram at memory location C (CεLIT 16 ).

The stack pointer register R 7 is incremented by the value 4 .

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

After the stack pointer is incremented, the incremented value of the PC is transferred to the top of the stack.

The program counter PC is loaded with literal C.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is incremented.

If an overflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the channel current MCS-channel is disabled by clearing the EN bit of STA.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the memory write operation of the incremented PC is discarding.

RET Instruction

Syntax: RET

Operation: PC←MEM(SP[15:0])[15:0]; R 7 ←R 7 − 4 ; SP_CNT←SP_CNT−1

Status: EN

Duration: 2 instruction cycles

Code: 1110 - - -0100 - -

Description: Return from subprogram.

The program counter PC is loaded with current value on the top of the stack.

Finally, the stack pointer register 7 is decremented by the value 4 .

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is decremented.

If an underflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an underflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register MCS[i]_CTRL is set, the channel current MCS-channel is disabled by clearing the EN bit of STA.

Other Instructions

WTRG Instruction

Syntax: WTRG A

Operation: Wait on trigger indexed by A

Status: —

Duration: suspends current MCS-channel

Code: 1111aaaa - - - 0000 - -

Description: Suspend current MCS-channel until a trigger bit is activated by another MCS-channel or the CPU, where A is the bit position of the trigger bit.

The trigger bits can be set by other MCS channels performing with a write access (e.g. using a MOVL instruction) to the STRG register.

Moreover, the trigger bits can be set by CPU performing with a write access to the MCS[i]_STRG register.

The trigger bit is not cleared automatically by hardware after resuming an MCS-channel, but it has to be cleared explicitly with a write access to the register CTRG by the MCS-channel or with a write access to the register CMCS[i]_CTRG by the CPU.

If a WTRG instruction is executed and the trigger bit is already set, the WTRG instruction does not suspend the channel.

The program counter PC is incremented by the value 4 , when the trigger bit is set and the channel continues its operation.

Please note that more then one channel can wait for the same trigger bit to continue.

NOP Instruction

Syntax: NOP

Operation: —

Status: —

Duration: 1 instruction cycle

Code: 0000 - -

Description: No operation is performed.

The program counter PC is incremented by the value 4 .

WTC Instruction

Syntax: WTC A

Operation: Wait for several instruction cycles.

Status: —

Duration: A+1 instruction cycles.

Code: 1111aaaa - - - 0001 - -

Description: The current MCS-channel is waiting for a dedicated number of instruction cycles, whereas register A (AεREG) holds the number of desired wait cycles.

If the register A holds a value greater than zero, the register is decremented, but the program counter PC is not incremented.

If the register A contains the value zero, the program counter PC is incremented by the value 4 .

While the WTC instruction is decrementing the register A, the CPU can access MCS memory, independent of the selected scheduling mode.

Thus, the WTC instruction can be used to improve memory bandwidth between CPU and MCS memory.

MCS Internal Registers

This section describes MCS internal registers that are only accessible by the corresponding MCS-channel itself.

These registers can be directly accessed with the entire MCS instruction set, e.g. using the ORL instruction to set a specific bit.

MCS Internal Registers Overview

The table describes the MCS internal registers. Only parts of this register set can be accessed by the CPU:

MCS Configuration Registers

This section describes the configuration registers of the MCS sub module.

These registers can only be accessed by the CPU using AEI, but not within the MCS-channel using MCS instructions.

MCS Configuration Registers Overview

The table describes the MCS registers that are visible and accessible by the CPU:

Memory Configuration (MCFG)

Overview

The Memory Configuration sub module (MCFG) is an infrastructure module that organizes physical memory blocks and maps them to the instances of Multi Channel Sequencer (MCS) sub modules.

The default configuration maps a memory of size 1K*32 bit=4 KB to MCS memory page 0 and a memory of size 0.5K*32 bit=2 KB to MCS memory page 1 .

In order to support different memory size for different MCS instances, the MCFG module provides two additional layout options for reorganization of memory pages between neighbouring MCS modules. FIG. 42 shows all layout options.

The layout option SWAP is swapping the 2 KB memory page of the current MCS instance with the 4 KB memory page of the successive MCS instance. Thus the memory of the current MCS module is increased by 2 KB but the memory of the successor is decreased by 2 KB.

The layout option BORROW is borrowing the 4 KB memory page of the successive MCS instance for the current instance. Thus the memory of the current MCS module is increased by 4 KB but the memory of the successor is decreased by 4 KB.

It should be noted that the successor of the last MCS instance MCS 3 is the first MCS instance MCS 0 .

Memory Layout Options

See FIG. 42 .

Consequently, the actual size of the memory pages for an MCS instance depends on the layout configuration for the current instance MCS[i] and the layout configuration of the preceding memory instance MCS[i− 1 ].

Table 0 summarizes the layout parameters MP 0 and MP 1 for MCS instance MCS[i].

The addressing of memory page 0 ranges from 0 to MP 0 - 4 and the addressing of memory page 1 ranges from MP 0 to MP 1 - 4 .

Memory Layout Parameters

See FIG. 43 .

MCFG Configuration Registers

This section describes the configuration registers of the MCFG sub module.

Interrupt Concentrator Module (ICM)

Overview

The Interrupt Concentrator Module (ICM) is used to bundle the GTM-IP interrupt lines of the individual sub modules in a reasonable manner into interrupt groups. By this bundling a smaller amount of interrupt lines is visible at the outside of the GTM-IP.

The individual interrupts of the GTM-IP sub modules and channels have to be enabled or disabled inside the sub modules and channels.

Chapter 0 shows the bundling for the three interrupt groups INFRA_IRQ_GPOUP and DPLL_IRQ_GROUP. However, there are more as these three interrupt groups present in the ICM.

ICM Interrupt Enable/Disable and Identification Principle

See FIG. 44 .

As can be seen from the figure, some parts of the bundling are already done inside the sub modules themselves. While some of the bundled interrupt lines coming from the sub modules are directly feed through the ICM to the outside world, the ICM bundles other interrupt lines internally and forms one combined interrupt line for the external world.

The feed through architecture of bundled interrupt lines is used for the sub modules ARU, BRC, CMP, PSM, TIM, DPLL and MCS.

The interrupts coming from the TOM and ATOM sub modules are internally combined in the ICM.

In the first case, the microcontroller can determine the interrupt source channel directly via the active interrupt line. As shown in the chapter 0 , the four interrupt lines of the individual PSM/FIFO channels are bundled into one external GTM-IP interrupt line PSMx_CHy_IRQ. The detailed interrupt of the PSM/FIFO channel has to be determined by accessing the corresponding FIFO_[x]_IRQ_NOTIFY register indicated by the ICM_IRQG_ 2 register bit or the interrupt PSMy_IRQ[x] respectively.

In the later case, the microcontroller is able to determine the interrupt source by reading out an ICM internal address first, to identify the sub module channel responsible for the interrupt and has then to read out the sub modules internal registers.

To determine the detailed interrupt source the microcontroller has to read the sub module/channel interrupt notification register NOTIFY and serve the channel individual interrupt.

Please note, that the interrupts are only visible inside the ICM and in consequence outside of the GTM-IP, when the interrupt is enabled inside the sub modules themselves.

ICM Interrupt Generation

The GTM-IP sub module individual interrupt sources are connected to the ICM. There, the individual interrupt lines are either feed through and signalled to the outside world or bundled a second time into groups and are then signalled to the outside world.

The ICM interrupt bundling is described in the following sections.

GTM Infrastructure Interrupt Bundling

The first interrupt group contains interrupts of the infrastructure and safety components of the GTM. This interrupt group includes therefore interrupt lines coming from the AEI, ARU, BRC, PSM, SPE and CMP sub modules. In this interrupt group each individual channel of the sub modules has its own interrupt line to the outside world.

Thus, the active interrupt line can be used by the CPU to determine the GTM-IP sub module channel that raised the interrupt. The interrupts are also represented in the ICM_IRQG_ 0 register, but this register is typically not read by the CPU.

DPLL Interrupt Bundling

The DPLL Interrupt group handles the interrupts coming from the DPLL sub module of the GTM-IP. Each of the individual DPLL interrupt lines has its own dedicated interrupt line to the outside world. The interrupts are additionally identified in the ICM_IRQG_ 1 interrupt group register, but this register is typically not read out by the CPU.

TIM Interrupt Bundling

Inside this group sub modules which handle GTM-IP input signals are treated. This is the case for the TIM sub modules. Each TIM sub module channel is able to generate six (6) individual interrupts if enabled inside the TIM channel. This six interrupts are bundled into one interrupt per TIM channel connected to the ICM.

The ICM does no further bundling. Thus, for the GTM-IP 40 interrupt lines TIMx_IRQ[y] are provided for the external microcontroller. The channel responsible for the interrupt can be determined by the raised interrupt line.

In addition, the ICM_IRQG_ 2 and ICM_IRQG_ 3 registers are a mirror for the TIM sub module channel interrupts.

MCS Interrupt Bundling

For complex signal output generation, the MCS sub modules are used inside the GTM-IP. Each of these MCS sub modules has eight channels with one interrupt line. This interrupt line is connected to the ICM sub module and is feed through directly to the outside world.

In addition the interrupt line status is shown in the ICM_IRQG_ 4 and ICM_IRQG_ 5 registers. Typically, the interrupt source is determined by the corresponding interrupt line and the ICM_IRQ 4 and ICM_IRQ 5 registers are never read out by the CPU.

TOM and ATOM Interrupt Bundling

For the TOM and ATOM sub modules, the interrupts are bundled within the ICM sub module a second time to reduce external interrupt lines. The interrupts are bundled in a manner that one GTM-IP external interrupt line represents two adjacent TOM or ATOM channel interrupts. For TOM 0 and TOM 1 the bundling is shown in chapter 0 .

TOM 0 and TOM 1 Interrupt Bundling within ICM

See FIG. 45 .

The interrupts coming from the TOM 0 and TOM 1 sub modules are registered in the ICM_IRQG_ 6 register. To identify the TOM sub module channel where the interrupt occurred, the CPU has to read out the ICM_IRQG_ 6 register first before it goes to the TOM sub module channel itself.

The ICM_IRQG_ 6 register bits are cleared automatically, when their corresponding interrupt in the sub module channels is served.

ICM Interrupt Signals

Following table shows the GTM-IP interrupt lines that are visible at the outside of the IP.

Signal Description GTM_AEI_IRQ AEI Shared interrupt GTM_ARU_IRQ[1:0] [0]: ARU_NEW_DATA Interrupt [1]: ARU_ACC_ACK Interrupt GTM_BRC_IRQ BRC Shared interrupt GTM_CMP_IRQ CMP Shared interrupt GTM_SPE0_IRQ SPE0 Shared interrupt GTM_SPE1_IRQ SPE1 Shared interrupt GTM_PSM0_IRQ[x] PSM0 Shared interrupts (x: 0 . . . 7) GTM_DPLL_IRQ[0] DPLL_TE4: DPLL TRIGGER event interrupt 4 GTM_DPLL_IRQ[1] DPLL_TE3: DPLL TRIGGER event interrupt 3 GTM_DPLL_IRQ[2] DPLL_TE2: DPLL TRIGGER event interrupt 2 GTM_DPLL_IRQ[3] DPLL_TE1: DPLL TRIGGER event interrupt 1 GTM_DPLL_IRQ[4] DPLL_TE0: DPLL TRIGGER event interrupt 0 GTM_DPLL_IRQ[5] DPLL_LL2I: DPLL Lost of lock interrupt for SUB_INC2 GTM_DPLL_IRQ[6] DPLL_GL2I: DPLL Get of lock interrupt for SUB_INC1 GTM_DPLL_IRQ[7] DPLL_EI: DPLL Error interrupt GTM_DPLL_IRQ[8] DPLL_LLI: DPLL Lost of lock interrupt for SUB_INC1 GTM_DPLL_IRQ[9] DPLL_GLI: DPLL Get of lock interrupt for SUB_INC1 GTM_DPLL_IRQ[10] DPLL_W1I: DPLL Write access to RAM region 1b or 1c int. GTM_DPLL_IRQ[11] DPLL_W2I: DPLL Write access to RAM region 2 interrupt GTM_DPLL_IRQ[12] DPLL_PWI: DPLL Plausibility window (PVT) viol. int. of TRIG. GTM_DPLL_IRQ[13] DPLL_TAS: DPLL TRIG. active slope det. while NTI_CNT is 0 GTM_DPLL_IRQ[14] DPLL_SAS: DPLL STATE active slope detected GTM_DPLL_IRQ[15] DPLL_MTI: DPLL Missing TRIGGER interrupt GTM_DPLL_IRQ[16] DPLL_MSI: DPLL Missing STATE interrupt GTM_DPLL_IRQ[17] DPLL_TIS: DPLL TRIGGER inactive slope detected GTM_DPLL_IRQ[18] DPLL_SIS: DPLL STATE inactive slope detected GTM_DPLL_IRQ[19] DPLL_TAX: DPLL TRIG. max. hold time (THMA) viol. detected GTM_DPLL_IRQ[20] DPLL_TIN: DPLL TRIG. min. hold time (THMI) viol. detected GTM_DPLL_IRQ[21] DPLL_PEI: DPLL enable interrupt GTM_DPLL_IRQ[22] DPLL_PDI: DPLL disable interrupt GTM_DPLL_IRQ[23] DPLL_CDIT: DPLL calculated duration interrupt for trigger GTM_DPLL_IRQ[24] DPLL_CDIS: DPLL calculated duration interrupt for state GTM_TIM0_IRQ[x] TIM0 Shared interrupts (x: 0..7) GTM_TIM1_IRQ[x] TIM1 Shared interrupts (x: 0..7) GTM_TIM2_IRQ[x] TIM2 Shared interrupts (x: 0..7) GTM_TIM3_IRQ[x] TIM3 Shared interrupts (x: 0..7) GTM_MCS0_IRQ[x] MCS0 Interrupt for channel x (x: 0 . . . 7) GTM_MCS1_IRQ[x] MCS1 Interrupt for channel x (x: 0 . . . 7) GTM_MCS2_IRQ[x] MCS2 Interrupt for channel x (x: 0 . . . 7) GTM_MCS3_IRQ[x] MCS3 Interrupt for channel x (x: 0 . . . 7) GTM_TOM0_IRQ[x] TOM0 Shared interrupts for x: 0..7 = {ch0||ch1, . . . , ch14||ch15} GTM_TOM1_IRQ[x] TOM1 Shared interrupts for x: 0..7 = {ch0||ch1, . . . , ch14||ch15} GTM_TOM2_IRQ[x] TOM2 Shared interrupts for x: 0..7 = {ch0||ch1, . . . , ch14||ch15} GTM_ATOM0_IRQ[x] ATOM0 Shared interrupts for x: 0..3 = {ch0||ch1, . . . , ch6||ch7} GTM_ATOM1_IRQ[x] ATOM1 Shared interrupts for x: 0..3 = {ch0||ch1, . . . , ch6||ch7} GTM_ATOM2_IRQ[x] ATOM2 Shared interrupts for x: 0..3 = {ch0||ch1, . . . , ch6||ch7} GTM_ATOM3_IRQ[x] ATOM3 Shared interrupts for x: 0..3 = {ch0||ch1, . . . , ch6||ch7} GTM_ATOM4_IRQ[x] ATOM4 Shared interrupts for x: 0..3 = {ch0||ch1, . . . , ch6||ch7}

ICM Configuration Registers Overview

ICM contains following configuration registers:

Details in Register Name Description Section ICM_IRQG_0 ICM Interrupt group register covering 0 infrastructural and safety components (ARU, BRC, AEI, PSM, MAP, CMP, SPE) ICM_IRQG_1 ICM Interrupt group register covering DPLL 0 ICM_IRQG_2 ICM Interrupt group register covering TIM0, 0 TIM1, TIM2, TIM3 ICM_IRQG_4 ICM Interrupt group register covering MCS0 0 to MCS3 sub modules ICM_IRQG_6 ICM Interrupt group register covering 0 GTM-IP output sub modules TOM0 to TOM1 ICM_IRQG_7 ICM Interrupt group register covering 0 GTM-IP output sub module TOM2 ICM_IRQG_9 ICM Interrupt group register covering 0 GTM-IP output sub modules ATOM0, ATOM1, ATOM2 and ATOM3 ICM_IRQG_10 ICM Interrupt group register covering 0 GTM-IP output sub module ATOM4

ICM Configuration Registers Description

TIM 0 Input Mapping Module (MAP)

Overview

The MAP sub module generates the two input signals TRIGGER and STATE for the sub module DPLL by evaluating the output signals of the channel 0 up to channel 5 of sub module TIM 0 . By using the TIM as input sub module, the filtering of the input signals can be done inside the TIM channels themselves. The MAP sub module architecture is depicted in FIG. 46 .

MAP Sub Module Architecture

See FIG. 46 .

Generally, the MAP sub module can route the channel signals coming from TIM 0 in two ways. First, it is possible to route the whole 49 bits of data coming from channel 0 of module TIM 0 (TIM 0 _CH 0 ) to the TRIGGER signal which is then provided to the DPLL together with the T_VALID signal. Second, the MAP module can route one of the signals coming from the module TIM 0 i.e. the signals coming from channel 1 up to channel 5 ) to the output signal STATE which is then provided to the module DPLL together with the S_VALID signal.

Second, the TRIGGER, T_VALID, STATE and S_VALID signals can be generated out of the TIM Signal Pre-processing (TSPP) subunits. This is done in combination with the Sensor Pattern Evaluation (SPE) sub module described in chapter 0 . There the signal TRIGGER is generated in subunit TSPP 0 out of the TIM signals coming from channel 0 up to 2 and the signal STATE is generated in subunit TSPP 1 out of the TIM signals coming from channel 3 up to channel 5 . This is only be done, when the TSSPx subunits are enabled and when the SPEx_NIPD signal is raised by the SPE sub module. The SPEx_NIPD_NUM signal encodes, which of the 3 TIMx_CHy input signals has been changed. The SPEx_DIR signal is routed through the TSPPx subunit and implements the T_DIR or S_DIR signal.

TIM Signal Pre-Processing (TSPP)

The TSPP combines the three 49 bit input streams coming from the TIM 0 sub module and generates one combined 49 bit output stream TSPPO. The input stream combination is done in the unit Bit Stream Combination (BSC). The architecture of the TSPP is shown in FIG. 47 .

TIM Signal Pre-processing (TSPP) Subunit Architecture

See FIG. 47 .

Bit Stream Combination

The BSC subunit is used to xor-combine the three most significant bits TIM 0 _CHx(48), TIM 0 _CHy(48) and TIM 0 _CHz(48) of the TIM 0 inputs. The xor-combined signal is merged with the remaining 48 bits of one of the three input signals TIM 0 _CHx(47 . . . 0), TIM 0 _CHy(47 . . . 0) or TIM 0 _CHz(47 . . . 0) the TSPPO signal. The selection is done with the SPEx_NIPD_NUM input signal coming from the SPE sub module. The action, when the 49 bits are transferred to the TSPPO and the T_VALID or S_VALID signal is raised is determined by the SPEx_NIPD signal coming from the SPE sub module. The TSPPO output signal generation is shown in the example in FIG. 48 .

TSPP Signal Generation for Signal TSPPO

See FIG. 48 .

The SPEx_NIPD_NUM input signal determines, which data is routed to the TSPPO signal. At the first edge of TIM 0 _CHx(48) the new data X11 and X12 are routed to TSPPO(47:0). The values X 11 and X 12 are the two 24 bit values coming from the TIM input channel TIM 0 _CHx. The next edge is at time t 1 on signal TIM 0 _CHy(48). Therefore, at time t 1 the TSPPO(48) signal level changes and the TSPPO(47:0) is set to Y 11 and Y 12 and so forth.

MAP Register Overview

The following table gives an overview about the MAP registers

Details in Register name Description Section MAP_CTRL MAP Control register 0

MAP Register Description

Register MAP_CTRL

Register MAP_CTRL Address Offset: 0x00000000 31 30 29 28 27 26 25 24 Bit Reserved TSPP1_I2V TSPP1_I1V TSPP1_I0V Reserved TSPP1_DLD TSPP1_EN Mode R RW RW RW R RW RW Initial 0 0 0 0 0 0 0 Value Address Offset: 0x00000000 23 22 21 20 19 18 17 16 Bit Reserved TSPP0_I2V TSPP0_I1V TSPP0_I0V Reserved TSPP0_DLD TSPP0_EN Mode R RW RW RW R RW RW Initial 0 0 0 0 00 0 0 Value Initial Value: 0x0000_0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Reserved SSL TSEL Mode R RW RW Initial 0 000 0 Value Bit 0 TSEL: TRIGGER signal output select. 0 = TIM0_CH0 selected as TRIGGER output signal. 1 = TSPP0_TSPPO selected as TRIGGER output signal. Bit 3:1 SSL: STATE signal output select. 000: TIM0_CH1 selected as STATE output signal. 001: TIM0_CH2 selected as STATE output signal. 010: TIM0_CH3 selected as STATE output signal. 011: TIM0_CH4 selected as STATE output signal. 100: TIM0_CH5 selected as STATE output signal. 101: TSPP1_TSPPO selected as STATE output signal. 110: Reserved 111: Reserved Bit 15:4 Reserved: Read as zero, should be written as zero. Bit 16 TSPP0_EN: Enable of TSPP0 subunit. 0 = TSPP0 disabled. 1 = TSPP0 enabled. Bit 17 TSPP0_DLD: DIR level definition bit. 0 = SPEx_DIR signal is routed through as is. 1 = SPEx_DIR signal is inverted. Bit 19:18 Reserved: Read as zero, should be written as zero. Bit 20 TSPP0_I0V: Enable of TSPP0 TIM0_CHx(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP0 is set to zero (0). Bit 21 TSPP0_I1V: Enable of TSPP0 TIM0_CHy(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP0 is set to zero (0). Bit 22 TSPP0_I2V: Enable of TSPP0 TIM0_CHz(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP0 is set to zero (0). Bit 23 Reserved: Read as zero, should be written as zero. Bit 24 TSPP1_EN: Enable of TSPP1 subunit. 0 = TSPP1 disabled. 1 = TSPP1 enabled. Bit 25 TSPP1_DLD: DIR level definition bit. 0 = SPEx_DIR signal is routed through as is. 1 = SPEx_DIR signal is inverted. Bit 27:26 Reserved: Read as zero, should be written as zero. Bit 28 TSPP1_I0V: Enable of TSPP1 TIM0_CHx(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP1 is set to zero (0). Bit 29 TSPP1_I1V: Enable of TSPP1 TIM0_CHy(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP1 is set to zero (0). Bit 30 TSPP1_I2V: Enable of TSPP1 TIM0_CHz(48) input line. 0 = Input line enabled. 1 = Input line disabled; input for TSPP1 is set to zero (0). Bit 31 Reserved: Read as zero, should be written as zero.

Digital PLL Module (DPLL)

Overview

The digital PLL (DPLL) sub module is used for frequency multiplication. The purpose of this module is to get a higher precision of position or value information also in the case of applications with rapidly changed input frequencies. The resolution of the generated signals is restricted by the period of the system clock used. The input signals to be triggered can be for instance position information of linear or angle motions, mass flow values, temperature, pressure or level of liquids.

The sub module is specified in such a way that it could be used easily by the software and can reduce the load of the CPU by relieving from repeated or periodic standard tasks.

The DPLL has to perform the following tasks:

prediction of the duration of the current increment in section 0 generation of SUB_INC pulses in normal or emergency mode (see section 0 ) synchronization of the actual position possibility of seamless switch to emergency mode and back prediction of position and time related events in section 0

Requirements and Demarcation

Up to 2 input signals could be used as trigger signals for the DPLL, one for a more frequent TRIGGER signal and one for a less frequent STATE signal. These signals can be selected from different available choices or be a combination of multiple input signals. The STATE signal is necessary in emergency mode, if no TRIGGER signal is available. Both input signals are combined with a validation signal T_VALID or S_VALID respectively, which shows the appearance of new data and must result in a data fetch and a start of the state machine to perform the calculations (see {REF: DPLL_1511}).

Because a switch in emergency mode can appear suddenly, the corresponding signals resulting from the STATE input should be calculated always as a precaution. The filtering as well as the combination or choice of the input signals is made in the TIM (see chapter 10 ) sub module by use of a configurable filter algorithm for each slope and signal as well as a multiplexer or a gating circuitry.

The filter delay value of the signal is transmitted in the FT part of the corresponding signal, because the delay conditions of the signals can change during application. The filter delays depend also on the filter algorithms used and therefore the generation of output reference signals have to be implemented properly, controlled by configuration bits in the control registers.

In order to provide the timing conditions to the DPLL the input trigger signals should have a time stamp (and optional in addition a position stamp, as stated above) with an appropriate resolution.

The DPLL delivers a reference signal as output depending on the time stamps of the input signals TRIGGER or STATE respectively and a signal which sends a predefined number of pulses between each active slope of the TRIGGER/STATE signal.

Dependent on configuration different actions in hardware are possible in order to correct a systematic wrong number of pulses.

Block and Interface Description

The block description of the DPLL is shown in the following picture.

DPLL Block Diagram

See FIG. 49 .

The following table summarizes the interface signals of the DPLL shown by the block diagram above ( FIG. 49 ).

Interface Description of DPLL

Name Width I/O Description Comment TRIGGER 1 × 49 I Normal Signal for 24 bits time stamp, triggering DPLL by filtered in different positions/values modes, 24 bits filter Bit(48) = TRIGGER_S delay value info, one Bits(47:24) = bit signal value (SV) TRIGGER_FT Bits(23:0) = TRIGGER_TS T_VALID 1 I The values of Announces the arrival TRIGGER are valid of a new TRIGGER value STATE 1 × 49 I Assistance signal for Replacement of synchronisation signal TRIGGER for STATE(48) = emergency situations, STATE_S bits like above, STATE(47:24) = corresponding; STATE_FT input can also be STATE(23:0) = used for the control of STATE_TS an independent device S_VALID 1 I The values of STATE Announces the arrival are valid of a new STATE value PMTR_D 53 I Position minus time Data values for request data, calculation of actual delivered by ARU on ACTIONs; the values request for up to 24 are requested by requests PMTR_RR; AENi = 1 1) and SV_i = PMTR_D(52:48): CAIP = 0 2) ; a served ACB bits, directly request is shown by written to the PMTR_V which correspondent signals that valid ACT_D registers PMTR data arrived PSAi = PMTR_D(47:24): and they are written position value for immediately after that action to the corresponding DLAi = PMTR_D(23:0) RAM regions and time delay value for registers; action PMTR_V 1 I signals a valid when valid: PMTR_D PMTR_D value, that overwrites data in the means data is PSAi and DLAi delivered on request registers, also when the corresponding ACT_Ni 3) bit = 1; ARU_CA 9 I Channel address; for counter value of ARU valid PMTR selects PMTR_RA addresses: demand and PMTR_RR when data by setting a valid address PMTR_RR = 1 when enabled by AENi = 1 1) and CAIP = 0 2) ; PMTR_RA 9 O read address of reflects ID_PMTR_i PMTR access according to the selected channel address PMTR_RR 1 O read request of reflects the value of PMTR access; the corresponding suppressed for AENi 1) bit while CAIP = 1 (see CAIP = 0 2) DPLL_STATUS register) ACT_D 53 O Output of a time Future time stamp, stamp, a position and additional position a control signal information and values for a additional control bits calculated action; SV_i = ACT_D(52:48): ACB bits, directly written from the correspondent PMTR_D signals; ACT_D(47:24) is the calculated position value PSACi for the action in relation to TBU_TS1 or 2 6) and ACT_D(23:0) is the time stamp value TSAi for the action in relation to TBU_TS0 6) ACT_V 1 O ACT_D value is for a valid action available and valid; address: ACT_V reflects the shadow value of ACT_Ni 3) (ACT_Ni is 1 when new PMTR values are available and the shadow register is updated, when a calculation of the actual PMTR values was done; ACT_Ni remains 1 until the calculated values are in the past or the corresponding AENi 1) bit is cleared) ACT_RA 9 I ACTION read address bits for address; selection of all 24 reading is always action channels valid after a first calculation of actual PMTR data ACT_RR 1 I read request of the action data is selected action demanded from an other module IRQ 23 O Interrupt request Interrupts of DPLL output SUB_INC1 1 O Pulse output for sub-position TRIGGER input filter increment provided continuously SUB_INC2 1 O Pulse output for sub-position STATE input filter increment provided continuously SUB_INC1c 1 O Pulse output for time sub-position base unit 1 in increment related to compensation mode TRIGGER input (can stop in automatic end mode) SUB_INC2c 1 O Pulse output for time sub-position base unit 2 in increment related to compensation mode STATE input (can stop in automatic end mode) TS_CLK 1 I Time stamp clock Clock, used for generation of the time stamps SYS_CLK 1 I System clock High frequency clock RESET_N 1 I Asynchronous reset Low active signal TBU_TS0 24 I Actual time stamp 24 bit time input, with from TBU; is needed a resolution of the to decide, if a time stamp clock calculated action is already in the past TBU_TS1 24 I Actual position/value 24 bit pos./val. input, stamp 1; for with a resolution of calculation of position the SUB_INC1 pulses stamps (TRIGGER/STATE) TBU_TS2 24 I Actual position/value ditto for SUB_INC2 stamp 2; to be for calculation of implemented for an position stamps additional (STATE) for independent position SMC 5) = RMO 4) = 1 TDIR 1 I Direction of direction information TRIGGER input from multiple sensors values (TDIR = 0 does valid only for mean a forward SMC 5) = 1 direction and TDIR = 1 a backward direction) SDIR 1 I Direction of STATE direction information input values (SDIR = 0 from multiple sensors does mean a forward valid only for direction and SDIR = 1 SMC 5) = 1 a backward direction) DIR1 1 O Direction information count direction of of SUB_INC1 (count TBU_TS1; DIR1 forwards for DIR1 = 0 changes always after and backwards for the evaluation of the DIR1 = 1) corresponding valid TRIGGER slope and after incrementing/decrementing of the address pointer DIR2 1 O Direction information count direction of of SUB_INC2 (count TBU_TS2; DIR2 forwards for DIR2 = 0 changes always after and backwards for the evaluation of the DIR2 = 1) corresponding valid STATE slope and after incrementing/decrementing of the address pointer For references above and below the following hints are used: 1) see DPLL_CTRL_x register, x = 2, 3, 4 2) see DPLL_STATUS register 3) see DPLL_ACT_STA register 4) see DPLL_CTRL_0 register 5) see DPLL_CTRL_1 register 6) see DPLL input signal description

DPLL Architecture

Purpose of the Module

The DPLL generates a predefined number of incremental signal pulses within the period between two events of an input TRIGGER or STATE signal. The resolution and number of the increments is restricted by the frequency of the system clock. Changes in the period length of the input signal will result in a change of the pulse frequency in order to get the same number of pulses. This adoption can be performed by DPLL hardware, software or with support of DPLL hardware in different modes.

The basic part of a DPLL is to make a prediction of the current period between two TRIGGER and/or STATE signal edges. Disturbances, systematic failures must be considered as well as changes in values or positions caused by acceleration and deceleration. Therefore, a good estimation is to be done using some measuring values from the past. When the process to be predicted takes a steady and differentiable course not only the current period but also some more periods for the future can be predicted. In utilisation of such calculations for the current increment also actions for the future can be predicted.

Explanation of the Prediction Methodology

As already shown in chapter 0 the DPLL has to perform different tasks. The basic function for all these tasks is a relation between time intervals in the past. Because the relation between two succeeding intervals at a fixed position remains also valid in the case of acceleration or deceleration the prediction of the duration of the current time interval is done by a similarity transformation. Having a good estimation of the current time interval, all the other tasks can be done easily by calculations explained in section 0 .

Clock Topology

All registers are read using the system clock SYS_CLK. The pulses generated have the highest frequency not higher then SYS_CLK. All operations can be performed using the system clock. In the case of no timing critical application and also for the case of power reduction the fast system clock can be replaced by a clock with lower frequency. When using a clock different to the system clock some synchronization registers are needed (not considered here).

Clock Generation

The clock is generated outside the DPLL.

Typical Frequencies

Typical system clock frequencies range from 40 MHz to 150 MHz, for future applications also up to 400 MHz. Frequency ranges for which a special technology of the circuits is needed, should be avoided.

Time Stamps and Systematic Corrections

The time stamps for the input signals TRIGGER and STATE have 24 bits each. These bits represent the value of the 24 bit free running counter running with a clock frequency of a typical 20 MHz. Thus the time stamp represents a relative value of time with a resolution of 50 ns in that typical case.

The input signals have to be filtered. The filter is not part of the DPLL. The time stamps can have a delay caused by the filter algorithm used. There are delayed and undelayed filter algorithms available and the delay value can depend on a time or a position value.

Systematic deviations of TRIGGER inputs can be corrected by a profile, which also considers systematic missing TRIGGERs. The increments containing missing TRIGGERS are divided into the corresponding number of nominal increments with duration comparable with all other increments. In the case of AMT=1 the ADT_Ti values in the RAM do contain the adapting information for the TRIGGER signal in normal mode.

The value PD for the TRIGGER describes the amount of missing or surplus pulses with a sint13 value, to be added to MLT directly (for SMC 5) =0). The correction value is in this way also applicable in the case of missing TRIGGER inputs for the synchronization gaps, while the value NT in addition describes the number of nominal parts to be considered for the following increment and is stored in the variable SYN_T (see NUTC register in section 0 ).

In the case of RMO 4) =1 for SMC 5) =0 (emergency mode) the time stamp of STATE is used to generate the output signal SUB_INC 1 .

More inaccuracy should be accepted because usually there are only a few values (SNU 4) ) available for FULL_SCALE.

For the STATE signal the systematic deviations of the increments can be corrected in the same way as for TRIGGER by adaptation information as described below.

Also for the case of systematic missing STATE events, all the increments can be divided into nominal parts of comparable duration using the stored profile information. The number of pulses SUB_INC 1 for a nominal STATE increment in emergency mode is given by the value of MLS 1 =(MLT+1)*(TNU+1)/SNU+1) for SMC=0 in order to get the same number of pulses in FULL_SCALE for normal and emergency mode.

For the case AMS 4) =1 the adapting values ADT_Si are used for the STATE signal.

The value PD_S for the STATE describes the amount of additional or surplus pulses with a sint16 value, to be added to MLS 1 .

DPLL Architecture Overview

As shown in 0 the DPLL can process different input signals. The signal TRIGGER is the normal input signal which gives the detailed information of the supervised process. It can be for instance the information of water or other liquid level representing the volume of the liquid, where each millimetre increasing results in a TRIGGER signal generation. In order to get a predefined filling level, without overflow also the inertia of the system must be taken into account. Hence, some delay for closing the inlet valve and also the remaining water amount in the pipe must be considered in order to start the closing action earlier as the filling level will be reached.

A second input signal STATE sends an additional (redundant) information for instance at some centimetres and because of intervals with different distances it gives also information about the system state with the direction of the water flow (in or out), while the TRIGGER signal must not contain information concerning the flow direction. In some applications the inactive slope of TRIGGER can be utilized to transmit a direction information. In the case of faults in the TRIGGER signal the STATE signal is to be processed in order to reach the desired value nevertheless, maybe with some loss of accuracy.

The measuring scale can have some systematic failures, because not all millimetre or centimetre distances measured mean the same value. This could be due to changes in the thickness of the measuring cylinder or the inaccurate position of the marks. These systematic failures are well know by the system and for improvement of the prediction the signals ADT_T and ADT_S for the correction of the systematic failures of TRIGGER and STATE respectively are stored in the internal RAM.

The input signals TRIGGER and STATE are represented as a time stamp signal each, which is stored in the 24 bit TS-part of the corresponding signal.

Information concerning the delay of this signal by filtering of disturbances is stored in the 24 bit FT-part of the signal.

In order to establish the relation of time stamps to the actual time the TBU_TS 0 6) value is also provided showing the actual time value to be compared with future time stamps in order to make a decision.

After reaching the desired water level the water is filled in a bottle by draining. After that the water filling is repeated. The water level at draining is observed by the same sensor signals (the same number of TRIGGER pulses), but the duration of the draining could be different from the filling time. Both times together form the FULL_SCALE region, while one of them is a HALF_SCALE region, which can differ time in i but not in the number of pulses.

For synchronisation purposes some TRIGGER marks can be omitted in order to set the system to a proper synchronisation value (maybe before the upper filling value is reached).

In emergency situations, when the TRIGGER signals are missed the STATE signal is used instead of.

The PMTR_i 6 ) signals announce the request for a position minus time calculation for up to 24 events.

All 24 events can be activated using the 24 AENi I (action enable) bits. Each of these enable bits are asked by the routing engine for a read access. The corresponding read request is generated by the AENi bit while CAIP is zero. CAIP is one bit of the DPLL_STATUS register with the meaning “calculation of actions in progress”, controlled by the state machine (see {REF: DPLL_1511}) for scheduling the operations.

When such a request is serviced by the ARU (in the case CAIP=0) the values for position and time are written in the corresponding RAM 1 a region (0x0200 . . . 0x025C for the position value and 0x0260 . . . 0x02BC for the delay value), the control bits for the corresponding action are set accordingly. When a new PMTR value arrives, an old value is overwritten without notice and the ACT_Ni (new action) bit in the DPLL_ACT_STA register is set, which is cleared, when the currently calculated action value is in the past. Overwriting of old information is possible because the read i request to ARU is suppressed during action calculations by the CAIP bit. In this way always the last possible PMTR value is used consistently.

DPLL Architecture Description

The DPLL block diagram 0 will now be explained in detail in combination with some example configuration of the control registers. Let in example TNU 4) be 0x3B (which is for TNU+1=60 decimal that means 120 events in FULL_SCALE) and MLT 4) be 0x257 (this means 600 pulses per TRIGGER event). Than you can divide FULL_SCALE into 72000 parts each of them associated with its own pulse. When you run through FULL_SCALE all 72000 pulses should appear but maybe with a different pulse frequency between two TRIGGER events. For this example after each 600 pulses at the SUB_INC 1 output the next TRIGGER event is to be expected with the corresponding new time stamp.

Missing pulses due to acceleration have to be taken into account within the next increment. Not one pulse has to be missed or added because of calculation inaccuracy in average for a sufficient number of FULL_SCALE periods. This means that not one pulse is sent in addition and all missing pulses are to be caught up on afterwards.

For correction of systematic missing TRIGGERs the value SYN_T bits of the NUTC register is used, which is got from the ADT_T values in the RAM region 2 c.

In normal mode the adapt values ADT_T could be used to balance the local systematic inaccuracy of the TRIGGER signal. The value of PD (see 0) is the pulse difference in the current increment and does mean the number of sub pulses to be added to the nominal number of pulses within the corresponding increment. PD is a signed integer value using 13 bits: up to +/−4096 pulses can be added for each increment.

The adapt values could be determined by the CPU (by the calculation of an average over a lot of measuring intervals) and stored in the RAM region 1 c 3 for STATE increments and in RAM region 2 c for TRIGGER increments.

Block diagram of time stamp processing.

See FIG. 50 .

Register and RAM Address Overview

The address map of the DPLL is divided into register and memory regions as defined in Table 0. The addresses from 0x0000 to 0x00FC are reserved for registers, from 0x0100 to 0x01Fc is reserved for action registers to serve the ARU at immediately request.

The RAM is divided into 3 independent accessible parts 1 a , 1 b+c and 2 .

The part 1 a from 0x0200 to 0x03FC is used for PMTR values got from ARU and intermediate calculation values; there is no write access from the CPU possible, while the DPLL is enabled.

The RAM 1 b part from 0x0400 to 0x05FC is reserved for RAM variables and the RAM part 1 c from 0x0600 to 0x09FC is used for the STATE signal values.

The RAM region 2 from 0x4000 to 0x7FFC is reserved for the TRIGGER signal values. RAM region 1 a has a size of 0,375 kBytes, Ram 1 b+c uses 1,125 kBytes while RAM region 2 is configurable from 1.5 to 12 kBytes, depending on the number of TRIGGER events in FULL_SCALE. The AOSV_ 2 register is used to determine the beginning of each part.

The table gives the DPLL Address map overview

Register and RAM Address Map

Registers are used to control the DPLL and to show its status. Also parameters are stored in registers when useful. The table below shows the addresses for status and control registers as well as values stored in additional registers. The register values are explained in the description part of this table while the bit positions of the status and control registers are described in detail in section 0 . Because the content of some value registers have a meaning related to position information (e.g. the address pointers APT and APS and the address pointers for the corresponding profile values APT_ 2 c and APS_ 1 c 3 respectively) it should be noticed that a synchronization is done when the pointers of the profile values are set by the CPU.

Addr. Addr. range range Value Byte Start End number # Content Indication Region RAM size 0x0000 0x0FC 64 256 Register used/ 0 no RAM reserved 0x100 0x1FC 64 192 ACTION direct read 0 no RAM registers from ARU 0x0200 0x03FC 128  384 PMTR CPU R/Pw 1a with RAM part values access, own 1a: 0.375 RAM 1a when DPLL ports kbytes disabled; ARU has highest priority 0x0400 0x05FC 128  384 Variables R and 1b RAM part RAM 1b monitored 1b + c: W access 1.125 by the CPU kbytes 0x0600 0x09FC 256  768 STATE R and 1c data monitored W access by the CPU 0x0600 0x06FC 64 192 RDT_Si STATE 1c1 reciprocal values 0x0700 0x07FC 64 192 TSF_Si STATE TS 1c2 values 0x0800 0x08FC 64 192 ADT_Si adapt 1c3 values of STATE 0x0900 0x09FC 64 192 DT_Si nom. 1c4 STATE inc 0x4000 0x47FC 512 . . . 1536 TRIGGER R and 2 RAM part . . . 4096 . . . data monitored 2: 1.5 . . . 0x7FFC 12288 W access 12 kbytes of CPU 0x4000 0x41FC 128 . . . 384 . . . RDT_Ti TRIGGER 2a . . . 4FFC 1024 3072 reciprocal values 0x4200 0x43FC 128 . . . 384 . . . TSF_Ti TRIGGER 2b . . . 5000 . . . 5FFC 1024 3072 TS values 0x4400 0x45FC 128 . . . 384 . . . ADT_Ti adapt 2c . . . 6000 . . . 6FFC 1024 3072 values of TRIGGER 0x4600 0x47FC 128 . . . 384 . . . DT_Ti nom. 2d . . . 7000 . . . 7FFC 1024 3072 TRIGGER increments

RAM Region 1

RAM region 1 has a size of 1.5 kBytes and is used to store variables and parameters as well as the measured and calculated values for increments of STATE. The RAM 1 region is divided into two independent accessible RAM parts with own ports. The address information is shown in the table above and the detailed description is performed in the following sections. The RAM 1 a is used to store the PMTR values got from ARU and in addition some intermediate calculation results or actions. RAM region 1 b is used for variables needed for the prediction of increments, while RAM 1 c is used to store time stamps, profile and durations for all the STATE inputs of the last FULL_SCALE region. All variables and values of RAM 1 b+c part use a data width of up to 24 bits.

The RAM is to be initialized by the CPU.

RAM Region 1 a : used for storage of PMTR values got from ARU; read and write access by the CPU is only possible, when the DPLL is disabled. The CPU Address range: 0x0200-0x03FC RAM Region 1 b : usable for intermediate calculations and auxiliary values, data width of 3 bytes used for 24 bit values; a write access to this region results in an interrupt to the CPU, when enabled. Address range: 0x0400-0x05FC RAM Region 1 c : Values of all STATE increments in FULL_SCALE, data width of 3 bytes used for 24 bit values;

a write access to this region results in an interrupt to the CPU, when enabled address range: 0x0600-0x09FC In RAM region 1 c there is a difference in the amount of data. While for the RAM regions 1 c 1 , 1 c 3 and 1 c 4 there are 2*(SNU+1−SYN_NS) entries, for the RAM region 1 c 2 there are 2*(SNU+1) entries. For the latter also the virtual events are considered, that means the gap is divided into equidistant parts each having the same position share as increments without a gap. For that reason the CPU must extend the stored TSF_Si values in the RAM region 1 c 2 before the APT_ 1 c 3 is written. The write access to APT_ 1 c 3 sets the SYS bit in the DPLL_Status register in order to show the end of the synchronization process. Only when the SYS bit is set the PMTR values can consider more then the last increment duration for the action prediction by setting NUSE to a corresponding value.

RAM Region 2

The RAM region 2 has a configurable size of 1.5 to 12 kBytes and is used to store measured and calculated values for increments of TRIGGER. The address information is explained later on.

Because of up to 512 TRIGGER events in HALF_SCALE the fields 2 a , b c and d must have up to 1024 storage places each. For 3 Bytes word size this does mean up to 12 k Byte of RAM region 2.

In order to save RAM size for configurations with less TRIGGER events the RAM is configurable by the offset switch Register OSW (0x001C) and the address offset value register of RAM region 2 AOSV_ 2 (0x0020). The RAM is to be initialized by the CPU.

In RAM region 2 there is a difference in the amount of data. While for the RAM regions 2 a , 2 c and 2 d there are 2*(TNU+1−SYN_NT) entries, for the RAM region 2 b there are 2*(TNU+1) entries. For the latter also the virtual events are considered, that means the gap is divided into equidistant parts each having the same position share as increments without a gap. For that reason the CPU must extend the stored TSF_Ti values in the RAM region 2 b before the APT_ 2 c is written.

The write access to APT_ 2 c sets the SYT bit in the DPLL_Status register in order to show the end of the synchronization process. Only when the SYT bit is set the PMTR values can consider more then the last increment duration for the action prediction by setting NUTE to a value greater then one.

Prediction of Next Increment

Increment Prediction in Normal Mode Forwards (DIR 1 =0)

For the prediction of actions in normal mode the values of RAM region 2 a are calculated as described in the following equations.

Please note, that the ascending order of calculation must be hold in order not to lose results still needed. It is important to calculate all equations to 16.14 before 16.1a4 . . . 7, 16.1b1 and 16.1c1, while the last one overwrites DT_Ti when NUTE (see section 0) is set to the FULL_SCALE range. Because the old value of DT_Ti is also needed for equation 16.10 and 16.11 this value is stored temporarily at DT_T_actual as shown by equation 16.1a or 16.1b respectively until all prediction calculations are done and after that equation 16.1a4 . . . 7, 16.1b1 and 16.1c1 updates DT_Ti: update DT_Ti after calculations of equation 16.14. For p=APT calculates in normal mode:

Equations 16.1a to Calculate TRIGGER Time Stamps

1) Consider values, calculated for the last increment; position related filter values are only considered up to at least 1 ms time between two TRIGGER events.

For calculation of time stamps use the filter delay information

TS_ T =TRIGGER_TS (unchanged for IDT= 0)  (16.1a0)

TS_ T =TS_ T −FTV_ T (for IDT= 1 and IFP= 0)  (16.1a1)

TS_ T =TS_ T −FTV_ T *(CDT_ TX /NMB_ T )_old 1) for ( IDT= 1 and IFP= 1)  (16.1a2)

this can be also calculated using the value of ADD_IN_CAL_N:

TS_ T =TS_ T −FTV_ T *(1/ADD_IN_CAL_ N _old 1) ) for ( IDT= 1 and IFP= 1)   (16.1a3)

NOTE: CDT_TX is the predicted duration of the last TRIGGER increment and NMB_T the calculated number of SUB_INC1 events in the last increment, because the new calculations are done by equations 16.5 and 16.21 for the current increment after that. Therefore in equation 16.1a3 the value ADD_IN of the last increment is used (see equation 16.25). SYN_T_old is the number of TRIGGER events including missing TRIGGERs as specified in the NUTC register for the last increment, with the initial value of 1.

For storage of time stamps in the RAM see also equations 16.1a4 ff. after calculation of actions

Equation 16.1b to Calculate DT_T_Actual (Nominal Value)

DT _ T _actual=(TS_ T −TS_ T _old)/SYN_ T _old  (16.1b)

For the case SYT=0 (still no synchronization to the profile) the values SYN_T and SYN_T_old are still assumed as having the value 1.

Equation 16.1c to Calculate RDT_T_Actual (Nominal Value)

RDT _ T _actual=1 /DT _ T _actual  (16.1c)

Equation 16.2a1 to Calculate QDT_T_Actual

Relation of the recent last two increment values for APT=p in forward direction (DIR1=0)

QDT _ T _actual= DT _ T _actual* RDT _ T ( p− 1)  (16.2a1)

QDT_T_actual as well as QDT_Ti have a 24 bit resolution and its relation value multiplied with 2 20

Equation 16.3 to Calculate the Error of Last Prediction

When q=NUTE consider for the error calculation only the last valid prediction values for DIR1=0:

Calculate the error of the last prediction when using only RDT_T(p−q−1), DT_T(p−q) and DT_T(p−1) for the prediction of DT_Tp:

EDT _ T=DT _ T _actual−( DT _ T ( p− 1)* QDT _ T ( p−q )  (16.3)

with

QDT _ T ( p−q )= DT _ T ( p−q )* RDT _ T ( p−q− 1)  (16.2b)

Equation 16.4 to calculate the weighted average error

MEDT _ T :=( EDT _ T+MEDT _ T )/2  (16.4)

Equations 16.5 to Calculate the Current Increment Value

Nominal Increment Value:

CDT _ TX _nom=( DT _ T _actual+ MEDT _ T )* QDT _ T ( p−q+ 1)  (16.5a)

with (for q>1):

QDT _ T ( p−q+ 1)= DT _ T ( p−q+ 1)* RDT _ T ( p−q )  (16.2c)

and for q=1 use equation 16.2a1.

the expected duration to the next TRIGGER event

CDT _ TX=CDT _ TX _nom*SYN_ T   (16.5b)

Note: In the case of an overflow in equations 16.5a or b set the value to 0xFFFFFF and the corresponding CTON or CTO bit in the DPLL_STATUS register.

Increment Prediction in Emergency Mode Forwards (DIR2=0)

Please note, that the ascending order of calculation for RAM region 1c must be hold in order not to lose results still needed. The same considerations as done for DT_T_actual are valid for DT_S_actual (equation 16.6a4 . . . 7, 16.6b1 and 16.6c1): update TD_Si after calculations of equation 16.14.

When using filter information of STATE_FT, selected by IDS=1, it must be distinguished by IFP, if this filter information is time or position related:

Equations 16.6a to Calculate STATE Time Stamps

For calculation of time stamps use the filter delay information and use p=APS while DIR2=0:

TS_S=STATE_TS (for IDS= 0, received unchanged value)  (16.6a0)

TS_ S =TS_ S−FTV _ S (for IDS= 1 and IFP= 0)  (16.6a1)

TS_ S =TS_ S−FTV _ S *( CDT _ SX/NMB _ S )_old 1) (for IDS= 1 and IFP= 1)  (16.6a2)

this can be also calculated using the value of ADD_IN_CAL_E:

TS_ S=TS _ S−FTV _ S *(ADD_IN_CAL_ E )_old 1) (for IDS= 1 and IFP= 1)  (16.6a3)

see also equations 16.6a4 ff. at chapter 0 for TRIGGER.

1) Consider values, calculated for the last increment; position related filter values are only considered up to at least 1 ms time between two STATE events.

Note: CDT_SX is the predicted duration of the last STATE increment and NMB_S the calculated number of SUB_INC 1 events in the last increment, because the new calculations are done by equations 16.10 and 16.22 respectively for the current increment after that. Therefore in equation 16.6a3 the value ADD_IN of the last increment is used (see equation 16.26). SYN_S_old is the number of increments including missing STATEs as specified in the NUSC register for the last increment with the initial value of 1 . The update to the RAM region 1 c 4 is done after all related calculations (see equation 16.6d—after 16.14—for this reason).

Equation 16.6b to Calculate DT_S_Actual (Nominal Value)

DT _ S _actual=(TS_ S −TS_ S _old)/SYN_ S _old  (16.6b)

For the case SYS=0 (still no synchronization to the profile) the values SYN_S and SYN_S_old are still assumed as having the value 1.

Equation 16.6c to Calculate RDT_S_Actual (Nominal Value)

RDT _ S _actual=1 /DT _ S _actual  (16.6c)

Equation 16.7a1 to Calculate QDT_S_Actual

for APS=p in forward direction (DIR 2 =0)

QDT _ S _actual= DT _ S _actual* RDT _ S ( p− 1)  (16.7a1)

QDT_S_actual as well as QDT_Si have a 24 bit resolution and its relation value multiplied with 2 20

Equation 16.8 to Calculate the Error of Last Prediction

with q=NUSE when using QDT_S(p−q) and DT_S(p−1) for the prediction of DT_Sp

EDT _ S=DT _ S _actual−( DT _ S ( p− 1)* QDT _ S ( p−q ))  (16.8)

and with

QDT _ S ( p−q )= DT _ S ( p−q )* RDT _ S ( p−q− 1)  (16.7b)

Equation 16.9 to Calculate the Weighted Average Error

MEDT _ S :=( EDT _ S+MEDT _ S )/2  (16.9)

Equations 16.10 to Calculate the Current Increment (Nominal Value)

CDT _ SX _nom=( DT _ S _actual+ MEDT _ S )* QDT _ S ( p−q+ 1)  (16.10a)

with

QDT _ S ( p−q+ 1)= DT _ S ( p−q+ 1)* RDT _ S ( p−q ) (for q> 1)  (16.7c)

see equation 16.7a for q=1

and the expected duration to the next STATE event

CDT _ SX=CDT _ SX _nom* SYN _ S   (16.10b)

Note: In the case of an overflow in equations 16.10a or b set the value to 0xFFFFFF and the corresponding CSON or CSO bit in the DPLL_STATUS register. All 5 steps above (16.6 to 16.10) are only needed in emergency mode. For the normal mode the calculations of equations 16.6 and 16.7 are done solely in order to get the values needed for a sudden switch to emergency mode.

Increment Prediction in Normal Mode Backwards (DIR 1 =1)

Equations 16.2a2 to Calculate QDT_T_Actual Backwards

QDT _ T _actual= DT _ T _actual* RDT _ T ( p+ 1)  (16.2a2)

QDT_T_actual as well as QDT_Ti have a 24 bit resolution and its relation value multiplied with 2 20

Equation 16.3a to Calculate of the Error of Last Prediction

When q=NUTE and DIR1=1 using only RDT_T(p+q+1), DT_T(p+q) and DT_T(p+1) for the prediction of DT_Tp

EDT _ T=DT _ T _actual−( DT _ T ( p+ 1)* QDT _ T ( p+q )  (16.3a)

with

QDT _ T ( p+q )= DT _ T ( p+q )* RDT _ T ( p+q+ 1)  (16.2b1)

Equation 16.4 to Calculate the Weighted Average Error

MEDT _ T :=( EDT _ T+MEDT _ T )/2  (16.4)

Equation 16.5 to Calculate the Current Increment Value

CDT _ TX _nom=( DT _ T _actual+ MEDT _ T )* QDT _ T ( p+q− 1)  (16.5a1)

with

QDT _ T ( p+q− 1)= DT _ T ( p+q− 1)* RDT _ T ( p+q ) (for q> 1)  (16.2c1)

for q=1 use equation 16.2a1.

and the expected duration to the next TRIGGER event

CDT _ TX=CDT _ TX _nom*SYN_ T   (16.5b)

Note: In the case of an overflow in equations 16.5a or b set the value to 0xFFFFFF and the corresponding CTON or CTO bit in the DPLL_STATUS register.

Increment Prediction in Emergency Mode Backwards (DIR2=1)

Equation 16.7a2 to Calculate QDT_S_Actual Backwards

QDT _ S _actual= DT _ S _actual* RDT _ S ( p+ 1)  (16.7a2)

Equation 16.8a to Calculate the Error of the Last Prediction

While q=NUSE, use only QDT_S(p+q) and DT_S(p+1) for the prediction of DT_Sp

EDT _ S=DT _ S _actual−( DT _ S ( p+ 1)* QDT _ S ( p+q ))  (16.8a)

with

QDT _ S ( p−q )= DT _ S ( p+q )* RDT _ S ( p+q+ 1)  (16.7b1)

Equation 16.9 to Calculate the Weighted Average Error

MEDT _ S :=( EDT _ S+MEDT _ S )/2  (16.9)

Equations 16.10 to Calculate the Current Increment Value

CDT _ SX _nom=( DT _ S _actual+ MEDT _ S )* QDT _ S ( p+q− 1)  (16.10a)

with

QDT _ S ( p+q− 1)= DT _ S ( p+q− 1)* RDT _ S ( p+q ) (for q> 1)  (16.7c1)

for q=1 use equation 16.7a.

and calculate the expected duration to the next STATE event

CDT _ SX=CDT _ SX _nom*SYN_ S   (16.10b)

Note: In the case of an overflow in equations 16.10a or b set the value to 0xFFFFFF and the corresponding CSON or CSO bit in the DPLL_STATUS register. All 5 steps above (16.6 to 16.10) are only needed in emergency mode. For the normal mode the calculations of equations 16.6 and 16.7 are done solely in order to get the values needed for a sudden switch to emergency mode.

Calculations for Actions

As already shown for the calculation of the current interval by equations 16.1 to 16.10 for the prediction of actions a similar calculation is to be done, as shown by the equations 16.11. to 16.14. The calculation of actions is also needed when the DPLL is used for synchronous motor control applications (SMC=1, see DPLL_CTRL_ 1 register). For action prediction purposes the measured time periods of the paste (one FULL_SCALE back, when the corresponding NUTE or NUSE values are set properly by the CPU) are used. The calculation can be explained by the following assumptions, which are considerably simple:

Take the corresponding increments for prediction in the past and put the sum of it in relation to the increment (DT_T_, DT_S_, which is represented by the time stamp difference) which is exactly one FULL_SCALE period in the past (16.11 or 16.13 respectively). Make a prediction for the coming sum of increments using the current measured increment (DT_T_actual or DT_S_actual respectively, that means 16.1 or 16.6 respectively) and add a weighted average error (16.3 and 16.4 or 16.8 and 16.9 respectively, calculated for one increment prediction) before multiplication with the relation of equation 16.11 or 16.13 respectively in order to get the result as described by equations 16.12 or 16.14 respectively.

In order to avoid division operations instead of the increment (DT_T_, DT_S_) in the paste its reciprocal value (RDT_T_, RDT_S_) is used, which is stored also in RAM. For the calculation of actions perform always a new refined calculation as long as the resulting time stamp is not in the past. In the other case the corresponding ACT_Ni bit in the DPLL_ACT_STA register is reset. Each new PMTR_i value will set this ACT_Ni bit again and result in a new calculation.

Calculations in Normal Mode forwards

valid for RMO=0 or for SMC=1

Equation 16.11a1 to Calculate the Time Prediction for an Action

For p=APT_ 2 b, t=APT, m=NAi (part w), mb=NAi(part b), NUTE=q>m and DIR1=0 calculate:

PDT _ Ti =( TSF _ T ( p+m−q )− TSF _ T ( p−q )+ mb*DT _ T _actual)* RDT _ T ( t−q )   (16.11a1)

For SMC=0 and RMO=0 calculate for DIR 1 = 0 all 24 actions in forward direction, if requested; in the case SMC=1 calculate up to 12 actions 0 to 11 in dependence of the TRIGGER input.

Equation 16.11a2 to Calculate the Time Prediction for an Action

For SYT=1, FS=1 and hence (because of the cyclic storage) for NUTE=2*(TNU+1) and DIR 1 =0 equation 16.11a2 is equal to

PDT _ Ti =( TSF _ T ( p+m )− TSF _ T ( p )+ mb*DT _ T _actual)* RDT _ Tt   (16.11a2)

Equation 16.11b to Calculate the Time Prediction for an Action

for DIR 1 =1, NUTE=q<m, q>1 and t=APT:

PDT _ Ti =( m+mb )* DT _ T ( t−q+ 1)* RDT _ T ( t−q )  (16.11b)

Note: Make the calculations above before updating the TSF_Ti values according to equations 16.1c3 ff.

Equation 16.11c to Calculate the Time Prediction for an Action

for q=1 (as well as for SYT=0)

PDT _ Ti =( m+mb )* DT _ T _actual* RDT _ T ( t− 1)  (16.11c)

Note: For the relevant last increment add the fractional part of DT_T_actual as described in NAi.

Equation 16.12 to Calculate the Duration Value Until Action

DTAi =( DT _ T _actual+ MEDT _ T )* PDT _ Ti   (16.12)

Note: All 5 steps in equations 16.11 to 16.12 are only calculated in normal mode.

Calculations in Normal Mode Backwards

valid for RMO=0 or for SMC=1

For SMC=0 and DMO=0 calculate for DIR 1 =1 all 24 actions in backward direction for special purposes; in the case SMC=1 calculate up to 12 actions 0 to 11 in dependence of the TRIGGER input.

Equation 16.11a3 to Calculate the Time Prediction for an Action

For p=APT_ 2 b, t=APT, m=NAi (part w), mb=NAi(part b), q=NUTE calculate:

PDT _ Ti =( TSF _ T ( p−m+q )− TSF _ T ( p+q )+ mb*DT _ T _actual)* RDT _ T ( t+q )   (16.11a3)

Equation 16.11a4 to Calculate the Time Prediction for an Action

For SYT=1, FS=1 and hence (because of the cyclic storage) for NUTE=2*(TNU+1) and DIR 1 =1 this is equal to

PDT _ Ti =( TSF _ T ( p−m )− TSF _ T ( p )+ mb*DT _ T _actual)* RDT _ Tt   (16.11a4)

Note: Make the calculations above before updating the TSF_Ti values according to equations 16.1c3 ff.

Equation 16.11b1 to Calculate the Time Prediction for an Action

For NUTE=q<m the following equation is valid for q>1 and t=APT:

PDT _ Ti =( m+mb )* DT _ T ( t+q− 1)* RDT _ T ( t+q )  (16.11b1)

Equation 16.11c1 to Calculate the Time Prediction for an Action

for q=1 (as well as for SYT=0)

PDT _ Ti =( m+mb )* DT _ T _actual* RDT _ T ( t+ 1)  (16.11c1)

Note: For the relevant last increment add the fractional part of DT_T_actual as described in NAi.

Equation 16.12 to Calculate the Duration Value for an Action

DTAi =( DT _ T _actual+ MEDT _ T )* PDT _ Ti   (16.12)

Use the results of equations 16.1a, b, 16.3 and 16.4 for the above calculation

Note: All 5 steps in equations 16.11 to 16.12 are only calculated in normal mode.

Calculations in Emergency Mode Forwards

valid for RMO=1

For SMC=0 and RMO=1 calculate for DIR 2 =0 all 24 actions in forward direction, if requested; in the case SMC=1 and RMO=1 calculate up to 12 actions 12 to 23 in dependence of the STATE input.

Equation 16.13a1 to Calculate the Time Prediction for an Action

For p=APS_ 1 c 2 , t=APS, m=Nai(part w) mb=Nai(part b), NUSE=q>m calculate:

PDT _ Si =( TSF _ S ( p+m−q )− TSF _ S ( p−q )+ mb*DT _ S _actual)* RDT _ S ( t−q )   (16.13a1)

Equation 16.13a2 to Calculate the Time Prediction for an Action

For SYS=1, FS=1 and hence (because of the cyclic storage) for NUSE=2*(SNU+1) equation 16.13a1 is equal to

PDT _ Si =( TSF _ S ( p+m )− TSF _ S ( p )+ mb*DT _ S _actual)* RDT _ St   (16.13a2)

Equation 16.13b to Calculate the Time Prediction for an Action

For NUSE=q<m and q>1:

PDT _ Si=m*DT _ S ( p−q+ 1)* RDT _ S ( p−q )  (16.13b)

Equation 16.13c to Calculate the Time Prediction for an Action

for q=1

PDT _ Si=m*DT _ S _actual* RDT _ S ( p− 1)  (16.13c)

Equation 16.14 to Calculate the Duration Value for an Action

DTAi =( DT _ S _actual+ MEDT _ S )* PDT _ Si   (16.14)

Use the results of 16.7, 16.8 and 16.9 for the above calculation

Note: All 5 steps of equations 16.13 to 16.14 are only calculated in emergency mode.

Calculations in Emergency Mode Backwards valid for RMO=1

For SMC=0 and RMO=1 calculate for DIR2=1 all 24 actions in backwards mode for special purposes; in the case SMC=1 and RMO=1 calculate up to 12 actions 12 to 23 in dependence of the STATE input.

Equation 16.13a3 to Calculate the Time Prediction for an Action

For p=APS_ 1 c 2 , t=APS, m=Nai(part w) mb=Nai(part b), NUSE=q≧m calculate

PDT _ Si =( TSF _ S ( p−m+q )− TSF _ S ( p+q )+ mb*DT _ S _actual)* RDT _ S ( t+q )   (16.13a3)

Equation 16.13a4 to Calculate the Time Prediction for an Action

For SYS=1, FS=1 and hence (because of the cyclic storage) for NUSE=2*(SNU+1) equation 16.13a3 is equal to

PDT _ Si =( TSF _ S ( p−m )− TSF _ S ( p )+ mb*DT _ S _actual)* RDT _ St   (16.13a4)

Equation 16.13b1 to Calculate the Time Prediction for an Action

For NUSE=q<m and q>1:

PDT _ Si=m*DT _ S ( p+q− 1)* RDT _ S ( p+q )  (16.13b1)

Equation 16.13c1 to Calculate the Time Prediction for an Action

for q=1

PDT _ Si=m*DT _ S _actual* RDT _ S ( p+ 1)  (16.13c1)

Equation 16.14 to Calculate the Duration Value Until Action

DTAi =( DT _ S _actual+ MEDT _ S )* PDT _ Si   (16.14)

Use the results of 16.7, 16.8 and 16.9 for the above calculation

Note: All 5 steps of equations 16.13 to 16.14 are only calculated in emergency mode.

Update of RAM in Normal and Emergency Mode

After considering the calculations for up to all 24 actions according to equations (16.11, 16.12), also when not performed, set time stamp values and durations of increments in the RAM:

Equation 16.1a4 to Update the Time Stamp Values for Trigger

TSF _ T ( s )= TS _ T   (16.1a4)

Store the time stamp values in the time stamp field according to the address pointer APT_ 2 b=s, but make this update only after the calculation of actions 0 because the old TSF_Ti values are still needed for these calculations. Please note that the address pointer after a gap is still incremented by SYN_T_old in that case (see state machine step 1 in chapter 0).

Equation 16.1a5-7 to Extend the Time Stamp Values for TRIGGER

when SYT=1, SYN_T_old=r>1 and DIR1=0

TSF _ T ( s− 1)= TSF _ T ( s )− DT _ T _actual  (16.1a5)

TSF _ T ( s− 2)= TSF _ T ( s− 1)− DT _ T _actual  (16.1a6)

until

TSF _ T ( s−r+ 1)= TSF _ T ( s−r+ 2)− DT _ T _actual  (16.1a7)

after the incrementation of the pointer APT_ 2 b by SYN_T_old

Equations 16.1a5-7 for Backward Direction

when SYT=1, SYN_T_old=r>1 and DIR1=1

TSF _ T ( s+ 1)= TSF _ T ( s )− DT _ T _actual  (16.1a5)

TSF _ T ( s+ 2)= TSF _ T ( s+ 1)− DT _ T _actual  (16.1a6)

until TSF_T(s+r−1)=TSF_T(s+r−2)−DT_T_actual  (16.1a7)

after the decrementation of the pointer APT_ 2 b by SYN_T_old

Equations 16.1b1 and 16.1c1 to Update the RAM after Calculation

DT _ Tp=DT _ T _actual  (16.1b1)

RDT _ Tp=RDT _ T _actual  (16.1c1)

store increment duration and reciprocal value in RAM after calculation of actions and before a new TRIGGER increment begins in normal and emergency mode.

Equation 16.6a4 to Update the Time Stamp Values for State

TSF _ S ( s )= TS _ S   (16.6a4)

Store the time stamp value in the time stamp field according to the address pointer APS_ 1 c 2 =s, but make this update only after the calculation of actions (equations 16.13a2, 0 or 16.13a4 0, if applicable) because the old TSF_Si values are still needed for these calculations. Please note, that the address pointer after a gap is still incremented by SYN_S_old in that case (see state machine step 21 in chapter 0).

Equations 16.6a5-7 to Extend the Time Stamp Values for State

When SYS=1 and SYN_S_old=r>1 and DIR2=0 calculate

TSF _ S ( s− 1)= TSF _ S ( s )− DT _ S _actual  (16.6a5)

TSF _ S ( s− 2)= TSF _ S ( s− 1)− DT _ S _actual  (16.6a6)

until

TSF _ S ( s−r+ 1)= TSF _ S ( s−r+ 2)− DT _ S _actual  (16.6a7)

after incrementation of the pointer APS_ 2 b by SYN_S_old

Equations 16.6a5-7 for Backward Direction

When SYS=1 and SYN_S_old=r>1 and DIR2=1 calculate

TSF _ S ( s+ 1)= TSF _ S ( s )− DT _ S _actual  (16.6a5)

TSF _ S ( s+ 2)= TSF _ S ( s+ 1)− DT _ S _actual  (16.6a6)

until

TSF _ S ( s+r− 1)= TSF _ S ( s+r− 2)− DT _ S _actual  (16.6a7)

Equations 16.6b1 and 16.6c1 to Update the RAM After Calculation

DT _ Sp=DT _ S _actual  (16.6b1)

RDT _ Sp=RDT _ S _actual  (16.6c1)

before a new STATE increment begins in normal and emergency mode.

store increment duration and reciprocal value in RAM after calculation of actions and before a new STATE increment begins in normal and emergency mode.

Time and Position Stamps for Actions in Normal Mode

Equation 16.15 to Calculate the Action Time Stamp

TSAi=DTAi−DLAi+TS _ T (for DTAi>DLAi )  (16.15)

TSAi=TS _ T (for DTAi<DLAi )  (16.15)

calculation is done after the calculation of the current expected duration value according to equation 16.12, 0 the time stamp of the action can be calculated as shown in equation 16.15 using the delay value of the action and the current time stamp.

Equations 16.17 to Calculate the Position Stamp Forwards

for DIR 1 =0

PSACi =(( DTAi−DLAi )* RCDT _ TX _nom)*( MLT+ 1)+ PSTC   (16.17)

with

RCDT _ TX _nom= RCDT _ TX *SYN_ T   (16.17a)

and

RCDT _ TX= 1 /CDT _ TX   (16.17b)

use the calculated value of (16.17b) also for the generation of SUB_INCi and serve the action by transmission of TSAi and PSACi to ACT_D_i

The action is to be updated for each new TRIGGER event until the calculated time stamp is in the past. Because of the non blocking read operation the ACT_D values can be read repeatedly.

Equations 16.17 to Calculate the Position Stamp Backwards

For DIR 1 =1

PSACi=PSTC −(( DTAi−DLAi )* RCDT _ TX _nom)*( MLT+ 1)  (16.17c)

with

RCDT _ TX _nom= RCDT _ TX *SYN_ T   (16.17a)

and

RCDT _ TX= 1 /CDT _ TX   (16.17b)

use the calculated value of (16.17b) also for the generation of SUB_INCi and serve the action by transmission of TSAi and PSACi to ACT_D_i

The action is to be updated for each new TRIGGER event until the calculated time stamp is in the past. Because of the non blocking read operation the ACT_D values can be read repeatedly.

Time and Position Stamps for Actions in Emergency Mode

Equation 16.18 to Calculate the Action Time Stamp

TSAi=DTAi−DLAi+TS _ S   (16.18)

calculation is done after the calculation of the current expected duration value according to equation 16.14, 0 the time stamp of the action can be calculated as shown in equation 16.18 using the delay value of the action and the current time stamp

Equations 16.20 to Calculate the Position Stamp Forwards

for DIR 2 =0

PSACi =(( DTAi−DLAi )* RCDT _ SX _nom)* MLS 1 +PSSC   (16.20)

with

RCDT _ SX _nom= RCDT _ SX *SYN_ S   (16.20a)

and

RCDT _ SX= 1 /CDT _ SX   (16.20b)

use the calculated value of (16.20b) also for the generation of SUB_INCi.

and serve the action by transmission of TSAi and PSACi to ACT_D.

The action is to be updated for each new STATE event until the event is in the past. Because of the blocking read operation the ACT_D values can be read only once.

Equations 16.20 to Calculate the Position Stamp Backwards

For DIR 2 =1

PSACi=PSSC −(( DTAi−DLAi )* RCDT _ SX _nom)* MLS 1  (16.20c)

with

RCDT _ SX _nom= RCDT _ SX *SYN_ S   (16.20a)

and

RCDT _ SX= 1 /CDT _ SX   (16.20b)

use the calculated value of (16.20b) also for the generation of SUB_INCi.

and serve the action by transmission of TSAi and PSACi to ACT_D.

The action is to be updated for each new STATE event until the event is in the past. Because of the non blocking read operation the ACT_D values can be read repeatedly.

The Use of the RAM

The RAM is used to store the data of the last FULL_SCALE period. The use of single port RAMs is recommended. The data width of the RAM is usual 3 bytes, but could be extended to 4 bytes in future applications. There are 3 different RAMs, each with separate access ports. the RAM 1 a is used to store the position minus time requests, got from the ARU. No CPU access is possible to this RAM during operation (when the DPLL is enabled).

Ram 1 b is used for configuration parameters and variables needed for calculations. within RAM 1 c the values of the STATE events are stored. RAM 1 b and RAM 1 c do have a common access port and are also marked as RAM 1 bc in order to clarify this fact.

RAM 2 l is used for values of the TRIGGER events.

Because of the access of the DPLL internal state machine at the one side and the CPU at the other side the access priority has to be controlled for both RAMs 1 bc and 2 . The access priority is defined as stated below. The CPU access procedure via AE-interface goes in a wait state (waiting for data valid) while it needs a colliding RAM access during serving a corresponding state machine RAM access. In order not to provoke unexpected behaviour of the algorithms the writing of the CPU to the RAM regions 1 b , 1 c or 2 will be monitored and results in interrupt requests when enabled.

CPU access is specified at follows:

1. CPU has highest priority for a single read/write access. The DPLL algorithm is stalled during external bus RAM accesses. 2. After serving the CPU access to the RAM the DPLL gets the highest RAM access priority for 8 clock cycles. Afterwards continue with 1 .

The RAM address space has to be implemented in the address space of the CPU.

Signal Processing

Time Stamp Processing

Signal processing does mean the computation of the time stamps in order to calculate at which time the outputs have to appear. For such purposes the time stamp values have to be stored in the RAM and by calculating the difference between old and new values the duration of the last time interval is determined simply. This difference should be also stored in the RAM in order to see the changes between the intervals by changing the conditions and the speed of the observed process.

Count and Compare Unit

The count and compare unit processes all input signals taking into account the configuration values. It uses a state machine and provides the output signals as described above.

Sub pulse generation for SMC=0

Equation 16.21 to Calculate the Number of Pulses to be Sent in Normal Mode Using the Automatic End Mode Condition

For RMO=0, SMC=0 and DMO=0

NMB _ T =( MLT+ 1)* SYN _ T+MP+PD _store  (16.21)

with

PD _store= ADT _ T (12:0)  (16.21a)

while the value for PD_store is zero for AMT=0

and

the value of MP is zero for COA=0

In order to get a higher resolution for higher speed a generator for the sub-pulses is chosen using an adder. All missing pulses MP are considered using equation 16.21 and are determined by counting the number of pulses of the last increment. The value SYN_T is stored from the last increment using NT of the ADT_Ti value at RAM region 2 c.

Equations 16.22-24 to Calculate the Number of Pulses to be Sent in Emergency Mode Using the Automatic End Mode Condition

For RMO=1, SMC=0 and DM 0 = 0 ;

the value for PD_S_store is zero for AMS=0

NMB _ S=MLS 1*SYN_ S+MP+PD _ S _store  (16.22)

with

MLS 1=( MLT+ 1)*( TNU+ 1)/( SNU+ 1)  (16.23)

and

PD _ S _store= ADT _ S (12:0)  (16.24)

Please note, that these calculations above in equations 16.21 and 16.22 are only valid for an automatic end mode (DMO=0).

For calculation of the number of generated pulses a value of 0.5 is added as shown in equations 16.25 or 16.26 respectively in order to compensate rounding down errors at the succeeding arithmetic operations. Because in automatic end mode the number of pulses is limited by INC_CNT1 it is guaranteed, that not more pulses as needed are generated and in the same way missing pulses are made up for the next increment.

Equation 16.25 to Calculate ADD_IN in Normal Mode

In normal mode (for RMO=0) calculate

ADD_IN_CAL_ N =( NMB _ T+ 0.5)* RCDT _ TX   (16.25)

with

RCDT_TX is the 224 time value of the quotient in equation 16.17b

0

Missing pulses to be caught up on with highest frequency should be sent to the input RPCUx (rapid pulse catch up on) in 0, while EN_Cxg=0 for the time sending such pulses.

For the normal mode replace ADD_IN of the ADDER (see FIG. 51 ) by ADD_IN_CAL_N (when calculated, DLM=0) or ADD_IN_LD_N (when provided by the CPU, DLM=1).

The sub-pulse generation in this case is done by the following calculations using a 24 bit adder with a carry out c out and the following inputs:

ADD_IN the second input is the output of the adder, stored one time stamp clock before

In order not to complicate the calculation procedure use a Multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

Enabling of the Compensated Output for Pulses

The c out of the adder influences directly the SUB_INC1 output of the DPLL (see FIG. 51 ). The compensated output SUB_INCxc is in automatic end mode only enabled by EN_Cxc when INC_CNTx>0.

Equation 16.26 to Calculate ADD_IN in Emergency Mode

In emergency mode (RMO=1) calculate

ADD_IN_CAL_ E =( NMB _ S+ 0.5)* RCDT _ SX   (16.26)

while

RCDT_SX is the 2 24 time value of the quotient in equation 16.20b 0.

Missing pulses to be caught up on with highest frequency should be sent to the input RPCUx (rapid pulse catch up on) in 0, while EN_Cxg=0 for the time sending such pulses.

For the emergency mode replace ADD_IN of the ADDER (see FIG. 51 ) by ADD_IN_CAL_E (when calculated, DLM=0) or ADD_IN_LD_E (when provided by the CPU, DLM=1).

The sub-pulse generation in this case is done by the following calculations using a 24 bit adder with a carry out c out and the following inputs:

ADD_IN the second input is the output of the adder, stored one time stamp clock before

In order not to complicate the calculation procedure use a Multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

Adder for Generation of SUB_INCx by the Carry c out .

See FIG. 51 .

Note: The SUB_INC generation by the circuit above has the advantage, that the resolution for higher speed values is better as for a simple down counter.

After RESET and after EN_Cxc=0 (after stopping in automatic end mode) the flip-flops (FFs) should have a zero value. EN_Cxg has to be zero until reliable ADD_IN values are available and the pulse generation starts. The calculated values for the increment prediction using equations 16.2c 0, 16.2c1, 16.7c or 16.7c1 respectively are valid only when at least NUTE>1 TRIGGER values or at least NUSE>1 STATE values are available. In the meantime the values QDT_Ti or QDT_Si are considered as having the value 1. In the time period with NUTE=1 or NUSE=1 respectively the equations 16.25 0 and 16.26 0 use the actual increment value subtracted by the weighted average error.

The generation of SUB_INC 1 pulses depends on the configuration of the DPLL. In automatic end mode the counter INC_CNT 1 resets the enable signal EN_C 1 when the number of pulses desired is reached. In this case only the uncompensated output SUB_INC 1 remains active in order to provide pulses for the input filter unit. A new TRIGGER input in normal mode or a new STATE input in emergency mode respectively resets the FFs and also the enable signal EN_Cxg. In the case of acceleration missing pulses can be determined at the next TRIGGER/STATE event in normal/emergency mode easily. For the correction strategy COA=0 those missing pulses are sent out with maximum frequency as soon they are determined. During this time period the EN_Cxg remains cleared. After calculation or providing of a new ADD_IN value the FFs are enabled by EN_Cxg. In this way no pulse is lost. The new pulses are sent out afterwards, when INC_CNT 1 is set to the desired value, maybe by adding MLT+1 or MLS 1 respectively for the new TRIGGER/STATE event.

Because the used DIV procedure of the algorithms results only in integer values, a systematic failure could appear. The pulse generation at SUB_INC 1 will stop in automatic end mode when the INC_CNT 1 register reaches zero or all remaining pulses at a new increment will be considered in the next calculation. In this way the lost of pulses can be avoided.

When a new TRIGGER/STATE appears the value of SYN_T*(MLT+1) or SYN_S*MLS 1 respectively is added to INC_CNT 1 . Therefore for FULL_SCALE 2*(TNU+1)*(MLT+1) pulses SUB_INC 1 generated, when INC_CNT1 reaches the zero value. The generation of SUB_INC 1 pulses has to be done as fast as possible. The calculations for the ADD_IN value must be done first. Therefore all values needed for calculation are to be fetched in a forecast.

Sub Pulse Generation for SMC=1

Necessity of Two Pulse Generators

The Adder of picture 0 must be implemented twice in the case of SMC=1: one for SUB_INC 1 controlled by the TRIGGER input and (while RMO=1) one for SUB_INC 2 , controlled by the STATE input. In the case described in the chapter above for SMC=0 only one Adder is used to generate SUB_INC 1 controlled by the TRIGGER in normal mode or by STATE in emergency mode.

Equation 16.27 to Calculate the Number of Pulses to be Sent for the First Device Using the Automatic End Mode Condition

For RMO=0, SMC=1 and DMO=0

NMB _ T=MLS 1*SYN_ T+MP _ +PD _store  (16.27)

with

PD _store= ADT _ T (12:0) of last increment  (16.21a)

while the value for PD_store is zero for AMT=0

and

the value of MP is zero for COA=0

Equation 16.28 to Calculate the Number of Pulses to be Sent for the Second Device Using the Automatic End Mode Condition

for RMO=1, SMC=1 and DMO=0

NMB _ S=MLS 2*SYN_ S+MP+PD _ S _store  (16.28)

with

PD _ S _store= ADT _ S (12:0) of last increment  (16.29)

while the value for PD_S_store is zero for AMS=0

and

the value of MP is zero for COA=0

Please note, that these calculations above in equations 16.27 and 16.28 are only valid for an automatic end mode (DMO=0). In addition the number of generated pulses is added by 0.5 as shown in equations 16.30 or 16.31 respectively in order to compensate rounding down errors at the succeeding division operation. Because in automatic end mode the number of pulses is limited by INC_CNTx it is guaranteed, that not more pulses as needed are generated and in the same way missing pulses are made up for the next increment.

Equation 16.30 to Calculate ADD_IN for the First Device

The sub-pulse generation in this case is done by the following calculations using a 24 bit adder with a carry out c out and the following inputs:

ADD_IN the second input is the (delayed) output of the adder, stored with each time stamp clock.

For RMO=0

replace ADD_IN by ADD_IN_CAL_N (when calculated, DLM=0) or ADD_IN_LD_N (when provided by the CPU, DLM=1) with:

ADD_IN_CAL_ N =( NMB _ T+ 0.5)* RCDT _ TX   (16.30)

When RCDT_TX is the 2 24 time value of the quotient in equation 16.17b 0

In order not to complicate the calculation procedure use a Multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

ADD_IN_CAL_N is a 24 bit integer value. The CDT_TX is the expected duration of current TRIGGER increment.

The c out of the adder influences directly the SUB_INC 1 output of the DPLL (see 0). The SUB_INC 1 output is in automatic end mode only enabled by EN_C1 when INC_CNT 1 >0.

Equation 16.30 to Calculate ADD_IN for the Second Device

For RMO=1

replace ADD_IN by ADD_IN_CAL_E (when calculated, DLM=0) or ADD_IN_LD_E (when provided by the CPU, DLM=1) with:

ADD_IN_CAL_ E =( NMB _ S+ 0.5)* RCDT _ SX   (16.31)

When RCDT_SX is the 2 24 time value of the quotient in equation 16.20b 0

In order not to complicate the calculation procedure use a Multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

The c out of the adder 2 influences directly the SUB_INC 2 output of the DPLL (see 0 ).

The SUB_INC 2 output is in automatic end mode only enabled by EN_C2 when INC_CNT2>0.

Note:

Please note, that after RESET and after EN_Cxc=0 (after stopping in automatic end mode) the flip-flops (FFs) have a zero value and also EN_Cxg has to be zero until reliable ADD_IN values are available and the pulse generation starts. The calculated values for the increment prediction using equations 16.2c 0, 16.2c1, 16.7c or 16.7c1 respectively are valid only when NUTE>1 or NUSE>1 respectively. In the meantime the values QDT_T_actual of equation 16.2a1 or QDT_S_actual of equation 16.7a1 are considered as having the value 1, also when RDT_T or RDT_S are zero (set to zero for minimal speed). In this time period for NUTE=1 or NUSE=1 respectively the equations 16.30 0 and 16.31 0 use the actual increment value subtracted by the weighted average error.

The generation of SUB_INCx pulses depends on the configuration of the DPLL.

In automatic end mode the counter INC_CNTx resets the enable signal EN_Cxcu when the number of pulses desired is reached. In this case only the uncompensated outputs SUB_INCx remain active in order to provide pulses for the input filter units. A new TRIGGER or STATE input respectively can reset the FFs and also ADD_IN, especially when EN_Cxc was zero before. In the case of acceleration missing pulses can be determined at the next TRIGGER/STATE event easily. For the correction strategy COA=0 those missing pulses are sent out with maximum frequency as soon they are determined. After that the pulse counter INC_CNTx should be always zero and the new pulses are sent out afterwards, when INC_CNTx is set to the desired value by adding MLS 1 or MLS 2 for the new TRIGGER or STATE event respectively.

Because the used DIV procedure of the algorithms results only in integer values, a systematic failure could appear. The pulse generation will stop when the INC_CNTx register reaches zero or all remaining pulses at a new increment will be considered in the next calculation. In this way the lost of pulses can be avoided.

When a new TRIGGER appears the value of SYN_T*MLS 1 is added to INC_CNT 1 . Therefore for FULL_SCALE 2*(TNU+1)*MLS 1 pulses SUB_INC 1 generated, when INC_CNT reaches the zero value. The generation of SUB_INC 1 pulses has to be done as fast as possible.

When a new STATE appears the value of SYN_S*MLS 2 is added to INC_CNT 2 . Therefore for FULL_SCALE 2*(SNU+1)*MLS 2 pulses SUB_INC 2 generated, when INC_CNT 2 reaches the zero value. The generation of SUB_INC 2 pulses has to be done as fast as possible.

Calculation of the Accurate Position Values

All incoming TRIGGER and STATE signals do have a time stamp and a position stamp assigned after the input filter procedure. For the calculation of the exact time stamp the filter values are considered in the calculations of equations 16.1a 0 or 16.6a 0 respectively. A corresponding calculation is to be performed for the calculation of position values. The accurate value could not be calculated for the first value (FTD=0 or FSD=0 respectively), because the values needed for this calculation are still not available:

for the case of a time related filter delay of TRIGGER the duration of the last increment is not known and also after the second TRIGGER input value there is no information about a gap until SYT or SYS is set respectively for the case of a position related filter delay the used SUB_INCx pulses are still not provided with a reliable relation to the increment duration.

For these reasons the calculated position values can be only determined exactly after setting the corresponding address pointer values APT_ 2 c or APTS_1c3 by the CPU respectively. This is flagged by the SYT or SYS bit in the DPLL_STATUS register respectively.

The PSTC and PSSC values are corrected by the CPU only.

Let PSTM be the measured position value and IDT=1, so the accurate position value PSTC could be calculated once by the CPU as follows:

for IFP=1 (filter delay considers position information)

PSTC=PSTM−IDT*FTV _ T   (16.32a)

for SMC=0 and IFP=0 (filter delay considers time information)

PSTC=PSTM−IDT*FTV _ T *( MLT+ 1)*SYN_ T _old/ DT _ T _actual  (16.32b)

for SMC=1 and IFP=0 (filter delay considers time information)

PSTC=PSTM−IDT*FTV _ T*MLS 1*SYN_ T _old/ DT _ T _actual  (16.32c)

Let PSSM be the measured position value and IDS=1, so the accurate position value PSSC could be calculated once by the CPU as follows:

for IFP=1 (filter delay considers position information)

PSSC=PSSM−IDS*FTV _ S   (16.33a)

for SMC=0 and IFP=0 (filter delay considers time information)

PSSC=PSSM−IDS*FTV _S*MLS1*SYN_ S _old/ DT _ S _actual  (16.33b)

for SMC=1 and IFP=0 (filter delay considers time information)

PSSC=PSSM−IDS*FTV _S*MLS2*SYN_ S _old/ DT _ S _actual  (16.33c)

The above calculation must be performed by the CPU at least once and the corresponding corrected PSTC/PSSC values are updated periodically by adding the increment values (MLT* 1 ), MLS 1 or MLS 2 respectively by the DPLL.

Scheduling of the Calculation

After enabling the DPLL with each valid TRIGGER or STATE event respectively a cycle of operations is performed to calculate all the results shown in detail in the table below {REF: DPLL_1511}. A state machine controls this procedure and consists of two parts, the first is triggered by a valid slope of the signal TRIGGER, begins at step 1 and ends at step 17 (in normal mode and for SMC=1). The second state machine is controlled by a valid slope of the signal STATE, begins at step 21 and ends at step 37 (in emergency mode and also for SMC=RMO=1). Depending on the mode used all 17 steps are executed or already after 2 steps the jump into the initial state is performed, as shown in the state machine descriptions below. For each new extended cycle (without this jump) all prediction values for actions in the case SMC=0 are calculated once more (with maybe improved accuracy because of better parameters) and all pending decisions are made using these new values when transmitted to the decision device.

In 0 the steps of the state machine are described. Please note, that the elaboration of the steps depends on the configuration bits described in the comments. The steps 4 to 17 are only calculated in normal mode (in the state machine explanation below marked yellow in {REF: DPLL_1511}), but steps 24 to 37 are only calculated in emergency mode (in the state machine explanation below marked cyan in {REF: DPLL_1511}) when SMC=0.

State Machine Partitioning for Normal and Emergency Mode.

See FIG. 52 .

Synchronization Description

The APT (address pointer for duration and reciprocal duration values of TRIGGER increments) is initially set to zero and incremented with each valid TRIGGER event. Therefore data are stored in the RAM beginning from the first available value. The actual duration of the last increment is stored at DT_T_actual. For the prediction of the next increment it is assumed, that the same value is valid as long as NUTE is one.

A missing TRIGGER is assumed, when at least after (TOV+1)*DT_T_actual no valid TRIGGER event appears.

The data of equations 16.1b1 and 16.1c1 0 is written in the corresponding RAM regions and APT is incremented accordingly up to 2*TNU−2*SYN_NT+1.

The APT_ 2 b (address pointer for the time stamp field of TRIGGER) is initially set to zero and incremented with each valid TRIGGER event. When no gap is detected because of the incomplete synchronization process at the beginning, for all TRIGGER events the time stamp values are written in the RAM up to up to 2*TNU−2*SYN_NT+1 entries. When the CPU knows the exact position, it extends the time stamp field at the gap positions by the number of virtual entries. In the consequence all 2*(TNU+1) storage locations do have the corresponding entries.

When the CPU detects the correct position and also the TSF_Ti values are extended properly to all 2*(TNU+1) entries in the RAM it writes the APT_ 2 c address pointer accordingly with the corresponding offset and caused by this write process the SYT bit is set simultaneously. For SYT=1 in normal mode (SMC=0) the LOCK1 bit is set with the system clock, when the right number of increments between two synchronization gaps is detected by the DPLL. An unexpected missing TRIGGER or an additional TRIGGER between two synchronization gaps does reset the LOCK1 bit in normal mode.

When SYT is set the calculations of equations 16.1 to 16.5 are performed accordingly and the values are stored in (and distributed to) the right RAM positions.

This includes the multiple time stamp storage by the DPLL for a gap according to equations 16.1a5 to 7 forwards 0 or backwards 0. The APT_ 2 b pointer is for that reason incremented or decremented before this operation considering the virtual increments in addition.

Please note, that for the APT and APT_ 2 c pointers the gap is considered as a single increment.

The APS (address pointer for duration and reciprocal duration values of STATE) is initially set to zero and incremented with each valid STATE event. Therefore data are stored in the RAM field beginning at the first location. The actual duration of the last increment is stored at DT_S_actual. For the prediction of the next increment it is assumed, that the same value is valid as long as NUSE is one.

A missing STATE is assumed, when at least after (TOV_S+1)*DT_S_actual no valid STATE event appears.

The data of equations 16.6b1 and 16.6c1 0 is written in the corresponding RAM regions and APS is incremented accordingly up to 2*SNU−2*SYN_NS+1.

The APS_ 1 c 2 (address pointer for the time stamp field of STATE) is initially set to zero and incremented with each valid STATE event. When no gap is detected because of the incomplete synchronization process at the beginning, for all STATE events the time stamp values are written in the RAM up to up to 2*SNU−2*SYN_NS+1 entries. When the CPU knows the exact position, it extends the time stamp field at the gap positions by the number of virtual entries. In the consequence all 2*(SNU+1) storage locations do have the corresponding entries.

When the CPU detects the correct position and also the TSF_Si is extended properly it writes the APS_ 1 c 3 address pointer accordingly with the corresponding offset and caused by this write process the SYS bit is set simultaneously. For SYS=1 in emergency mode (SMC=0) the LOCK 1 bit is set with the system clock, when the right number of increments between two corresponding synchronization gaps is detected. An unexpected missing STATE or an additional STATE between two synchronization gaps does reset the LOCK 1 bit in emergency mode.

When SYS is set the calculations of equations 16.5 to 16.10 are performed accordingly and the values are stored in (and distributed to) the right RAM positions. This includes the multiple time stamp storage by the DPLL for a gap according to equations 16.6a5 to 7 forwards 0 or backwards 0. The APS_ 1 c 2 pointer is for that reason incremented or decremented before this operation considering the virtual increments in addition.

Please note, that for the APS and APS_ 2 c pointers the gap is considered as a single increment.

SMC=1:

For SMC=1 it is assumed, that the starting position is known by measuring the characteristic of the device. In this way the APT and APT_ 2 c as well the APS and APS_ 1 c 3 values are set properly, maybe with an unknown repetition rate. When no gap is to be considered for TRIGGER or STATE signals the APT_ 2 b and APS_ 1 c 2 address pointers are set equal to APT or APS respectively. It is assumed, that all missing TRIGGERs and missing STATEs can be also considered from the beginning, when a valid profile with the corresponding adapts values is written in the RAM regions 1 c 3 and 2 c respectively. In that case the TSF_Ti and TSF_Si must be extended to all events (including missing events), before the address pointers for the profiles are set. Thus the SYT and SYS bits could be set from the beginning and the LOCK 1 and LOCK 2 bits are set after recognition of the corresponding gaps accordingly. When no gap exists, the LOCK bits are set after a FULL_SCALE operation. The CPU can correct the APT_ 2 c and APS_ 1 c 3 pointer according to the recognized repetition rate later once more without the loss of Lock 1 , 2 .

Operation in Backward Direction in Normal Mode (SMC=0)

When for SMC=0 in normal mode a backwards condition is detected for the TRIGGER input signal (e.g. when THMI is violated), the LOCK 1 bit and the FTD (as well as LOCK 2 and FSD) in the DPLL_STATUS register are reset, the NUTE value in NUTC register is set to 1 (the same for NUSE in NUSC) and the address pointers APT and APT_ 2 c as well as APT_ 2 b are incremented for a last time (and after that decremented for each following valid slope of TRIGGER as long as the DIR 1 bit shows the backward direction).

Please notice, that in the case of the change of the direction the ITN and ISN bit in the DPLL_STATUS register are reset.

For this transition to the backward direction no change of address pointers APT and APT_ 2 b is necessary.

Profile Update for TRIGGER

The profile address pointer APT_ 2 c is changed step by step in order to update the profile information in SYN_T, SYN_T old and PD_store; in the same procedure the APT_ 2 b pointer is updated:

decrement APT_ 2 c, load SYN_T, decrement APT_ 2 b by (SYN_T−1) decrement APT_ 2 c, load SYN_T, decrement APT_ 2 b by (SYN_T−1) decrement APT_ 2 c, load SYN_T and PD_store, update SYN_T_old and decrement APT_ 2 b by (SYN_T−1) decrement APT_ 2 c, make calculations, load SYN_T and PD_store, update SYN_T_old and wait for a new TRIGGER event.

Note: The update of SYN_T_old and the loading of PD_store can be performed in all steps above.

Make calculations does mean: the operation of the state machine starts in normal mode at step 1 with the calculations and results in an update of the SYN_T value including the automatic update of SYN_T_old at state 17 using the actual APT_ 2 c address pointer value, see {REF: DPLL_1511}.

The TBU_TB 1 value is to be corrected by the number of pulses sent out in the wrong direction mode during the last increment. This correction is done by sending out SUB_INC 1 pulses for decrementing TBU_TB 1 (while DIR 1 =1).

The amount of pulses is determined by calculation of the difference between NMB_T and INC_CNT 1 . In addition the pulses for the new increment SYN_T_old*(MLT+1) are sent. All pulses are sent out by the maximum possible frequency, because no speed information is available for the first increment after changing the direction.

Consequences for STATE

With the next valid STATE event also DIR 2 is set to 1, after a last increment of APS, APS_ 1 c 3 and APS_ 1 c 2 according to the STATE event. After that with each following valid STATE event APS, APS_ 1 c 3 as well as AP 1 _ 1 c 2 are decremented accordingly as long as DIR 2 =1. The SYN_S value, the APS_ 1 c 3 and APS_ 1 c 2 pointers must be updated accordingly, when a change appears.

decrement APS_ 1 c 3 , load SYN_S, decrement APS_ 1 c 2 by (SYN_S−1) decrement APS_ 1 c 3 , load SYN_S, decrement APS_ 1 c 2 by (SYN_S−1) decrement APS_ 1 c 3 , load SYN_S and PD_S_store, update SYN_S_old and decrement APS_ 1 c 2 by (SYN_S−1) decrement APS_ 1 c 3 , make calculations, load SYN_S and PD_S_store, update SYN_S_old, wait for a new TRIGGER event.

Note: The update of SYN_S_old and the loading of PD_S_store can be performed in all steps above.

When a new STATE event occurs, all address pointers are decremented as long as DIR 2 =1.

Repeated Change to Forward Direction for TRIGGER

The DIR 1 bit remains set as long as the THMI value remains none violated for the following TRIGGER events and is reset when for an invalid TRIGGER slope the THMI is violated and DIR 2 follows the state of DIR 1 with the next valid STATE slope. Resetting the DIR 1 to 0 results (after repeated reset of LOCK 1 , FTD, FSD, NIT, NIS) in the opposite correction of the address pointer use.

This does mean four increment operations of the address pointer including the update of SYN_S and PD_S_store with the automatic update of SYN_S_old.

The correction of TBU_TS 1 is done by sending out the correction pulses with the highest possible frequency at SUB_INC 1 while DIR 1 =0. The number of pulses is calculated by (NMB_T−INC_CNT 1 ) and in addition the pulses for the new increment SYN_T_old*(MLT+1).

Consequences for STATE

For DIR 1 =0: DIR 2 is reset to 0 after the next valid STATE event and after a last decrementing of APS, APS_ 1 c 3 as well as APS_ 1 c 2 . After that the address pointers are incremented again with each following valid STATE event.

Operation in Backward Direction for TRIGGER (SMC=1)

When for SMC=1a backwards condition is detected for the TRIGGER input signal (TDIR=1, resulting in DIR 1 =1 after a last increment of the address pointers), the LOCK 1 bit and the FTD in the DPLL_STATUS register are reset, the NUTE value in NUTC register is set to 1 and the address pointers APT and APT_ 2 c as well as APT_ 2 b are incremented for a last time (and after that decremented for each following valid slope of TRIGGER as long as the DIR 1 bit shows the backward direction).

Please notice, that in the case of the change of the direction the ITN bit in the DPLL_STATUS register is reset.

Profile Update for TRIGGER

Make the same update steps for the profile address pointer as shown in chapter 0 : Decrement APT_ 2 c for 4 times with the update of the SYN_T and PD_store values at each step with an automatic update of SYN_T_old.

The TBU_TB 1 value is to be corrected by the number of pulses sent out in the wrong direction mode during the last increment. This correction is done by sending out SUB_INC 1 pulses for decrementing TBU_TB 1 (while DIR 1 =1).

The amount of pulses is determined by calculation of the difference between NMB_T and INC_CNT 1 . In addition the pulses for the new increment SYN_T_old*(MLS 1 ) are sent. All pulses are sent out by the maximum possible frequency, because no speed information is available for the first increment after changing the direction.

Repeated Change to Forward Direction for TRIGGER

The DIR 1 bit remains set as long as the TDIR bit is set for the following TRIGGER events and is reset when for a valid TRIGGER slope the TDIR is zero. Resetting the DIR 1 to 0 results (after repeated reset of LOCK 1 and FTD) in the opposite correction of the address pointer use.

This does mean four increment operations of the address pointer including the update of SYN_T and PD_store.

The correction of TBU_TS 1 is done by sending out the correction pulses with the highest possible frequency at SUB_INC 1 while DIR 1 =0. The number of pulses is calculated by (NMB_T−INC_CNT 1 ) and in addition the pulses for the new increment SYN_T_old*(MLS 1 ).

Operation in Backward Direction for STATE (SMC=1)

When for SMC=1a backwards condition is detected for the STATE input signal (SDIR=1, resulting in DIR 2 =1 after a last increment of the address pointers), the LOCK 2 bit and the FSD in the DPLL_STATUS register are reset, the NUSE value in NUSC register is set to 1 and the address pointers APS and APT_ 1 c 3 13 f and APT_ 1 c 3 _b as well as APT_ 1 c 2 are incremented for a last time (and after that decremented for each following valid slope of STATE as long as the DIR 2 bit shows the backward direction).

Please notice, that in the case of the change of the direction the ISN bit in the DPLL_STATUS register is reset.

For this transition to the backward direction no change of address pointers APT and APT_ 1 c 2 is necessary.

Profile Update for STATE

Make the same update steps for the profile address pointer as shown in chapter 0 : Decrement APS_ 1 c 3 for 4 times with the update of the SYN_S, SYN_S_old and PD_S_store values at each step.

The TBU_TB 2 value is to be corrected by the number of pulses sent out in the wrong direction mode during the last increment. This correction is done by sending out SUB_INC 2 pulses for decrementing TBU_TB 2 (while DIR 2 =1).

The amount of pulses is determined by calculation of the difference between NMB_S and INC_CNT 2 . In addition the pulses for the new increment SYN_S_old*(MLS 2 ) are sent. All pulses are sent out by the maximum possible frequency, because no speed information is available for the first increment after changing the direction.

Repeated Change to Forward Direction for STATE

The DIR 2 bit remains set as long as the SDIR bit is set for the following STATE events and is reset when for a valid STATE slope SDIR is zero.

Resetting the DIR 2 to 0 results (after repeated reset of LOCK 2 and FSD) in the opposite correction of the address pointer use.

After a last decrementing of all address pointers the APS_ 1 c 3 is incremented 4 times with a repeated update of SYN_S, SYN_S_old and PD_S_store after each increment.

The correction of TBU_TS 2 is done by sending out the correction pulses with the highest possible frequency at SUB_INC 2 while DIR 2 =0. The number of pulses is calculated by (NMB_S−INC_CNT 2 ) and in addition the pulses for the new increment SYN_S_old*(MLS 2 ).

DPLL Reaction in the Case of Non Plausible Input Signals

When the DPLL is synchronized concerning the TRIGGER signal by setting the FTD, SYT and LOCK 1 bits in the DPLL_STATUS register, the number of valid TRIGGER events between the gaps is to be checked continuously.

When additional events appear while a gap is expected, the LOCK 1 bit is reset and the ITN bit in the DPLL_STATUS register is set. In that case the state machine 1 will remain in state 1 and the address pointer APT, APT_ 2 c and APT_ 2 c will remain unchanged until the CPU sets the APT_ 2 c accordingly. In this case also the NUTE value in the NUTC register is set to 1 . The DPLL stops the generation of the SUB_INC 1 pulses and will perform no other actions—remaining in step1 of the first state machine (see {REF: DPLL —1511}).

When an unexpected gap appears (missing TRIGGERS), the NUTE value in the NUTC register is set to 1, the LOCK 1 bit is reset and the ITN bit in the DPLL_STATUS register is set. The address pointers are incremented with the next valid TRIGGER slope accordingly.

When in the following the direction DIR 1 changes as described in the chapters above the ITN bit in the DPLL_STATUS register is reset, the use of the address pointers APT_ 2 c is switched and the pulse correction takes place as described above.

In all other cases the CPU can interact to leave the instable state. This can be done by setting the APT_ 2 c address pointer which results in a reset of the ITN bit. In the following NUTE can also be set to higher values.

When the DPLL is synchronized concerning the STATE signal by setting the FSD, SYS and LOCK 2 bits in the DPLL_STATUS register, the number of valid STATE events between the gaps is to be checked continuously.

When additional events appear while a gap is expected or while SMC=0 an unexpected missing STATE event appears, the LOCK 2 bit is reset and the ISN bit in the DPLL_STATUS register is set. In that case the state machine 2 will remain in state 21 and the address pointer APS, APS_ 1 c 3 and APS_ 1 c 3 will remain unchanged until the CPU sets the APT_ 1 c 3 accordingly. In this case also the NUSE value in the NUSC register is set to 1. The DPLL stops the generation of the SUB_INC 1 or 2 pulses respectively, when the RMO bit is set, and will perform no other actions—remaining in step 21 of the second state machine.

When an unexpected gap appears for RMO=SMC=1 (missing STATEs for synchronous motor control), the NUSE value in the NUSC register is set to 1, the LOCK 2 bit is reset and the ISN bit in the DPLL_STATUS register is set. The address pointers are incremented with the next valid STATE slope accordingly.

When in the following the direction DIR 2 changes as described in the chapters above the ISN bit in the DPLL_STATUS register is reset, the use of the address pointers APT_ 1 c 3 is switched and the pulse correction takes place as described above. In all other cases the CPU must interact to leave the instable state. This can be done by setting the APT_ 1 c 3 address pointers which results in a reset the ISN bit. In the following NUSE can also be set to higher values.

State Description of the State Machine.

Step Description Comments always for each invalid TRIGGER slope: for SMC = 0; for generate the TIS interrupt; calculate set DIR1 always after DEN = 1 the time stamp difference to the last inc./decr. the address valid event, store this value at pointers APT, APT_x; THVAL go to step 1; when THMI is violated (ΔT < THMI): stop output of SUB_INC1 generate TIN interrupt, and correct pulses after set DIR1 = 0 (forwards) changing DIR1 after set BWD1 = 0 (see DPLL_STATUS incr./decr. of APS,_x register) set DIR2 always after else incr./decr. the address set DIR1 = 1 (backwards); pointers APS, APS_x; set BWD1 = 1 (see DPLL_STATUS go to step 1 register) after changing the direction correct the pulses sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency for each invalid STATE slope: set DIR2 = DIR1 always set DIR1 = BWD1 = TDIR, for SMC = 1; for set DIR2 = BWD2 = SDIR; set the direction bits DEN = 1 for each change of TDIR go to step always after incr./decr. 1 after performing the calculations the corresponding and update of SYN_T, PD_store address pointers; and correct the pulses sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency. for each change of SDIR go to step 21 after performing the calculations and the update of SYN_S, PD_S_store and correct the pulses sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency.  1 When DEN = 1 and TEN = 1: wait for Depending on TSL, TEN, T_VALID, DEN the leaving of step when no T_VALID appears until one is done with the next THMA is reached, generate the TRIGGER input; TAX interrupt; Note: Step 1 is also left when a T_VALID appears: compare in emergency mode TRIGGER_S with TSL (valid when a valid TRIGGER slope); event appears in order to When no valid TRIGGER appears make a switch back to and when TS_T_CHECK time is normal mode possible; reached: _old - values are values send missing TRIGGER INT, when valid at the last but one no Gap exist; set MT = 1 (missing valid TRIGGER event; TRIGGER bit) in the for the whole table: use DPLL_STATUS register; do not always MLS1 instead of leave step 1 until a valid (MLT + 1) for the case TRIGGER appears. SMC = 1; When a valid TRIGGER appears decrement does mean: check PVT increment for DIR1 = 0 when the PVT value is violated: decrement for DIR1 = 1 generate the PWI interrupt, ignore SYN_T_old is still not the TRIGGER input and wait for updated the next T_VALID event; do not replace MLT + 1 by MLS1 store any value for SMC = 1 When the PVT value is fulfilled: replace MLT + 1 by MLS1 store actual position stamp at for SMC = 1 PSTM; SYN_T is still not store all relevant configuration bits X updated of the DPLL_CTRL(0, 1) * ) replace (MLT + 1) by Registers in shadow registers MLS1 for SMC = 1: and consider them for all corresponding calculations of steps 2 to 17 accordingly; the relevant bits are explained in the registers itself generate the TAS interrupt when NTI_CNT is zero or decrement NTI_CNT when not zero; for FTD = 0: set PSTC = PSTM set FTD (first TRIGGER detected) do not change PSTC, APT, APT_2b for RMO = 0 or SMC = 1: increment INC_CNT1 by (MLT + 1)* ) send SUB_INC1 pulses with highest possible frequency for SYT = 0 and FTD = 1: decrement APT and APT_2b by one; decrement PSTC by (MLT + 1)* ) for RMO = 0 or SMC = 1: increment INC_CNT1 by (MLT + 1)* ) for SYT = 1 and ITN = 0: decrement APT, APT_2c, decrement APT_2b by SYN_T_old decrement PSTC by SYN_T_old * (MLT + 1)* ) + PD_store_old for RMO = 0 or SMC = 1: increment INC_CNT1 by SYN_T * (MLT + 1) + PD_store within the DPLL_STATUS register: set LOCK1 bit accordingly;  2 calculate TS_T according to equations 16.1a; calculate DT_T_actual = TS_T − TS_T_old calculate RDT_T_actual calculate QDT_TX according to equation 16.2  3 send CDIT interrupt; calculate EDT_T and MEDT_T according to equations 16.3 and 16.4 for (RMO = 1 and SMC = 0): update the RAM by equation 16.a-c (see chapter 0); go back to step 1 for (RMO = 1 and SMC = 0); update SYN_T and PD_store only in that case  4 calculate CDT_TX according to for RMO = 0 or SMC = 1; equation 16.5a and b;  5 calculate missing pulses; for RMO = 0 or SMC = 1 for a current correction of missing or * ) replace (MLT + 1) by surplus pulses use the correction MLS1 for SMC = 1 value MPVAL1, used by CPU also add MPVAL1 only for when switched modes; PCM = 1; add MPVAL1 MP = SYN_T_old * (MLT + 1)* ) + once to INC_CNT1 and PD_store_old − (PSTM − PSTM_old) + reset PCM1 after that MP_old + MPVAL1; (PD_store_old is zero for AMT = 0)  6 sent MP with highest possible for RMO = 0 or SMC = 1, frequency DMO = 0 and COA = 0 and calculate * ) replace (MLT + 1) by NMB_T = (MLT + 1)* ) * SYN_T + MLS1 for SMC = 1 PD_store (PD_store is zero for AMT = 0) 7 calculate number of pulses to be for RMO = 0 or SMC = 1, sent DMO = 0 and COA = 1 NMB_T = (MLT + 1)* ) * SYN_T + * ) replace (MLT + 1) by PD_store + MP (see equations MLS1 for SMC = 1 16.21 or 16.27 respectively) (PD_store is zero for AMT = 0)  8 NMB_T = SYN_T * CNT_NUM_1 for RMO = 0 or SMC = 1, DMO = 1  9 no operation 10 calculate ADD_IN_CAL_N for RMO = 0 or SMC = 1 according to equation 16.25 or for DLM = 0 16.31 and store this value in RAM for DLM = 1 use ADD_IN_CAL_N as ADD_IN value for the case DLM = 0 use ADD_IN_LD_N as ADD_IN for the case DLM = 1, for DMO = 0 and EN_C1u = 0: reset the FlipFlops in the SUB_INC1 generator; start sending SUB_INC1; 11 calculate for RMO = 0 or SMC = 1; TS_T_CHECK = TS_T + DT_T_actual * (TOV); 12 automatic setting of actions masking steps 12 to 16 are not bits in the DPLL_STATUS register: valid for the combination: for SMC = 0: set CAIP1 = CAIP2 = 1 (SMC = 0 and RMO = 1) for SMC = 1: set only CAIP1 = 1 13 for all correspondent actions with actions 0 . . . 11 for SMC = 1 ACT_Ni = 1 calculate: actions 0 . . . 24 for SMC = 0 NAi with depending on ACT_Ni in w = (PSAi − PSTC)/(MLT + 1)* ) as DPLL_ACT_STA integer part and register; b = remainder of the division replace MLT + 1 by MLS1 (fractional part) for SMC = 1 14 calculate PDT_Ti and DTAi for up to actions 0 . . . 11 for SMC = 1 24 action values according to actions 0 . . . 24 for SMC = 0 equations 16.11 and 16.12; 15 calculate TSAi according to equation actions 0 . . . 11 for SMC = 1 16.15 and PSACi according to actions 0 . . . 24 for SMC = 0 equation 16.17 16 automatic resetting of actions Set ACT_Ni for all masking bits in the DPLL_STATUS enabled actions register: concerned: for SMC = 0: set CAIP1 = CAIP2 = 0 0 . . . 11 for SMC = 1 for SMC = 1: set only CAIP1 = 0; 0 . . . 24 for SMC = 0 set the corresponding ACT_Ni bits in the DPLL_ACT_STA register 17 store TS_T in RAM 2b according to for all conditions APT_2b; update RAM 2a and RAM 2d update SYN_T and PD_store; go back to step 1 21 When DEN = 1 and SEN = 1: wait for Depending on SSL, SEN, S_VALID, compare STATE_S DEN the leaving of step with SSL (valid slope); for each 21 one is done with the invalid slope: generate a SIS next STATE input; interrupt; for the steps 22-37: for send missing STATE INT when SMC = 1 replace: TS_S_CHECK time is reached MLS1 by MLS2, and set MS = 1 (missing STATE LOCK1 by LOCK2; bits) in that case; do not leave SUB_INC1 by step 21 while no valid STATE SUB_INC2; appears. CNT_NUM_1 by When a valid STATE appears: CNT_NUM_2; store actual position stamp at PSSM MPVAL1 by MPVAL2; store all relevant configuration bits X EN_C1u by EN_C2u; of the DPLL_CTRL(0,1) decrement does mean: Registers in shadow registers increment for DIR2 = 0 and consider them for all decrement for DIR2 = 1 corresponding calculations of steps 22 to 37 accordingly; the relevant bits are explained in the registers itself for FSD = 0: set PSSC = PSSM set FSD (first STATE detected) do not increment PSSC for RMO = 1 and SMC = 0: increment INC_CNT1 by MLS1 for RMO = 1 and SMC = 1: increment INC_CNT2 by MLS2 for SYS = 0 and FSD = 1: decrement PSSC by MLS1 (SMC = 0) or MLS2 (SMC = 1) increment INC_CNT1 by MLS1 (for SMC = 0 and RMO = 1); increment INC_CNT2 by MLS2 (for SMC = 1 and RMO = 1); decrement APS and APS_1c3 decrement APS_1c2 by SYN_S_old for SYS = 1 and ISN = 0: decrement APS and APS_1c3 decrement APS_1c2 by SYN_S_old for RMO = 1 and SMC = 0: decrement PSSC by SYN_S_old * MLS1 + PD_S_store_old, increment INC_CNT1 by SYN_S * MLS1 + PD_S_store for RMO = 1 and SMC = 1: decrement PSSC by SYN_S_old * MLS2 + PD_S_store_old, increment INC_CNT2 by SYN_S * MLS2 + PD_S_store within the DPLL_STATUS register: set LOCK1 or 2 bit accordingly; 22 calculate TS_S according to equations 16.6a; calculate DT_S_actual = TS_S − TS_S_old calculate RDT_S_actual calculate QDT_SX 23 send CDIS interrupt; calculate EDT_S and MEDT_S according to equations 16.8 and 16.9 for RMO = 0: update RAM by equation 16.7c (see chapter 0); go back to step 21 for RMO = 0 and update SYN_S and PD_S_store using the current ADT_Si values in that case; 24 calculate CDT_SX according to only for RMO = 1 equation 16.10a and b; 25 calculate missing pulses only for RMO = 1 for a current correction of missing or add MPVAL1/2 once to surplus pulses use the correction INC_CNT1/2 and reset value MPVAL1 (MPVAL2), used by PCM1/2 after that CPU also when switched modes; SMC = 0: add MPVAL1 MP = SYN_S_old * MLS1 + only for PCM1 = 1 PD_S_store_old − (PSSM − SMC = 1: add MPVAL2 PSSM_old) − MP_old + MPVAL1; only for PCM2 = 1 MP = SYN_S_old * MLS2 + PD_S_store_old − (PSSM − PSSM_old) − MP_old + MPVAL2; (PD_S_store_old is zero for AMS = 0 26 sent MP with highest possible only for RMO = 1, frequency and calculate DMO = 0 and COA = 0 NMB_S = MLS1 + PD_S_store for SMC = 0 NMB_S = MLS2 + PD_S_store for SMC = 1 (PD_S_store is zero for AMS = 0 27 calculate number of pulses to be only for RMO = 1, sent according to 16.22 or DMO = 0 and COA = 1 NMB_S = MLS1 * SYN_S + for SMC = 0; PD_S_store + MP for SMC = 1; NMB_S = MLS2 * SYN_S + PD_S_store + MP (PD_S_store is zero for AMS = 0;) 28 NMB_S = SYN_S * CNT_NUM_1 only for RMO = 1, (SMC = 0) DMO = 1 and COC = 0 NMB_S = SYN_S * CNT_NUM_2 (SMC = 1) 29 Go to step 30 no operation 30 calculate ADD_IN_CAL_E according only for RMO = 1 to equation 16.26 or 16.31 for DLM = 0 respectively and store this value in for DLM = 1 RAM use ADD_IN_CAL_E as ADD_IN value for the case DLM = 0 use ADD_IN_LD_E as ADD_IN for the case DLM = 1 for RMO = 1, DMO = 0 and EN_C1u = 0 (EN_C1u = 0): reset the FlipFlops in the SUB_INC1 or SUB_INC2 generator respectively; start sending SUB_INC1/ SUB_INC2; 31 calculate only for RMO = 1; TS_S_CHECK = TS_S + DT_S_actual * (TOV_S); 32 automatic setting of actions masking for RMO = 1 bits in the DPLL_STATUS register: CAIP1 and CAIP2 for SMC = 0 only CAIP2 for SMC = 1 33 for all actions with ACT_Ni = 0 for SMC = 0: 24 actions, calculate: for SMC = 1: 12 actions; NAi with w = (PSAi − PSSC)/MLS1 depending on ACT_Ni in as integer part and DPLL_ACT_STA b = remainder of the division register (fractional part) use MLS2 as divider in the case of SMC = 1 34 calculate PDT_Si and DTAi for up to only for RMO = 1; 24 action values according to for SMC = 0 actions 0 . . . 23 equations 16.13 and 16.14; for SMC = 1 actions 12 . . . 23 35 calculate TSAi according to equation for the relevant actions 16.18 and PSACi according to (see above) and RMO = 1 equation 16.20 36 automatic reset of the actions for the relevant actions masking bit CAIP in the (see above) and RMO = 1 DPLL_STATUS register: Set ACT_Ni and reset CAIP1 = CAIP2 = 0 for SMC = 0 and ACT_WRi for all enabled only CAIP2 = 0 for SMC = 1 actions set the corresponding ACT_Ni bits in the DPLL_ACT_STA register 37 store TS_S in RAM 1c2 according to for all conditions APT_1c2; update RAM 1c1 and RAM 1c4 update SYN_S and PD_S_store; go back to step 21

DPLL Interrupt Signals

The DPLL provides 24 interrupt lines. These interrupts are shown below.

DPLL Interrupt Signals

Signal Description DPLL_CDI_IRQ TRIGGER duration calculated for last increment DPLL_TE5_IRQ TRIGGER event interrupt 5 request 3) DPLL_TE4_IRQ TRIGGER event interrupt 4 request 3) DPLL_TE3_IRQ TRIGGER event interrupt 3 request 3) DPLL_TE2_IRQ TRIGGER event interrupt 2 request 3) DPLL_TE1_IRQ TRIGGER event interrupt 1 request 3) DPLL_LL2_IRQ Lost of lock interrupt for SUB_INC2 request DPLL_GL2_IRQ Get of lock interrupt for SUB_INC2 request DPLL_E_IRQ Error interrupt request DPLL_LL1_IRQ Lost of lock interrupt for SUB_INC1 request DPLL_GL1_IRQ Get of lock interrupt for SUB_INC1 request DPLL_W1_IRQ Write access to RAM region 1b or 1c interrupt request DPLL_W2_IRQ Write access to RAM region 2 interrupt request DPLL_PW_IRQ Plausibility window violation interrupt of TRIGGER request DPLL_TAS_IRQ TRIGGER active slope while NTI_CNT is zero interrupt request DPLL_SAS_IRQ STATE active slope interrupt request DPLL_MT_IRQ Missing TRIGGER interrupt request DPLL_MS_IRQ Missing STATE interrupt request DPLL_TIS_IRQ TRIGGER inactive slope interrupt request DPLL_SIS_IRQ STATE inactive slope interrupt request DPLL_TAX_IRQ TRIGGER maximum hold time violation interrupt request DPLL_TIN_IRQ TRIGGER minimum hold time violation interrupt request DPLL_PE_IRQ DPLL enable interrupt request DPLL_PD_IRQ DPLL disable interrupt request Note: TEi_IRQ depends on the TINT value in ADT_Ti 1) and is only active when ADTV 2) = 1. 1) see RAM region 2 explanation 2) see DPLL STATUS register 3) see TINT value in the corresponding ADT_Ti section of RAM region 2

DPLL Register Overview

DPLL Register Overview

RAM Region 1 map description.

RAM Region 2 map description.

Address Name Description offset RAM Region 2 0x4000-0x7FFC NOTE: the following registers for the size from signal TRIGGER are located in RAM 1.5 kBytes to region 2, read access by AEI via bus 12 kBytes interface possible, write access configurable for results in an interrupt, when word sizes of 24 enabled; Bits data width of 3 bytes used for 24 bit values The RAM field part contains up to 1024 values and all are configurable for 128, 256, 512 or 1024 values in order to select the RAM size needed Region 2a Reciprocal values of the AOSV_2i values corresponding successive are addresses increments RDT_Ti (see after shift left by equations 16.2a,b); 8 address offsets are given by the AOSR0 . . .3 RDT_T0 RDT_T0 AOSV_2a RDT_T1 RDT_T1   +4 . . . . . . 2 * (TNU + 1 − SYN_NT) valid . . . entries RDT_T1023 RDT_T1023 +4092 Region 2b Time stamp field for all TRIGGER events in FULL_SCALE; 24 bit time stamp values TSF_T0 TSF_T0 AOSV_2b TSF_T1 TSF_T1   +4 . . . . . . 2 * (TNU + 1) valid entries . . . TSF_T1023 TSF_T1023 +4092 Region 2c ADT_T values to correct the measured TRIGGER signal values; time stamp values bits 24-27 in addition to the 24 bit value of TSF_Tx, stored in the bits 23:20 of ADT_Ti ADT_T0 ADT_T0 AOSV_2c ADT_T1 ADT_T1   +4 . . . . . . 2 * (TNU + 1 − SYN_NT) valid . . . entries ADT_T1023 ADT_T1023 +4092 Region 2d Uncorrected last increment values of TRIGGER (DT_T); measuring raw data of increments DT_T0 DT_T0 AOSV_2d DT_T1 DT_T1   +4 . . . . . . 2 * (TNU + 1 − SYN_NT) valid . . . entries DT_T1023 DT_T1023 +4092

DPLL Register Description

DPLL RAM Region is Value Description

DPLL RAM Region 1 b Value Description

DPLL RAM Region is Value Description

DPLL RAM Region 2 Value Description

Sensor Pattern Evaluation (SPE)

Overview

The Sensor Pattern Evaluation (SPE) sub module can be used to evaluate three hall sensor inputs and together with the TOM module to support the drive of BLDC engines. Thus, the input signals are filtered already in the connected TIM channels. In addition, the SPE sub module can be used as an input stage to the MAP sub module if the DPLL should be used to calculate the rotation speed of one or two electric engine(s). The integration of the SPE sub module into the overall GTM-IP architecture concept is shown in FIG. 53 .

SPE Sub Module Integration Concept into GTM-IP

See FIG. 53 .

As mentioned above, the SPE sub module can determine a rotation direction out of the combined TIM[i]_CHx(48), TIM[i]_CHy(48) and TIM[i]_CHz(48) signals. On this input signals a pattern matching algorithm is applied to generate the SPEx_DIR signal on behalf of the temporal relation between these input patterns. A possible sample pattern of the three input signals is shown in FIG. 54 . In general, the input pattern is programmable within the SPE sub module.

SPE Sample Input Pattern for TIM[i]_CH[x,y,z](48)

See FIG. 54 .

In FIG. 54 the input signals define the pattern from the input sensors which have a 50% high and 50% low phase. The pattern according to FIG. 54 is as follows:

100 - 110 - 010 - 011 - 001 - 101 - 100

where the first bit (smallest circle) represents TIM[i]_CH[x](48), the second bit represents TIM[i]_CH[y](48), and the third bit (greatest circle) represents TIM[i]_CH[z](48).

Note that the SPE module expects that with every new pattern only one of the three input signals changes its value.

SPE Sub Module Description

The SPE sub module can handle sensor pattern inputs. Every time if one of the input signals TIM[i]_CH[x](48), TIM[i]_CH[y](48) or TIM[i]_CH[z](48) changes its value, a sample of all three input signals is made. Derived from the sample of the three inputs the encoded rotation direction and the validity of the input pattern sequence can be detected and signalled. When a valid input pattern is detected, the SPE sub module can control the outputs of a dedicated connected TOM sub module. This connection is shown in FIG. 55 .

SPE to TOM Connections

See FIG. 55 .

The TOM[i]_CH 0 _TRIG_CCU[x] and TOM[i]_CH[x]_SOUR signal lines are used to evaluate the current state of the TOM outputs, whereas the SPE[i]_OUT output vector is used to control the TOM output depending on the new input pattern. The SPE[i]_OUT output vector is defined inside the SPE sub module in a pattern definition table SPE[i]_OUT_PAT[x]. The internal SPE sub module architecture is shown in FIG. 56 .

SPE Sub Module Architecture

See FIG. 56 .

The SPE[i]_PAT register holds the valid input pattern for the three input patterns TIM[i]_CH[x](48), TIM[i]_CH[y](48) and TIM[i]_CH[z](48). The input pattern is programmable. The valid bit shows if the programmed pattern is a valid one. FIG. 57 shows the programming of the SPE[i]_PAT register for the input pattern defined in FIG. 54 .

The rotation direction is determined by the order of the valid input pattern. This rotation direction defines if the SPE_PAT_PTR is incremented (DIR=0) or decremented (DIR=1). Whenever a valid input pattern is detected, the NIPD signal is raised, the SPE_PAT_PTR is incremented/decremented and a new output control signal SPE[i]_OUT(x) is send to the corresponding TOM sub module.

The TOM[i]_CH 2 with i=0 . . . 3 can be used together with the SPE module to trigger a delayed update of the SPE_OUT_CTRL register after new input pattern detected by SPE (signalled by SPE[i]_NIPD).

To do this, the TOM[i]_CH 2 has to be configured to work in one-shot mode (set bit OSM in register TOM[i]_CH 2 _CTRL). The SPE mode of this channel has to be enabled, too (set bit SPEM in register TOM[i]_CH 2 _CTRL). The SPE module has to be configured to update SPE_OUT_CTRL on TOM[i]_CH 2 _TRIG_CCU 1 (set in SPE[i]_CTRL_STAT bits TRIG_SEL to ‘11’). Then, on new input detected by SPE, the signal SPE[i]_NIPD triggers the start of the TOM channel 2 to generates one PWM period by resetting CN 0 to 0. On second PWM edge triggered by CCU 1 of TOM channel 2, the signal TOM[i]_CH 2 _TRIG_CCU 1 triggers the update of SPE_OUT_CTRL.

According to FIG. 56 , the two input patterns “000” and “111” are not allowed combinations and will end in a SPE[i]_PERR interrupt. These two patterns can be used to determine a sensor input error. A SPE[i]_PERR interrupt will also be raised, if the input patterns occur in a wrong order, e.g. if the pattern “010” does not follow the pattern “110” or “011”.

The register SPE[i]_IN_PAT bit field inside the SPE[i]_CTRL_STAT register is implemented, where the input pattern history is stored by the SPE sub module. The CPU can determine a broken sensor when the SPE[i]_PERR interrupt occurs by analysing the bit pattern NIP inside the SPE[i]_CTRL_STAT register. The input pattern in the SPE[i]_CTRL_STAT register is updated whenever a valid edge is detected on one of the input lines TIM[i]_CH[x](48), TIM[i]_CH[y](48) or TIM[i]_CH[z](48). The pattern bit fields are then shifted. The input pattern history generation inside the SPE[i]_CTRL_STAT register is shown in FIG. 57 .

Additionally to the sensor pattern evaluation the SPE module also provides the feature of fast shut-off for all TOM channels controlled by the SPE module. The feature is enables by setting bit FSOM in register SPE[i]_CTRL_STAT. The fast shut-off level itself is defined in the bit field FSOL of register SPE[i]_CTRL_STAT. The TIM input used to trigger the fast shut-off is either TIM channel 6 or TIM channel 7 depending on the TIM instance connected to the SPE module. For details of connections please refer to FIG. 53 .

SPE[i]_IN_PAT Register Representation

See FIG. 57 .

The CPU can disable one of the three input signals, e.g. when a broken input sensor was detected, by disabling the input with the three input enable bits SIE inside the SPE[i]_CTRL_STAT register.

Whenever at least one of the input signal TIM[i]_CH[x](48), TIM[i]_CH[y](48) or TIM[i]_CH[z](48) changes the SPE sub module stores the new bit pattern in an internal register NIP (New Input Pattern). If the current input pattern in NIP is the same as in the Previous Input Pattern (PIP) the direction of the engine changed, the SPEC[i]_DCHG interrupt is raised, the direction change is stored internally and the pattern in the PIP bit field is filled with the AIP bit field and the AIP bit field is filled with the NIP bit field. The SPE[i]_DIR bit inside the SPE[i]_CTRL_STAT register is toggled and the SPE[i]_DIR signal is changed.

If the SPE encounters that with the next input pattern detected new input pattern NIP the direction change again, the input signal is categorized as bouncing and the bouncing input signal interrupt SPE[i] BIS is raised.

Immediately after update of register NIP, when the new detected input pattern doesn't match the PIP pattern (i.e. no direction change was detected), the SPE shifts the value of register AIP to register PIP and the value of register NIP to register AIP. The SPE[i] NIPD interrupt is raised.

The number of the channel that has been changed and thus leads to the new input pattern is encoded in the signal SPE[i]_NIPD_NUM.

If a sensor error was detected, the CPU has to define upon the pattern in the SPE[i]_CTRL_STAT register, which input line comes from the broken sensor. The faulty signal line has to be masked by the CPU and the SPE sub module determines the rotation direction on behalf of the two remaining TIM[i]_CH[x] input lines.

The pattern history can be determined by the CPU by reading the two bit fields AIP and PIP of the SPE[i]_CTRL_STAT register. The AIP register field holds the actual detected input pattern at TIM[i]_CH[x](48), TIM[i]_CH[y](48) and TIM[i]_CH[z](48) and the PIP holds the previous detected pattern.

After reset the register NIP, AIP and PIP as well as the register SPE[i]_PAT_PTR and SPE[i]_OUT_CTRL will not contain valid start-up values which would allow correct behaviour after enabling SPE and detecting the first input patterns.

Thus, it is necessary to initialize these register to correct values.

To do this, before enabling the SPE, the bit field NIP of register SPE[i]_CTRL_STAT can be read and depending on this value the initialization values for the register AIP, PIP, SPT_PAT_PTR and SPE[i]_OUT_CTRL can be determined.

SPE Interrupt Signals

The following table describes SPE interrupt signals:

Signal Description SPE[i]_NIPD SPE New valid input pattern detected. SPE[i]_DCHG SPE Rotation direction change detected on behalf of input pattern. SPE[i]_PERR SPE Invalid input pattern detected. SPE[i]_BIS SPE Bouncing input signal detected at input.

SPE Register Overview

The following table shows an overview about the SPE register set.

Details in Register name Description Section SPE[i]_CTRL_STAT SPE Control status register 0 SPE[i]_PAT SPE Input pattern definition 0 register. SPE[i]_OUT_PAT[x] SPE Output definition 0 registers. (x: 0 . . .7) SPE[i]_OUT_CTRL SPE output control register 0 SPE[i]_IRQ_NOTIFY SPE Interrupt notification 0 register. SPE[i]_IRQ_EN SPE Interrupt enable register. 0 SPE[i]_IRQ_FORCINT SPE Interrupt generation by 0 software. SPE[i]_IRQ_MODE IRQ mode configuration 0 register

SPE Register Description

Output Compare Unit (CMP)

Overview

The Output Compare Unit (CMP) is designed for the use in safety relevant applications. The main idea is to have the possibility to duplicate outputs in order to be compared in this unit. Because of the simple EXOR function used it is necessary to ensure the total cycle accurate output behaviour of the output modules to be compared. This is given when two ATOM units produce output signals at the same time stamp or when two TOMs have the same configuration and start their output generation at the same time. This is possible by means of the trigger mechanisms TRIG_x provided by the TOMs as shown in the chapter 0 (TOM Block Diagram). It is not necessary to compare each output channel with each other.

The CMP enables the comparison of 2×24 channels of the TOM and ATOM units respectively and is restricted to neighbour channels. Thus, channel 0 is compared with channel 1, channel 2 with 3 and so on until the comparison of channel 22 with channel 23.

Selection of the First 24 TOM and ATOM Outputs for Comparison

See FIG. 58 .

Architecture of the Compare Unit

See FIG. 59 .

Bitwise Compare Unit (BWC)

The Bitwise Compare Unit compares in pairs the combinations shown in following table

TBWC/ABWC Compare Compare Comparator TOM/ATOM Bit TOM/ATOM Bit Number Number one Number Two Output Number 0 0 1 0 1 2 3 1 2 4 5 2 3 6 7 3 4 8 9 4 5 10 11 5 6 12 13 6 7 14 15 7 8 16 17 8 9 18 19 9 10 20 20 10 11 22 23 11

Configuration of the Compare Unit

Because of the restrictions described in the section above the Compare Unit consists of 24 antivalence (EXOR) elements, a select register CMP_EN which selects the corresponding comparisons and a status register CMP_IRQ_NOTIFY which shows and stores each mismatching result, when selected.

For each mismatching error an interrupt is generated, which can result in an undelayed reaction of the CPU.

An additional interrupt enable register prevents the interrupt generation for test purposes.

Error Generator

The error generator generates an error signal to be transmitted directly to the MON unit and independently from the CMP_IRQ. The error is set when in the status register at least one bit is set.

The CMP_ERR output reflects its status in the main status register of the Monitor Unit, which is to be polled by the CPU.

CMP Interrupt Signals

The CMP sub module has two interrupt signals. The source of both interrupts can be determined by reading the CMP_IRQ_NOTIFY status register for CMP_ERR interrupt line and under consideration of CMP_IRQ_EN register for CMP_IRQ interrupt line. Each source can be forced separately for debug purposes using the interrupt force CMP_IRQ_FORCINT register.

Signal Description CMP_IRQ Mismatching interrupt of outputs to be compared CMP_ERR Not maskable mismatching interrupt of outputs to be compared

CMP Configuration Registers Overview

CMP contains following configuration registers:

Register Name Description Details in Section CMP_EN Comparator enable 0 register CMP_IRQ_NOTIFY Event notification 0 register CMP_IRQ_EN Interrupt enable 0 register CMP_IRQ_FORCINT Interrupt force register 0 CMP_IRQ_MODE IRQ mode 0 configuration register

CMP Configuration Registers Description

Monitor Unit (MON)

Overview

The Monitor Unit (MON) is designed for the use in safety relevant applications. The main idea is to have a possibility to supervise common used circuitry and resources. In this way the activity of the clocks as well as the basic activity of the ARU is supervised.

Clock and Time Base Monitoring

The monitor unit has a connection to each of the 8 clocks CMU_CLK 0 , . . . CMU_CLK 7 , provided by the CMU. Some of these clocks can be used for special tasks (see chapter 0 ).

In addition the 5 clock inputs of the TOMs CMU_FXCLK(4:0) are also connected to the MON unit.

The supervising of the clocks is done by scanning for activity of each clock.

When a valid slope at the clock is detected, the corresponding bit in the status register MON_STATUS is set.

As valid slope a high-low slope is defined. Reading this status register resets all its bits to zero.

When the register is polled by the CPU and the time between two read accesses is higher than the period of the slowest clock, all bits of the corresponding clocks must be set.

When polling in shorter time distances, not for all clocks an activity can be shown, although they are still working.

In addition by the use of a select register only the selected bits are to be considered.

ARU Monitoring

Because the ARU is a common used module for routing the data the operation out of control can have an essential impact on more than one connected module. Therefore, it is important to have information about the basic activity of the ARU.

Each of the ARUs used sends a high level signal, when the first destination address is selected. This is performed by the ARUx_zero signal, when the ARU select counter has a zero value.

Detecting a high-low slope at this signal in the activity checker circuit sets the corresponding status bit ACT_ARUx. This is a simple possibility to check, if the corresponding ARU is working or not.

In order to check the correct cycle time of the ARU some features of the MCS sub module can be used as described in the following chapter.

Checking ARU Cycle Time and Expected Signal Durations

The cycle time of the ARU can be checked, when this is essential for safety purposes. This check can be performed by a MCS channel.

The resulting error is reported to the MON unit using the MCS_ERRx signal in addition to an interrupt, generated in MCS.

The corresponding MCS is programmed to get a fixed data value at address 0x1FF. The data value is always zero and is not blocked. When getting the access the time stamp value TBU_TS 0 is stored in a register. The next time getting the access the new TBU_TS 0 value is stored and the difference between both values is compared with a given value. When the comparison fails, an error flag is set in the status register, an interrupt is generated and the error signal MCS_ERR is provided.

In a similar way the duration of a signal can be checked.

The signal to be checked can be an output signal of the GTM or an arbitrary other signal.

The signal values can be checked involving given tolerances.

When the check fails, an error flag is set in the status register, an interrupt is generated and the error signal MCS_ERR is provided for the MON unit.

FIG. 60 shows the block diagram of the Monitor Unit.

MON Block Diagram

See FIG. 60 .

MON Interrupt Signals

The MON sub module has no interrupt signals.

MON Configuration Registers Overview

Following configuration registers are considered in MON sub module

Register Name Description Details in Section MON_STATUS Monitor Status register 0

MON Configuration Registers Description

Register MON_STATUS Address Offset: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 Bit Reserved MCS_ERR3 MCS_ERR2 MCS_ERR1 MCS_ERR0 Reserved Mode R RCw RCw RCw RCw R Initial 0x00 0 0 0 0 0X00 Value Address Offset: 0x00 Initial Value: 0x0000_0000 18 17 16 15 14 13 12 11 10 Bit Reserved CMP_ERR Reserved ACT_CMUFX4 ACT_CMUFX3 ACT_CMUFX2 Mode R RCw R RCw RCw RCw Initial 0x00 0 0x00 0 0 0 Value Initial Value: 0x0000_0000 9 8 7 6 5 Bit ACT_CMUFX1 ACT_CMUFX0 ACT_CMU7 ACT_CMU6 ACT_CMU5 Mode RCw RCw RCw RCw RCw Initial 0 0 0 0 0 Value Initial Value: 0x0000_0000 4 3 2 1 0 Bit ACT_CMU4 ACT_CMU3 ACT_CMU2 ACT_CMU1 ACT_CMU0 Mode RCw RCw RCw RCw RCw Initial 0 0 0 0 0 Value Bit 0 ACT_CMU0: CMU_CLK0 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 1 ACT_CMU1: CMU_CLK1 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 2 ACT_CMU2: CMU_CLK2 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 3 ACT_CMU3: CMU_CLK3 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 4 ACT_CMU4: CMU_CLK4 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 5 ACT_CMU5: CMU_CLK5 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 6 ACT_CMU6: CMU_CLK6 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 7 ACT_CMU7: CMU_CLK7 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 8 ACT_CMUFX0: CMU_CLKFX0 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 9 ACT_CMUFX1: CMU_CLKFX1 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 10 ACT_CMUFX2: CMU_CLKFX2 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 11 ACT_CMUFX3: CMU_CLKFX3 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 12 ACT_CMUFX4: CMU_CLKFX4 activity Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Note: Bits 0 to 12 are set, when a high low slope is detected at the considered clock Bit 15:13 Reserved: Reserved bits Note: Read as zero should be written as zero Bit 16 CMP_ERR: Error detected at CMP Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 19:17 Reserved: Reserved bits Note: Read as zero should be written as zero Bit 20 MCS_ERR0: Error detected at MCS 0 Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 21 MCS_ERR1: Error detected at MCS 1 Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 22 MCS_ERR2: Error detected at MCS 2 Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 23 MCS_ERR3: Error detected at MCS 3 Note: This bit will be cleared on a CPU write access of value ‘1’. A read access leaves the bit unchanged. Bit 31:24 Reserved: Reserved bits Note: Read as zero should be written as zero Note: Bits 16 and 20 to 23 are set, when the corresponding unit reports an error Note: The MCS can be programmed to generate an error, when the comparison of signal values (duty time, cycle time) fails or also when the cycle time of the ARU (checking of the TBU_TS0 between two periodic accesses) is out of the expected range.

Register Bit Attributes

Below the bit name in a register table, the attributes “Access Mode” and “Reset Value” of each bit are described with the following syntax:

ARU Write Address Overview

ARU Write Address Table:

Name Address ARU_ACCESS 0x000 TIM [0 . . .3] TIM0_WRADDR[0 . . . 7] 0x001 . . . 0x008 TIM1_WRADDR[0 . . . 7] 0x009 . . . 0x010 TIM2_WRADDR[0 . . . 7] 0x011 . . . 0x018 TIM3_WRADDR[0 . . . 7] 0x019 . . . 0x020 unused 0x021 . . . 0x038 DPLL DPLL_WRADDR[0 . . . 23] 10x039 . . . 0x050 F2A [0] F2A0_WRADDR[0 . . . 7] 0x051 . . . 0x058 unused 0x059 . . . 0x060 BR BRC_WRADDR[0 . . . 21] 0x061 . . . 0x076 MCS [0 . . .3] MCS0_WRADDR[0 . . . 23] 0x077 . . . 0x08E MCS1_WRADDR[0 . . . 23] 0x08F . . . 0x0A6 MCS2_WRADDR[0 . . . 23] 0x0A7 . . . 0x0BE MCS3_WRADDR[0 . . . 23] 0x0BF . . . 0x0D6 unused 0x0D7 . . . 0x11E ATOM [0 . . .5] ATOM0_WRADDR[0 . . . 7] 0x11F . . . 0x126 ATOM1_WRADDR[0 . . . 7] 0x127 . . . 0x12E ATOM2_WRADDR[0 . . . 7] 0x12F . . . 0x136 ATOM3_WRADDR[0 . . . 7] 0x137 . . . 0x13E ATOM4_WRADDR[0 . . . 7] 0x13F . . . 0x146 ATOM5_WRADDR[0 . . . 7] 0x147 . . . 0x14E misc unused 0x14F . . . 0x1FD ARU_EMPTY_ADDR 0x1FE ARU_FULL_ADDR 0x1FF

GTM Configuration Registers Address Map

The base addresses of the implemented sub modules are not specified in detail here.