DC voltage conversion circuit of liquid crystal display apparatus

This application is based on and claims priority from Korean Patent Application No. 10-2011-0103231, filed on Oct. 10, 2011, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

The present disclosure relates to a DC voltage conversion circuit of a liquid crystal display apparatus, and more particularly, to a DC voltage conversion circuit of a liquid crystal display apparatus capable of generating higher voltage from limited DC power supply voltage and a clock signal to utilize the generated voltage for driving the liquid crystal display apparatus.

A thin film transistor (hereinafter, referred to as a “TFT”) is embedded and used in a liquid crystal display apparatus by using a merit capable of forming the TFT on a large-sized glass substrate and the like. Currently, an amorphous silicon (a-Si) TFT is used in most liquid crystal display apparatuses, but recently, as screen scanning efficiency is increased up to 480 Hz, a TFT having more excellent current driving capacity has been required. An oxide TFT uses metal oxide such as IGZO (In—Ga—Zn—O), ZnO and the like as an active layer, and since the oxide TFT has electron mobility of 10 cm 2 /Vs or more as illustrated in FIG. 1 , the current driving capacity is ten times or higher than an existing a-Si TFT.

However, in the oxide TFT, since a characteristic is changed due to a minute condition change in a manufacturing process, or voltage and light, a depletion-mode operation characteristic having negative threshold voltage V T is shown.

In the existing a-Si TFT, since the threshold voltage V T has a positive value, the a-Si TFT is turned off when gate-source voltage V GS is 0 V and thus a driving circuit is easily configured. However, since the oxide TFT (hereinafter, referred to as an “oxide TFT”) having the depletion-mode operation characteristic have negative threshold voltage V T as illustrated in FIG. 2 , the oxide TFT is not turned off and current flows even in the case where the gate-source voltage V GS is 0 V. Accordingly, in order to completely turn off the depletion-mode TFT, the negative threshold voltage V T needs to be applied. In order to solve the problem and configure an embedded circuit of the liquid crystal display apparatus by using the depletion-mode TFT, a new circuit capable of applying the negative threshold voltage V T needs to be designed.

FIG. 3 is a diagram illustrating a DC voltage conversion circuit in the related art, and FIG. 4 is a diagram illustrating a DC voltage conversion circuit in the related art which operates in response to a characteristic of a depletion-mode TFT which improves the DC voltage conversion circuit in the related art (“Charge pump circuit for depletion-mode oxide TFTs”, M. W. Oh, et al., Electronics Letters, Vol. 47, No. 6, 2011).

Referring to FIGS. 3 and 4 , since the DC voltage conversion circuit in the related art uses only an N-type TFT, a circuit may be configured by using the a-Si TFT or oxide TFT, and all TFTs are turned off when the gate-source voltage V GS is −5 V, such that the circuit may operate normally even in the depletion-mode TFT. However, when the TFT is turned on, since 0 V is applied as the gate-source voltage V GS , a general TFT having threshold voltage V T of 0 V or more is not turned on, such that the circuit is difficult to operate normally.

The present disclosure has been made in an effort to provide a DC voltage conversion circuit of a liquid crystal display apparatus against wide distribution of threshold voltage V T by applying positive gate-source voltage V GS when turning on a TFT, and applying negative gate-source voltage V GS when turning off the TFT.

An exemplary embodiment of the present disclosure provides a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltage applied to a gate of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.

According to the exemplary embodiment of the present disclosure, by providing a DC voltage conversion circuit of a liquid crystal display apparatus which applies positive gate-source voltage V GS when turning on a TFT and applies negative gate-source voltage V GS when turning off the TFT, since the DC voltage conversion circuit has a large voltage margin when the TFT is turned on as compared with a DC voltage conversion circuit in the related art, it is possible to stably maintain power efficiency even in large load current and thus show stable output voltage and power efficiency against wide distribution of threshold voltage V T .

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

FIG. 1 is a graph illustrating electron mobility of an oxide TFT.

FIG. 2 is a graph illustrating a transfer characteristic V GS -I D of an oxide TFT.

FIG. 3 is a diagram illustrating a DC voltage conversion circuit in the related art.

FIG. 4 is a diagram illustrating a DC voltage conversion circuit capable of increasing DC voltage V DD up to three times and outputting the increased DC voltage by improving the DC voltage conversion circuit in the related art.

FIG. 5 is a timing diagram of a clock signal which is inputted to a DC voltage conversion circuit according to an exemplary embodiment of the present disclosure.

FIG. 6 is a diagram for describing a case where voltage is applied when an oxide TFT is turned on or off in a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure.

FIG. 7 is a diagram illustrating the overall configuration of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure.

FIG. 8 is a diagram for describing an operation of a main pumping circuit according to the exemplary embodiment of the present disclosure at the time of a first clock cycle T 1 .

FIG. 9 is a diagram for describing an operation of a main pumping circuit according to the exemplary embodiment of the present disclosure at the time of a second clock cycle T 2 .

FIG. 10 is a diagram for describing an operation of a switch control signal generator according to the exemplary embodiment of the present disclosure at the time of a first clock cycle T 1 .

FIG. 11 is a diagram for describing an operation of a switch control signal generator according to the exemplary embodiment of the present disclosure at the time of a second clock cycle T 2 .

FIG. 12 is a graph comparing output voltages of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure and a DC voltage conversion circuit in the related art.

FIG. 13 is a graph comparing power efficiencies of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure and a DC voltage conversion circuit in the related art.

In the following detailed description, reference is made to the accompanying drawing, which form a part hereof. The illustrative embodiments described in the detailed description, drawing, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the present disclosure, well-known functions or constructions will not be described in detail since they may unnecessarily obscure the understanding of the present disclosure.

FIG. 5 is a timing diagram of a clock signal which is inputted to a DC voltage conversion circuit according to an exemplary embodiment of the present disclosure.

The DC voltage conversion circuit according to an exemplary embodiment of the present disclosure uses second power supply voltage V DD2 and first power supply voltage V DD1 having a smaller value than the second power supply voltage V DD2 . In addition, the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure uses four clock signals, and each clock signal has an amplitude of the second power supply voltage V DD2 or the first power supply voltage V DD1 and has an opposite phase to each other. Values of the second power supply voltage V DD2 and the first power supply voltage V DD1 may be arbitrarily determined as necessary, and for convenience of the description, the exemplary embodiment of the present disclosure will be described by setting the values of the second power supply voltage V DD2 and the first power supply voltage V DD1 to 9 V and 3 V, respectively.

As illustrated in FIG. 5 , the first power supply voltage V DD1 is 3 V, and the second power supply voltage V DD2 is 9 V. Further, a first clock signal CK_ 3 / 0 and a second clock signal CK_ 0 / 3 have an amplitude of the first power supply voltage V DD1 , and a third clock signal CK_ 9 / 0 and a fourth clock signal CK_ 0 / 9 have an amplitude of the second power supply voltage V DD2 . Herein, waveforms of the clock signals are not overlapped with each other, and frequencies of the clock signals may be changed.

FIG. 6 is a diagram for describing a case where voltage is applied when an oxide TFT is turned on or off in the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure.

Referring to FIG. 6 , when source voltage of an oxide thin film transistor (hereinafter, referred to as ‘TFT’) M 3 is 12 V, 15 V is applied to a gate and thus the oxide TFT M 3 is turned on. In this case, a source and a drain are connected to each other and thus drain voltage becomes 12 V. When the oxide TFT M 3 is turned off, the gate voltage drops by the amplitude of 9 V and thus becomes 6 V, and the source voltage and drain voltage drop and rise by the amplitude of 3 V, respectively. Accordingly, since the source voltage becomes 9 V, gate-source voltage V GS becomes −3 V and thus the oxide TFT M 3 is completely turned off.

FIG. 7 is a diagram illustrating the overall configuration of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure.

Referring to FIG. 7 , the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure includes a plurality of TFTs M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 and M 8 , and includes a main pumping circuit 710 in which the plurality of TFTs M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 and M 8 are alternately turned on or off depending on voltages applied to the gates to output voltage for driving a liquid crystal display apparatus, and a switch control signal generator 720 which controls the voltages applied to the gates of the plurality of TFTs M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 and M 8 in order to alternately turn on or off the plurality of TFTs M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 and M 8 due to inversion of the clock signal. Herein, the two functional units 710 and 720 share nodes thereof to generate voltages and turn on/off the TFTs.

The main pumping circuit 710 according to the exemplary embodiment of the present disclosure includes a first TFT M 1 , a second TFT M 2 , a third TFT M 3 , a fourth TFT M 4 , a fifth TFT M 5 , a sixth TFT M 6 , a seventh TFT M 7 and an eighth TFT M 8 .

In the first TFT M 1 , the second power supply voltage V DD2 is applied to the source, a first node n 6 _ 15 is connected to the gate, and a second node n 12 _ 9 is connected to the drain. Herein, the fourth clock signal CK_ 0 / 9 is inputted to the first node n 6 _ 15 , and the first clock signal CK_ 3 / 0 is inputted to the second node n 12 _ 9 .

In the second TFT M 2 , the second power supply voltage V DD2 is applied to the source, a third node n 15 _ 6 is connected to the gate, and a fourth node n 9 _ 12 is connected to the drain. Herein, the third clock signal CK_ 9 / 0 is inputted to the third node n 15 _ 6 , and the second clock signal CK_ 0 / 3 is inputted to the fourth node n 9 _ 12 .

In the third TFT M 3 , the second node n 12 _ 9 is connected to the source, the third node n 15 _ 6 is connected to the gate, and a fifth node n 12 _ 15 is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the second node n 12 _ 9 , the third clock signal CK_ 9 / 0 is inputted to the third node n 15 _ 6 , and the second clock signal CK_ 0 / 3 is inputted to the fifth node n 12 _ 15 .

In the fourth TFT M 4 , the fourth node n 9 _ 12 is connected to the source, the first node n 6 _ 15 is connected to the gate, and a sixth node n 15 _ 12 is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the fourth node n 9 _ 12 , the fourth clock signal CK_ 0 / 9 is inputted to the first node n 6 _ 15 , and the first clock signal CK_ 3 / 0 is inputted to the sixth node n 15 _ 12 .

In the fifth TFT M 5 , the fifth node n 12 _ 15 is connected to the source, a seventh node n 9 _ 18 is connected to the gate, and an eighth node n 18 _ 15 is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the fifth node n 12 _ 15 , the fourth clock signal CK_ 0 / 9 is inputted to the seventh node n 9 _ 18 , and the first clock signal CK_ 3 / 0 is inputted to the eighth node n 18 _ 15 .

In the sixth TFT M 6 , the sixth node n 15 _ 12 is connected to the source, a ninth node n 18 _ 9 is connected to the gate, and a tenth node n 15 _ 18 is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the sixth node n 15 _ 12 , the third clock signal CK_ 9 / 0 is inputted to the ninth node n 18 _ 9 , and the second clock signal CK_ 0 / 3 is inputted to the tenth node n 15 _ 18 .

In the seventh TFT M 7 , the eighth node n 18 _ 15 is connected to the source, an eleventh node n 21 _ 12 is connected to the gate, and an output node OUT is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the eighth node n 18 _ 15 , and the third clock signal CK_ 9 / 0 is inputted to the eleventh node n 21 _ 12 .

In the eighth TFT M 8 , the tenth node n 15 _ 18 is connected to the source, a twelfth node n 12 _ 21 is connected to the gate, and the output node OUT is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the tenth node n 15 _ 18 , and the fourth clock signal CK_ 0 / 9 is inputted to the twelfth node n 12 _ 21 .

The switch control signal generator 720 according to the exemplary embodiment of the present disclosure includes an eleventh TFT MA, a twelfth TFT MB, a thirteenth TFT MC, a fourteenth TFT MD, a fifteenth TFT ME, a sixteenth TFT MF, a seventeenth TFT MG and an eighteenth TFT MH.

In the eleventh TFT MA, the first power supply voltage V DD1 is applied to the source, the fourth clock signal CK_ 0 / 9 is inputted to the gate, and a thirteenth node n 6 _ 3 is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the thirteenth node n 6 _ 3 .

In the twelfth TFT MB, the first power supply voltage V DD1 is applied to the source, the third clock signal CK_ 9 / 0 is inputted to the gate, and a fourteenth node n 3 _ 6 is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the fourteenth node n 3 _ 6 .

In the thirteenth TFT MC, the thirteenth node n 6 _ 3 is connected to the source, the third clock signal CK_ 9 / 0 is inputted to the gate, and the first node n 6 _ 15 is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the thirteenth node n 6 _ 3 , and the fourth clock signal CK_ 0 / 9 is inputted to the first node n 6 _ 15 .

In the fourteenth TFT MD, the fourteenth node n 3 _ 6 is connected to the source, the fourth clock signal CK_ 0 / 9 is inputted to the gate, and the third node n 15 _ 6 is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the fourteenth node n 3 _ 6 , and the third clock signal CK_ 9 / 0 is inputted to the third node n 15 _ 6 .

In the fifteenth TFT ME, the second power supply voltage V DD2 is applied to the source, the third node n 15 _ 6 is connected to the gate, and the seventh node n 9 _ 18 is connected to the drain. Herein, the third clock signal CK_ 9 / 0 is inputted to the third node n 15 _ 6 , and the fourth clock signal CK_ 0 / 9 is inputted to the seventh node n 9 _ 18 .

In the sixteenth TFT MF, the second power supply voltage V DD2 is applied to the source, the first node n 6 _ 15 is connected to the gate, and the ninth node n 18 _ 9 is connected to the drain. Herein, the fourth clock signal CK_ 0 / 9 is inputted to the first node n 6 _ 15 , and the third clock signal CK_ 9 / 0 is inputted to the ninth node n 18 _ 9 .

In the seventeenth TFT MG, the second node n 12 _ 9 is connected to the source, the third node n 15 _ 6 is connected to the gate, and the twelfth node n 12 _ 21 is connected to the drain. Herein, the first clock signal CK_ 3 / 0 is inputted to the second node n 12 _ 9 , the third clock signal CK_ 9 / 0 is inputted to the third node n 15 _ 6 , and the fourth clock signal CK_ 0 / 9 is inputted to the twelfth node n 12 _ 21 .

In the eighteenth TFT MH, the fourth node n 9 _ 12 is connected to the source, the first node n 6 _ 15 is connected to the gate, and the eleventh node n 21 _ 12 is connected to the drain. Herein, the second clock signal CK_ 0 / 3 is inputted to the fourth node n 9 _ 12 , the fourth clock signal CK_ 0 / 9 is inputted to the first node n 6 _ 15 , and the third clock signal CK_ 9 / 0 is inputted to the eleventh node n 21 _ 12 .

Meanwhile, in the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure, two situations of a first clock cycle T 1 and a second clock cycle T 2 repetitively occur by inversion of the clock signal.

That is, at the time of the first clock cycle T 1 , the first clock signal CK_ 3 / 0 and the third clock signal CK_ 9 / 0 are in a “High” state, and the second clock signal CK_ 0 / 3 and the fourth clock signal CK_ 0 / 9 are in a “Low” state. Accordingly, the second TFT M 2 , the third TFT M 3 , the sixth TFT M 6 , the seventh TFT M 7 , the twelfth TFT MB, the thirteenth TFT MC, the fifteenth TFT ME and the seventeenth TFT MG are turned on, and the first TFT M 1 , the fourth TFT M 4 , the fifth TFT M 5 , the eighth TFT M 8 , the eleventh TFT MA, the fourteenth TFT MD, the sixteenth TFT MF and the eighteenth TFT MH are turned off.

At the time of the second clock cycle T 2 , the first clock signal CK_ 3 / 0 and the third clock signal CK_ 9 / 0 are in a “Low” state, and the second clock signal CK_ 0 / 3 and the fourth clock signal CK_ 0 / 9 are in a “High” state. Accordingly, the second TFT M 2 , the third TFT M 3 , the sixth TFT M 6 , the seventh TFT M 7 , the twelfth TFT MB, the thirteenth TFT MC, the fifteenth TFT ME and the seventeenth TFT MG are turned off, and the first TFT M 1 , the fourth TFT M 4 , the fifth TFT M 5 , the eighth TFT M 8 , the eleventh TFT MA, the fourteenth TFT MD, the sixteenth TFT MF and the eighteenth TFT MH are turned on.

Hereinafter, operations of the main pumping circuit 710 and the switch control signal generator 720 according to the exemplary embodiment of the present disclosure will be described in detail, respectively.

FIG. 8 is a diagram for describing an operation of a main pumping circuit according to the exemplary embodiment of the present disclosure at the time of a first clock cycle T 1 .

Referring to FIG. 8 , the first TFT M 1 is turned off when the voltage of the first node n 6 _ 15 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the first TFT M 1 is −3 V.

The second TFT M 2 is turned on when the voltage of the third node n 15 _ 6 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the second TFT M 2 is 6 V. Accordingly, the second TFT M 2 transfers 9 V of the second power supply voltage V DD2 to the fourth node n 9 _ 12 .

The third TFT M 3 is turned on when the voltage of the third node n 15 _ 6 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the third TFT M 3 is 3 V. Accordingly, the third TFT M 3 transfers 12 V of the second node n 12 _ 9 boosted by the first clock signal CK_ 3 / 0 to the fifth node n 12 _ 15 .

The fourth TFT M 4 is turned off when the voltage of the first node n 6 _ 15 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the fourth TFT M 4 is −3 V.

The fifth TFT M 5 is turned off when the voltage of the seventh node n 9 _ 18 connected to the gate becomes 9 V. In this case, the gate-source voltage V GS of the fifth TFT M 5 is −3 V.

The sixth TFT M 6 is turned on when the voltage of the ninth node n 18 _ 9 connected to the gate becomes 18 V. In this case, the gate-source voltage V GS of the sixth TFT M 6 is 3 V. Accordingly, the sixth TFT M 6 transfers 15 V of the sixth node n 15 _ 12 boosted by the first clock signal CK_ 3 / 0 to the tenth node n 15 _ 18 .

The seventh TFT M 7 is turned on when the voltage of the eleventh node n 21 _ 12 connected to the gate becomes 21 V. In this case, the gate-source voltage V GS of the seventh TFT M 7 is 3 V. Accordingly, the seventh TFT M 7 transfers 18 V of the eighth node n 18 _ 15 boosted by the first clock signal CK_ 3 / 0 to the output node OUT.

The eighth TFT M 8 is turned off when the voltage of the twelfth node n 12 _ 21 connected to the gate becomes 12 V. In this case, the gate-source voltage V GS of the eighth TFT M 8 is −3 V.

FIG. 9 is a diagram for describing an operation of a main pumping circuit according to the exemplary embodiment of the present disclosure at the time of a second clock cycle T 2 .

Referring to FIG. 9 , the first TFT M 1 is turned on when the voltage of the first node n 6 _ 15 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the first TFT M 1 is 6 V. Accordingly, the first TFT M 1 transfers 9 V of the second power supply voltage V DD2 to the second node n 12 _ 9 .

The second TFT M 2 is turned off when the voltage of the third node n 15 _ 6 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the second TFT M 2 is −3 V.

The third TFT M 3 is turned off when the voltage of the third node n 15 _ 6 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the third TFT M 3 is −3 V.

The fourth TFT M 4 is turned on when the voltage of the first node n 6 _ 15 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the fourth TFT M 4 is 3 V. Accordingly, the fourth TFT M 4 transfers 12 V of the fourth node n 9 _ 12 boosted by the second clock signal CK_ 0 / 3 to the sixth node n 15 _ 12 .

The fifth TFT M 5 is turned on when the voltage of the seventh node n 9 _ 18 connected to the gate becomes 18 V. In this case, the gate-source voltage V GS of the fifth TFT M 5 is 3 V. Accordingly, the fifth TFT M 5 transfers 15 V of the fifth node n 12 _ 15 boosted by the second clock signal CK_ 0 / 3 to the eighth node n 18 _ 15 .

The sixth TFT M 6 is turned off when the voltage of the ninth node n 18 _ 9 connected to the gate becomes 9 V. In this case, the gate-source voltage V GS of the sixth TFT M 6 is −3 V.

The seventh TFT M 7 is turned off when the voltage of the eleventh node n 21 _ 12 connected to the gate becomes 12 V. In this case, the gate-source voltage V GS of the seventh TFT M 7 is −3 V.

The eighth TFT M 8 is turned on when the voltage of the twelfth node n 12 _ 21 connected to the gate becomes 21 V. In this case, the gate-source voltage V GS of the eighth TFT M 8 is 3 V. Accordingly, the eighth TFT M 8 transfers 18 V of the tenth node n 15 _ 18 boosted by the second clock signal CK_ 0 / 3 to the output node OUT.

FIG. 10 is a diagram for describing an operation of a switch control signal generator according to the exemplary embodiment of the present disclosure at the time of a first clock cycle T 1 .

Referring to FIG. 10 , the eleventh TFT MA is turned off when the voltage of the fourth clock signal CK_ 0 / 9 inputted to the gate becomes 0 V. In this case, the gate-source voltage V GS of the eleventh TFT MA is −3 V.

The twelfth TFT MB is turned on when the voltage of the third clock signal CK_ 9 / 0 inputted to the gate becomes 9 V. In this case, the gate-source voltage V GS of the twelfth TFT MB is 6 V. Accordingly, the twelfth TFT MB transfers the first power supply voltage V DD1 to the fourteenth node n 3 _ 6 .

The thirteenth TFT MC is turned on when the voltage of the third clock signal CK_ 9 / 0 inputted to the gate becomes 9 V. In this case, the gate-source voltage V GS of the thirteenth TFT MC is 3 V. Accordingly, the thirteenth TFT MC transfers 6 V of the thirteenth node n 6 _ 3 boosted by the first clock signal CK_ 3 / 0 to the first node n 6 _ 15 .

The fourteenth TFT MD is turned off when the voltage of the fourth clock signal CK_ 0 / 9 inputted to the gate becomes 0 V. In this case, the gate-source voltage V GS of the fourteenth TFT MD is −3 V.

The fifteenth TFT ME is turned on when the voltage of the third node n 15 _ 6 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the fifteenth TFT ME is 6 V. Accordingly, the fifteenth TFT ME transfers the second power supply voltage V DD2 to the seventh node n 9 _ 18 .

The sixteenth TFT MF is turned off when the voltage of the first node n 6 _ 15 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the sixteenth TFT MF is −3 V.

The seventeenth TFT MG is turned on when the voltage of the third node n 15 _ 6 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the seventeenth TFT MG is 3 V. Accordingly, the seventeenth TFT MG transfers 12 V of the second node n 12 _ 9 boosted by the first clock signal CK_ 3 / 0 to the twelfth node n 12 _ 21 .

The eighteenth TFT MH is turned off when the voltage of the first node n 6 _ 15 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the eighteenth TFT MH is −3 V.

FIG. 11 is a diagram for describing an operation of a switch control signal generator according to the exemplary embodiment of the present disclosure at the time of a second clock cycle T 2 .

Referring to FIG. 11 , the eleventh TFT MA is turned on when the voltage of the fourth clock signal CK_ 0 / 9 inputted to the gate becomes 9 V. In this case, the gate-source voltage V GS of the eleventh TFT MA is 6 V. Accordingly, the eleventh TFT MA transfers the first power supply voltage V DD1 to the thirteenth node n 6 _ 3 .

The twelfth TFT MB is turned off when the voltage of the third clock signal CK_ 9 / 0 inputted to the gate becomes 0 V. In this case, the gate-source voltage V GS of the twelfth TFT MB is −3V.

The thirteenth TFT MC is turned off when the voltage of the third clock signal CK_ 9 / 0 inputted to the gate becomes 0 V. In this case, the gate-source voltage V GS of the thirteenth TFT MC is −3 V.

The fourteenth TFT MD is turned on when the voltage of the fourth clock signal CK_ 0 / 9 inputted to the gate becomes 9 V. In this case, the gate-source voltage V GS of the fourteenth TFT MD is 3 V. Accordingly, the fourteenth TFT MD transfers 6 V of the fourteenth node n 3 _ 6 boosted by the second clock signal CK_ 0 / 3 to the third node n 15 _ 6 .

The fifteenth TFT ME is turned off when the voltage of the third node n 15 _ 6 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the fifteenth TFT ME is −3V.

The sixteenth TFT MF is turned on when the voltage of the first node n 6 _ 15 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the sixteenth TFT MF is 6 V. Accordingly, the sixteenth TFT MF transfers the second power supply voltage V DD2 to the ninth node n 18 _ 9 .

The seventeenth TFT MG is turned off when the voltage of the third node n 15 _ 6 connected to the gate becomes 6 V. In this case, the gate-source voltage V GS of the seventeenth TFT MG is −3 V.

The eighteenth TFT MH is turned on when the voltage of the first node n 6 _ 15 connected to the gate becomes 15 V. In this case, the gate-source voltage V GS of the eighteenth TFT MH is 3 V. Accordingly, the eighteenth TFT MH transfers 12 V of the fourth node n 9 _ 12 boosted by the second clock signal CK_ 0 / 3 to the eleventh node n 21 _ 12 .

FIG. 12 is a graph comparing output voltages of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure and a DC voltage conversion circuit in the related art.

In FIG. 12 , output voltages of two circuits will be compared with each other under the condition in which threshold voltage V T of the TFT is −4 V to +4 V, and the output current is 10 uA to 200 uA.

Referring to FIG. 12 , FIG. 12A is a graph illustrating output voltage of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure, and FIG. 12B is a graph illustrating output voltage of a DC voltage conversion circuit in the related art. The DC voltage conversion circuit according to the exemplary embodiment of the present disclosure generates stable output voltage as compared with the DC voltage conversion circuit in the related art. Particularly, it is verified that the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure more stably operates in a positive threshold voltage V T region which is a general situation. This is because the TFT is sufficiently turned on even under the positive threshold voltage V T condition and thus the DC voltage conversion circuit operates normally.

FIG. 13 is a graph comparing power efficiencies of a DC voltage conversion circuit according to the exemplary embodiment of the present disclosure and a DC voltage conversion circuit in the related art.

Referring to FIG. 13 , reference numeral 1310 represents power efficiency of the DC voltage conversion circuit in the related art under the condition where output current is 100 uA, reference numeral 1320 represents power efficiency of the DC voltage conversion circuit in the related art under the condition where output current is 200 uA, reference numeral 1330 represents power efficiency of the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure under the condition where output current is 100 uA, and reference numeral 1340 represents power efficiency of the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure under the condition where output current is 200 uA.

As illustrated in FIG. 13 , it is verified that the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure has higher power efficiency than the DC voltage conversion circuit in the related art. In particular, the DC voltage conversion circuit according to the exemplary embodiment of the present disclosure has significantly excellent power efficiency under the positive threshold voltage V T condition.

From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.