Class-AB radio frequency amplifier for envelope detector

This disclosure relates to an envelope detector (ED), and more particularly, an ED core with an enhanced linear range that eliminates the need for an external envelope detector or excessive factory open loop power calibration, and to a linearizer and a specialized class-AB amplifier that may be used with the ED core.

Rapid advances in electronics and communications technologies, driven by immense customer demand, have resulted in the widespread adoption of data-driven devices, including cellular phones, smart phones and global positioning devices (GPSs), to name just a few. Envelope detectors (EDs) detect the voltage amplitude of a radio frequency (RF) signal output from a transmitter (TX) of such cellular devices for purposes of calibration or power detection. For instance, the envelope or peak information of the TX output may be used for calibration of LOFT (Local Oscillator (LO) feedthrough), IQ (in-phase/quadrature) mismatch and power level control. An envelope detector can also be used for envelope tracking of voltage amplifier supply to save power by decreasing the supply when the output is low. Peak to average ratio and dynamic range of the TX output may require stringent linear ranges for an ED core integrated within a cellular transmitter. During ED conversion, a linearity accuracy within plus or minus 0.5 dB may be expected for proper calibration and envelope tracking.

The innovation may be better understood with reference to the following drawings and description. In the figures, like reference numerals designate corresponding parts throughout the different views.

FIG. 1 is an example circuit showing typical placement of an envelope detector (ED) within a cellular transmitter (TX).

FIGS. 2A and 2B are, respectively, graphs of: (a) V out versus V in (TX out — peak ), or V out /V in , of an envelope detector; and (b) the slope of V out /V in of FIG. 2A in decibels (dB).

FIGS. 3A , 3 B and 3 C are example conventional envelope detectors, respectively that use: (a) an operational amplifier; (b) a current mode, operation transconductance amplifier (OTA); and (c) a voltage mode ED that employs complementary metal-oxide-semiconductor (CMOS) devices.

FIG. 4 is an example conventional envelope detector core like the ED of FIG. 3C , but that generates positive and negative, or differential, voltage outputs.

FIG. 5 is a high-level circuit diagram showing the interrelation of an envelope detector core, which operates detecting transistors in subthreshold bias regions, with a linearizer, and several amplifiers the last of which may be a specialized class-AB amplifier.

FIGS. 6A and 6B respectively are graphs of I 0 (b) and ln(I 0 (b)) versus b, where I k (b) is a modified Bessel function of order k and

FIG. 7 is a graph of V out versus V in of the ED core of FIG. 4 , showing regions where varying current bias of ED transistors helps.

FIG. 8 is a graph of the slope of V out versus V in of the ED core of FIG. 4 , showing regions where smaller bias current is preferred and regions where larger bias current is preferred.

FIG. 9 is an example circuit diagram of an ED core enhanced with variable control of subthreshold bias current of ED transistors using a feedback linearizer.

FIGS. 10A and 10B is an example circuit of a bias-varying ED core with feedback linearizer.

FIGS. 11A through 11D is an example complete ED core circuit, including the feedback linearizer, with additional programmability capabilities for multi-mode adaptation.

FIG. 12 is an example circuit of a typical radio frequency (RF) amplifier.

FIGS. 13A and 13B is an example circuit of a specialized class-AB, RF amplifier to act as a pre-driver to the envelope detector of FIGS. 5 and 9 - 11 .

FIG. 14 is a graph of linear range improvement of the output of the ED core of FIGS. 5 and 9 - 11 .

FIG. 15 is a graph of the slope of the curves of the graph of FIG. 14 .

FIG. 16 is a graph of the ED output slope measured from a fabricated microchip in decibels (dB) versus TX output power, showing additional linear range added by respective gain amplifier stages of FIG. 5 with variable overlap between the gain amplifier stages.

FIGS. 17A and 17B are, respectively, (a) a graph of an example envelope detected at the output of the ED of FIGS. 5 and 9 - 11 ; and (b) an example amplitude-modulated voltage input to the ED with an envelope varying over the linear range of the ED.

FIG. 18 is an example graph of V out versus V in of an envelope detector with a linearizer, from simulation over process, voltage, and temperature (PVT) corners.

The discussion below makes reference to an envelope detector (ED) with an enhanced linear range and accuracy, which adds calibration capability of LOFT (Local Oscillator (LO) feedthrough), IQ (in-phase/quadrature) mismatch and closed-loop power level control. Furthermore, the enhanced high-performance ED design reduces the number of factory calibration points, and may eliminate the need for external envelope detection or excessive factory open loop power calibration, making the manufacture of the cellular phones (or other radio application) chips more cost effective. Gain and bias programmability features also make an ED core of the enhanced ED more generic for various envelope and peak detections for calibration purposes in future chip generations and applications.

The high-performance ED is also power-efficient and area-efficient in design. The entire envelope detector, including voltage amplifiers, takes only about 0.1 mm 2 of chip space. Furthermore, by using subthreshold biasing of detecting transistors, a specially-designed class-AB amplifier, and programmability to reduce the current to amplifiers when not required, makes the enhanced ED quite power efficient. In some implementations, for example, the ED core, which is part of the overall ED design, consumes about 200 uA on average from a 1.2V power supply.

The enhanced ED automates incorporation of feedback signals that sets biases to enhance linearity of operation. This automated feedback capability combined with programmability in various gain stages, makes the enhanced ED design usable in multi-mode solutions. For instance, the ED may be useable with next-generation products including with products that employ the following non-exhaustive list of standards: Global System for Mobile Communications (GSM), Second Generation (2G), General Packet Radio Services (GPRS), Third Generation (3G), Third Generation Partnership Project (3GPP), Enhanced Data Rates for GSM Evolution (EDGE), Fourth Generation (4G) (Mobile WiMax and LTE) and Wideband Code Division Multiple Access (W-CDMA), among other high band and low band standards.

The discussion below makes further reference to a voltage-mode envelope detector core that includes parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, which input may come from a cellular transmission (TX) output. The ED core may output positive and negative, or differential, voltage ED outputs as a detected envelope of the RF signal input. The detection transistors may be configured with a size and for a current to be biased in subthreshold regions of operation. The ED core may be configured to variably control a bias current through the detection transistors, where the bias current is varied proportionally to the voltage amplitude of the RF signal input such that the detection transistors continue to operate in subthreshold regions.

In one example, the detection transistors may include a pair of transistors configured to output the positive ED output and a pair of transistors configured to output the negative ED output. The ED core may include a current-biasing transistor for each pair (or group) of detection transistors, where a bias voltage of the current-biasing transistors determines the bias current for each pair of detection transistors, the bias voltage being determined from the positive and negative differential ED outputs.

In a further example, a linearizer may be connected in a feedback loop between the ED outputs and the ED core, to control the bias current of the detection transistors according to voltage amplitude of the ED outputs. The linearizer may include a linearizer circuit configured with a differential amplifier connected to the differential positive and negative ED outputs. The linearizer circuit may be configured to generate the bias voltage for the current-biasing transistors as proportional to a difference between the positive and negative ED outputs, while the detection transistors continue to operate in subthreshold regions despite a larger biasing current.

Multiple voltage amplifiers may be positioned serially in gain stages between the TX output and the ED core to provide a total linear range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers that directly drives the ED core may be a specialized class-AB RF amplifier configured to operate within a full linear range of the ED core.

FIG. 1 is an example circuit showing typical placement of an envelope detector (ED) 10 within a cellular transmitter (TX) 15 . A voltage amplifier driver 5 outputs positive and negative (or differential) TX voltage outputs 6 and 8 that become inputs to the ED 10 . Different conventional designs for the ED 10 are discussed with reference to FIGS. 3 and 4 that sense or detect amplifier power.

The ED 10 detects a voltage envelope of the TX outputs 6 and 8 by detecting voltage peaks of the TX voltage RF output signals. The ED 10 outputs the detected voltage envelope to an analog-to-digital converter 12 , which provides calibration data 14 to be combined with digital data 16 from other parts of the cellular TX before being processed by a digital data processing block 20 . The digital data processing block 20 yields signals after having been digitally processed.

A pair of digital-to-analog converters 22 may then convert the processed in-phase and quadrature (I&Q) digital signals back to analog signals. An in-phase/quadrature (I/Q) low pass filter (LPF) and buffer block 26 may further filter and calibrate the analog signals. A mixer 28 may then modulate the filtered signal with a clock 30 before the signal is amplified by the voltage amplifier driver 5 for transmission. The amplified signal may be further filtered or processed before final transmission.

FIG. 2A is a graph of V out versus V in (TX out — peak ), or V out /V in , of an envelope detector. FIG. 2B is a graph of the slope of V out /V in of FIG. 2A in decibels (dB) where an effective linear range of the ED is set within 1 dB of maximums at shown as V H and V L . Because the envelope detector is used in calibration or power detection, the relevant algorithms call for a minimum linear accuracy in the power or voltage level detection. The slope of V out /V in is ideally constant, shown as a straight line in FIG. 2A . The effective linear range of envelope detecting is determined by 20 log(V H /V L ). For instance, when V H is 150 mV and V L is 30 mV, 20 log(V H /V L ) equals about 14 dB.

FIGS. 3A , 3 B and 3 C are example conventional envelope detectors (EDs).

FIG. 3A is an ED that uses a feedback operational amplifier (“opamp”) A 1 followed by a diode D 1 . The ED of FIG. 3A may be limited by the gain bandwidth product of the operational amplifier, and thus may not be the best choice for high frequency RF signals, depending on application and choice of opamp.

FIG. 3B is a current-mode operational transconductance amplifier (OTA)-based ED in which an OTA 40 is followed by a rectifier 42 and a peak detector 44 . The ED of FIG. 3B may call for a high speed and linear OTA that may be power hungry when compared with the ED of FIG. 3C .

FIG. 3C is a voltage-mode ED that employs a complementary metal-oxide-semiconductor (CMOS) transistor (or other type of integrated circuit transistor) 50 and a current source 55 . The ED of FIG. 3C can be more power efficient, but may not provide sufficient linear range due to performance degradation of the detector at small signal levels and saturation at large signal levels.

FIG. 4 is an example conventional ED core 60 like the ED of FIG. 3C , but that generates positive and negative, or differential, voltage outputs. The ED core 60 includes a positive half 61 and a negative half 63 , each half configured substantially the same except that the transistor M 0 of the first half 61 is driven by the RF signal input of the envelope detector while the transistor M 1 of the second half 63 is not driven by the RF signal. The first half 61 of the ED generates a positive voltage ED output (Vop) while the second half 63 of the ED generates a negative voltage ED output (Von), which together generate a differential voltage output of the ED core 60 .

A bias voltage (VB) also drives gates of the transistors M 0 and M 1 and direct current (DC) current sources (I 1 , I 2 ) are provided at the respective sources of each transistor M 0 and M 1 to set the operating point and mode of M 0 and M 1 , respectively. The transistors M 0 and M 1 may be CMOS transistors or any other kind of integrated circuit (IC) transistor (such as bi-polar or field effect transistors (FETs) for instance). The transistors referred to throughout this disclosure may be any type or combination of transistors.

An even non-linearity develops a voltage at Vop such that the DC current (“I”) matches the average DC current of the transistor M 0 . Even nonlinearity can come from the square law in the saturation region of the transistor; from the exponential IN equation in the subthreshold region of the transistor; or from the transition between the two. The ED core 60 of FIG. 4 is commonly biased in saturation, which provides a linear range of about 10 dB, which may be insufficient for TX multi-purpose calibration applications. A transistor is biased in saturation when V GS is larger than a threshold voltage.

Detecting transistors (M 0 and M 1 of FIG. 5 or FIG. 9 ) of the ED core 102 may be operated in subthreshold bias regions by subthreshold biasing, made possible because of the exponential IN relation. Such subthreshold biasing improves the linearity of Vop versus the RF input 106 and 108 while saving significantly on power.

FIG. 5 is a high-level circuit diagram of an enhanced envelope detector (ED) 100 , showing the interrelation of an envelope detector core 102 with a feedback linearizer 104 and a specialized class-AB amplifier 116 .

The feedback linearizer 104 may vary the bias of the detecting transistors according to an input envelope amplitude, to significantly improve the linear range of the ED core 102 while reducing total power of the ED as well. The linearizer 106 will be discussed in more detail with reference to FIGS. 9 and 10 .

Multiple voltage amplifiers, such as voltage amplifiers 110 , 112 and 114 ( FIG. 12 ), may be positioned in serial gain stages between the TX output and the class-AB amplifier 116 , sufficient to provide the total linear range of about 60 dB as listed in Table 1. Each gain stage may be variably controlled.

The specialized class-AB amplifier 116 may also be referred to as a class-AB driver in directly driving the ED core 102 . The class-AB amplifier 116 may be configured to provide a signal within a full linear voltage range of the ED 100 , which also provides power savings to the ED. The class-AB amplifier, therefore, improves usability of the ED core as the RF signal input to the ED core may go up to approximately a 1V peak. The specialized class-AB amplifier 116 will be discussed in more detail with reference to FIGS. 13A and 13B .

Specifications for designing the enhanced ED were set according to Table 1. These specifications were met or exceeded by the enhanced ED design, discussed in more detail below, without excessive power or area penalties.

In the subthreshold regions, the current of detecting transistors (M 0 and M 1 of FIG. 4 , for instance) is an exponential function of gate-source voltage (V GS ). More specifically,

⁢ ( v GS - v TH nV T ( 1 )

where V TH is a threshold voltage of the transistor, I S is the current at V GS =V TH . nV T =nKT/q≅×26 mV≈32.5 mV, n is a slope factor, V T is a thermal voltage, T is absolute temperature, K is the Boltzmann constant and q is the electron charge.

With reference to FIG. 4 , considering the RF input signal as V m cos(ωt) with a peak amplitude of V m and a bias voltage V B , Equation (1) can be rewritten as:

The input signal portion from Equation (2) can be expanded as:

e ⁢ ( v m ⁢ cos ⁡ ( ω ⁢ ⁢ t ) ) nV T = [ I 0 ⁡ ( b ) + 2 ⁢ I 1 ⁡ ( b ) ⁢ cos ⁡ ( ω ⁢ ⁢ t ) + 2 ⁢ I 2 ⁡ ( b ) ⁢ cos ⁡ ( ω ⁢ ⁢ t ) + … ⁢ ] ( 3 )

where I k (b) is a modified Bessel function of order k, and

b = V m nV T .

Considering the fact that the average current of M 0 is equal to current source current I 1 in FIG. 4 ), the current I 1 can be derived from Equations (2) and (3) as:

Similarly for M 1 with no input RF signal in FIG. 4 , Equation (1) can rewritten as:

Dividing Equation (5) by Equation (4) and taking the logarithm from both sides, after rearrangement, yields:

FIGS. 6A and 6B are, respectively, graphs of

I 0 ⁡ ( V m nV T ) ⁢ ⁢ and ⁢ ⁢ l n ⁡ ( I 0 ⁡ ( V m nV T ) )

versus V m . The value of

I 0 ⁡ ( V m nV T )

in Equation (6) is mostly an exponential function of V m . The exponential behavior of I 0 (b) makes V out mostly a linear function of V m for reasonable sizes of V m .

The dotted curve in FIG. 6A may be derived from a known approximation

I 0 ⁢ ( b ) = e b √ 2 ⁢ π ⁢ ⁢ b

for large b. Thus, Equation (6) can be written as

V out = nV T · ln ⁡ ( I 2 I 1 ) + V m - nV T 2 ⁢ ln ⁡ ( 2 ⁢ π ⁢ ⁢ V m / V T ) ( 7 )

And thus the slope of V out versus input amplitude will be:

ⅆ V out ⅆ V m = 1 - nV T 2 · 1 V m ( 8 )

As can be seen from Equation (8), the nonlinear term in the slope is diminished at larger V m .

Accordingly, the subthreshold biasing of the ED not only saves power, but also improves linearity performance in the detecting performance by the ED 100 , e.g., up to at least approximately 4 dB of additional linear range for the ED core.

Moreover, there are other second-order effects improved upon by the ED 100 . Such second-order effects may include, for instance, dependency of current and output to V ds of both M 0 and DC current sources. Another second-order effect may include how deep M 0 is operating in the subthreshold region. Introducing subthreshold biasing improves the linearity compared to standard saturation ED by at least 4 dB, but another 5-6 dB improvement may be achieved by compensating for the second-order effects in the feedback scheme that includes the linearizer 104 , as will be discussed.

FIG. 7 is a graph of V out versus V in of the ED core 60 , showing regions 71 and 73 where varying current bias of ED transistors helps. FIG. 8 is a graph of the slope of V out versus V in of the ED core 60 , showing region 71 where smaller bias current is preferred and region 73 where larger bias current is preferred. More specifically, for a small RF input signal amplitude, lower bias (or deeper subthreshold) provides a better linearity performance. On the other hand, due to shrinking V ds with larger input RF signal, larger biasing helps in region 71 , which reduces V op and increases V ds , thus providing a larger potential detection range despite the larger input RF signal.

FIG. 9 is an example circuit diagram of an ED core 102 enhanced with variable control of subthreshold bias current of ED transistors using the feedback linearizer 104 . The bias current, which in FIG. 9 is shown as DC current bias blocks (I), may be varied in relation to the amplitude of the RF input signal. Conveniently, the RF input signal is available at the ED output, so a feedback loop may be designed.

The feedback linearizer 104 receives the differential ED output, V out , and varies the bias current sources (I) in the ED core 100 according to the amplitude of V out . More specifically, the linearizer output (V bn ). may be set as V bn +KV out , thus being proportional to the differential ED output, where K is the gain of the linearizer. How K is determined will be discussed with reference to FIG. 10A . While the bias current changes with input RF envelope amplitude of the RF input signal, the ED transistors M 0 and M 1 will be kept in subthreshold regions.

FIGS. 10A and 10B is an example circuit of a bias-varying envelope detector (ED) core 102 ( FIG. 10B ) with a feedback linearizer 104 ( FIG. 10A ). The example circuit in FIG. 10B may also include a voltage bias generator 130 . The transistor M 0 from FIG. 4 now includes two differential transistors, M 0 A and M 0 B, connected in parallel to each other. Likewise, transistor M 1 now includes differential transistors M 1 A and M 1 B, connected in parallel to each other.

The input TX RF signal is differentially AC-coupled to gates of transistors M 0 A and M 0 B after passing through capacitors C 0 A and C 0 B. When there is no input RF signal, a total bias current Ibp of about 2.4 uA may be symmetrically passed through M 0 A and M 0 B, and a total bias current Ibn of about 2.4 uA may also be symmetrically passed through M 1 A and M 1 B. This means that, if M 0 A and M 0 B are substantially symmetrical, then each will carry about 1.2 uA of current. Similarly, if M 1 A and M 1 B are substantially symmetrical, then each will carry about 1.2 uA of current. The bias current (Ibp or Ibn) of about 2.4 uA puts the transistors in deep subthreshold, but the bias current can increase with RF input amplitude up to about 50 uA, which is still in the subthreshold region. Other bias current ranges are possible where the transistors differ in type and size.

Accordingly, all transistors M 0 and M 1 are biased in the subthreshold region so that the ED 100 operates more linearly as an envelope detector. When the amplitude of the input TX RF signal is more than zero, the voltage output (Vop and Von) will grow proportionally to the input amplitude as will be explained.

Transistor M 2 provides the bias current Ibp to transistors M 0 A and M 0 B and transistor M 3 provides the bias current Ibn to transistors M 1 A and M 1 B. The feedback linearizer 104 may be configured to set the bias voltage for transistors M 2 and M 3 , using the differential ED outputs, Vop and Von, as inputs.

The different ED outputs, Vop and Von, drive at least two transistors, M 8 and M 9 of the feedback linearizer 104 , which may be of a differential amplifier design. The output of the linearizer 104 is Vbn, which is proportional to V out , where V out equals Vop−Von. More specifically,

V bn =V bn — 0 +KV out   (9)

K is the gain of the linearizer, which is set approximately by Equation (10):

Because Vbn provides the bias voltage to M 2 and M 3 , which provide the bias current of the detection input transistors M 0 A through M 1 B, as Vout increases, the bias currents Ibp and Ibn will increase, which is the desired result as discussed with reference to FIGS. 7 and 8 . That is, because Ibp and Ibn increase as Vout increases, the transistors M 0 A through M 1 B may continue to operate in the more-linear subthreshold regions and over a wider amplitude range, including smaller and larger input amplitude RF signals.

The feedback linearizer 104 shown FIG. 10A may include a diffpair made up by transistors M 4 through M 11 in a feedback loop as shown in FIG. 9 , where Vop and Von directly drive transistors M 8 and M 9 , respectively. Degeneration resistor R 9 may be connected between sources of M 8 and M 9 . Transistor M 10 may have its drain connected to the drain of M 8 , where the drain of M 8 may drive the gate of transistor M 10 through resistor R 10 . Transistor M 9 may have its drain connected to the drain of M 11 , where the drain of M 9 may drive the gate of transistor M 11 through resistor R 11 . Resistors R 10 and R 11 may be connected to each other and to the gates of M 10 and M 11 . Resistors herein may also be referred to as impedances.

Transistors M 4 and M 6 may be connected in series and provide a first bias current to transistors M 8 and M 10 . Transistors M 5 and M 7 may be connected in series and provide a second bias current to transistors M 9 and M 11 .

Transistor M 12 may have a gate connected to gates of M 4 and M 5 and transistor M 13 may have a gate connected to gates of M 6 and M 7 . Transistors M 12 and M 13 may be connected in series to each other and be configured to set the first and second bias currents by driving the transistors M 4 through M 7 . A reference current bias block I 2 may generate bias voltages Vpbn and Vpcn through transistors M 12 and M 13 . Resistors R 13 and R 14 may be connected in series-like configuration to each other between the drain of the M 13 and the current bias block I 2 . A gate of the M 12 may be connected to the drain of M 13 and a gate of the M 13 may be connected between R 13 and R 14 .

The transistors of FIGS. 10A and 10B and the current bias block I 2 may be configured such that the output Vbn includes a bias voltage that is proportional to a difference between the positive and negative ED outputs (V out ) with which to drive the biasing transistors M 2 and M 3 , to keep the envelope-detecting transistors M 0 A through M 1 B operating in subthreshold regions despite a widened voltage amplitude range of a radio frequency (RF) signal input to the ED.

The feedback linearizer 104 may be effective over the bandwidth of an envelope that it is detecting, for instance, 2 MHz for the 3G standard, which is much smaller than the input signal frequency, for instance approximately 2 GHz.

The voltage bias generator 130 may include current bias block I 1 connected to power (Vdd) and transistor M 16 having a gate and a drain connected to the current bias block. A resistor R 52 may be connected between a source of M 16 and ground (Vss). The voltage bias generator 130 may be configured to adjust a bias voltage of the detecting transistors M 0 A through M 1 B to follow a threshold voltage variation of transistor M 16 , to maintain substantially constant bias voltages for the positive and negative ED outputs, Vop and Von.

Because detecting transistors M 0 A through M 1 B may be exposed to excessive voltages and because the ED 100 is configured to handle a widened voltage swing at the RF inputs, transistors M 0 A, M 0 B, M 1 A and M 1 B may be high-voltage (e.g., thick oxide) devices but powered with a lower voltage supply to ensure reliability. For example, the input voltage to each detecting transistor may be allowed to reach plus or minus about 1 (one) volt peak, but the detecting transistor may have voltage biases of about 300 mV. Following this example, V dg (the drain-gate voltage) of the M 0 transistors can be Vdd−(0.3−1)=Vdd+0.7, which is safe for thick oxide devices in a 40 nm process, for instance.

The feedback paths (Vop to Vbn and Von to Vbn) of the linearizer 104 do not require stringent linearity, as the paths are used to set both positive and negative bias currents, Ibp and Ibn. Because V out equals Vop minus Von, the nonlinear effect of either or both of the bias currents with respect to V out is cancelled out, which relaxes the linearizer circuit and makes it power and area efficient. Nevertheless, the degeneration resistor R 9 and the ratio of (R 11 +R 10 )/R 9 provide sufficiently stable and linear gain for operation of the linearizer circuit.

FIGS. 11A through 11D is an example complete ED core circuit 1002 , including the feedback linearizer 104 , with additional programmability capabilities for multi-mode adaptation. Additional calibration and adjustment options are not required but may be added to make the final design practical and for general use across varying communication standards (e.g., 2G/3G/LTE) of cellular transmitters.

As a multi-mode option, the complete ED core circuit 1002 may be converted to a standard ED, something like ED core 60 , by converting the linearizer 104 to a bias-only block. This conversion may be executed by disconnecting the linearizer inputs and grounding the linearizer inputs through switches M 44 , M 59 , M 60 and M 119 , M 120 and M 52 .

The bias current of the ED core 1002 may be further statically programmed by enabling transistors M 2 B, M 2 C, M 2 D and M 2 E and transistors M 3 B, M 3 C, M 3 D and M 3 E using control signals pdet_lup<0:1>. The voltage bias for M 0 A through M 1 B may also be generated separately to add the capability of varying the detecting transistors M 0 A through M 0 B separately, thus adding a DC voltage shift to Vout to accommodate the dynamic signal range of the next analog-to-digital converter 12 or buffer block input.

FIG. 12 is an example circuit of a typical radio frequency (RF) amplifier 210 , which may be used as voltage amplifiers 110 , 112 and 114 for the gain stages discussed with reference to FIG. 5 . The RF amplifier 210 of FIG. 12 may be designed with a complementary CMOS architecture using transistors M 1 , M 2 , M 3 and M 4 . A current bias block I 0 and degeneration resistor R 0 may be variable, to vary the gain of each stage. The gain amplifier stages may be AC-coupled to each other. Resistors R 1 and R 2 provide DC feedback that creates a bias at the differential inputs (RF_inp and RF_inn) and outputs (RF_outp and RF_outn) of the amplifier 210 .

FIGS. 13A and 13B is an example circuit of the class-AB RF amplifier 116 that may act as a pre-driver to the envelope detector 102 of FIGS. 5 and 9 - 11 . As the linear range extension of the ED 100 is both at higher and lower amplitude, the pre-driver or amplifier before the ED core 102 should be configured to handle a large signal swing up to 1 (one) volt (V) peak or more. The class-AB amplifier 116 of FIGS. 13A and 13B was specifically designed to handle this voltage swing and configured to operate within a full linear voltage range of the ED core 104 .

A core of the class-AB amplifier 116 may be complementary CMOS architecture, but any complementary transistor architecture will suffice, so CMOS devices are not required, as discussed. More specifically, transistors M 1 and M 2 may be complementary and connected in series to each other. Transistors M 3 and M 4 may be complementary and connected in series to each other. Transistors M 1 , M 2 , M 3 and M 4 include AC-coupled inputs from the RF input signal of the last of the voltage amplifiers, e.g. voltage amplifier 114 in FIG. 5 .

Separate biasing voltages, Vbp and Vpn, are provided in a feedback loop to, respectively, p-type transistors M 1 and M 3 and n-type transistors M 2 and M 4 . Transistor M 9 may provide a positive bias voltage to M 1 and M 3 . Transistor M 7 may provide a negative bias voltage to M 2 and M 4 . The different bias voltages provide maximum output peak-to-peak linear swing range close to the supply voltage Vdd of about 2.5V, for instance.

Simultaneously, the feedback circuitry including transistors M 5 through M 8 sets a common (DC) voltage at the output (V out — DC ) of the class-AB amplifier 116 close to half of the power supply voltage, e.g., about 1.25V for a Vdd of approximately 2.5V. This feedback of the common voltage may be performed through two negative paths of the class-AB amplifier, one that determines Vbn at transistor M 7 and the other that determines Vbn 1 at transistor M 8 . Voltage signals Vbn and Vbn 1 are determined by the arrangement of transistors M 9 through M 13 .

Transistors M 10 and M 11 may be connected in series to each other and to M 9 and be complementary to M 9 . Vbn, generated by M 8 , may then provide a bias voltage to M 10 and Vcn, generated by M 6 , may provide a bias voltage to M 10 . As Vbn 1 is increased, Vbp is lowered, which pulls V out — DC higher.

Transistors M 6 and M 8 may be complementary and connected in series with each other. Transistors M 5 and M 6 may also be complementary and connected in series with each other. Transistors M 12 and M 13 may be connected in series with each other, and may be a single transistor or two separate transistors. External bias signals Vpb 1 and Vpc 1 may drive gates of M 12 and M 13 , respectively, thus determining a bias current that is to be split between M 5 and M 7 on the one hand and M 6 and M 8 on the other.

When V out — DC decreases, more current will be drawn for M 6 and M 8 , setting Vbn 1 higher. A higher Vbn 1 increases current for M 9 , making Vbp go lower. As Vbp goes lower, V out — DC is pulled higher.

Simultaneously, currents sum for transistors M 5 through M 8 , which current is kept substantially constant as biased through externally-controlled Vpb 1 and Vpc 1 at gates of M 12 and M 13 . Accordingly, when currents drawn for M 6 and M 8 increases, currents drawn for M 5 and M 7 will decrease, resulting in a lower bias voltage provided to Vbn for transistors M 2 and M 4 . As Vbn goes lower, V out — DC goes higher.

By adjusting Vbn and Vbn 1 , therefore, the V out — DC common biasing voltage may also be set as equal to Cmref. Because resistance of resistors R 72 and R 71 may be equal and create a voltage divider, Cmref may be set to be about half of Vdd, the power supply voltage. A different ratio of Vdd may be used by adjusting resistance of resistors R 72 and R 71 , but setting V out — DC at about half Vdd provides the largest possible swing in input voltage of the class-AB amplifier 116 in both smaller signal and larger signal directions.

FIG. 14 is a graph of linear range improvement of the output of the ED core 102 of FIGS. 5 and 9 - 11 . FIG. 15 is a graph of the slope of the curves of the graph of FIG. 14 . The range is determined by the linear part of each curve of FIG. 14 . The dashed line shows a linear range of about 10.5 dB when the conventional ED core 60 is biased in saturation. The dotted line shows a linear range of about 14.5 dB when the conventional ED core 60 is biased in subthreshold. The dotted/dashed line shows a linear range of about 20 dB when the enhanced ED core 102 is biased in subthreshold and when its biasing transistors are driven by the linearizer 104 . A linear range of 20 dB is a significant improvement over the conventional ED core 60 , even when the conventional ED core is biased in subthreshold regions.

FIG. 16 is a graph of the ED output slope in decibels (dB) versus TX output power measure from a fabricated microchip for the enhanced ED 100 , showing additional linear range added by respective gain amplifier stages of FIG. 5 . The total linear range for the ED 100 is 60 dB with variable overlap greater than 4 dB between the gain amplifier stages, each of which can provide up to about 20 dB. A significant amount of overlap may be required by closed loop power control (CLPC) and other calibration algorithms. The gain stage settings may be set, however, to increase the total linear range but with less overlap.

Output 310 shows use of all the gain stages. At output 310 , the ED amplifiers may achieve a maximum gain, but at the lowest TX power. Output 320 shows use of one gain stage less than used for output 310 . Output 330 shows use of two gain stages less than used for output 310 . Output 340 shows use of three gain stages less than used for output 310 . Finally, output 350 shows an instance where even the class-AB amplifier 116 is bypassed to further reduce the gain, and thus the full linearity range of the ED core 102 cannot be utilized in this situation. Output 350 may provide an optional setting for higher power applications where there is less linearity required.

FIGS. 17A and 17B are, respectively, (a) a graph of an example envelope detected at the output of the ED of FIGS. 5 and 9 - 11 ; and (b) an example amplitude-modulated voltage input to the ED with an envelope varying over the linear range of the ED. FIG. 18 is an example graph of V out versus V in of the ED 100 with the linearizer 104 during simulation for different process, voltage, and temperature (PVT) corners.

The methods, devices, and logic described above may be implemented in many different ways in many different combinations of hardware, software or both hardware and software. For example, all or parts of the system may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.