Modularized control circuit with signal-capturing function for fan motor and controlling method

This application is based on and claims the benefit of Taiwan Application No. 101110416 filed Mar. 26, 2012 the entire disclosure of which is incorporated by reference herein.

1. Technical Field

The present disclosure relates generally to a control circuit for a fan motor and a method of controlling the same, and more particularly to a modularized control circuit with a signal-capturing function for a fan motor and a method of controlling the same.

2. Description of Related Art

For applications of the fan motor, a pulse-width modulation (PWM) technology is usually used to control speed, output power, and so forth of the fan motor. Because of different structures of the motor as well as various loads driven by the motor, the external PWM signal needs to be adjusted to drive and control the rotor of the motor according to practical conditions.

For the signal process of controlling the motor, the digital-to-analog conversion or the low-pass filtering are used to convert the pulse control signal into an analog voltage signal. Afterward, the analog voltage signal is processed by a control logic circuit or a microprocessor with an analog-to-digital function. However, it is easily to cause errors of capturing the frequency or the duty cycle of the pulse control signal because of the limitations of sensitivity of the low-pass filter or the digital-to-analog converter. In addition, a counter is usually used for count operations. Also, the normal operation of the counter is that one access action is executed in one triggering operation thereof. However, the triggering time needs to be increased if the counter has to execute consecutive access action. But, for this reason, it is easily to increase the error risk of setting the trigging time.

Accordingly, it is desirable to provide a modularized control circuit with a signal-capturing function for a fan motor and a method of controlling the same to increase the reliability and convenience of replacement of the control circuit for the fan motor by providing parameter setup via the software, firmware, and the hardware.

Accordingly, the modularized control circuit with a signal-capturing function operates a duty cycle of an external pulse signal for a fan motor. The modularized control circuit includes a driven circuit and a microcontroller integrated circuit. The driven circuit is electrically connected to the fan motor to produce at least one analog driven voltage signal for driving the fan motor. The microcontroller integrated circuit is electrically connected to the driven circuit and the microcontroller integrated circuit includes a signal-capturing module, a control unit, and a driven signal generator. The signal-capturing module is configured for receiving the external pulse signal to produce a cycle-capturing signal with the duty cycle of the external pulse signal. The control unit is connected to the signal-capturing module and is configured for receiving the cycle-capturing signal to produce a control signal. The driven signal generator is connected to the control unit and is configured for receiving the control signal to produce a plurality of switch driven signals for controlling the driven circuit.

Accordingly, the method of controlling the modularized control circuit with a signal-capturing function operates a duty cycle of an external pulse signal for a fan motor. The method includes following steps: (a) a driven circuit is provided to produce at least one analog driven voltage signal to drive the fan motor; (b) a signal-capturing module is provided to receive the external pulse signal and produce a cycle-capturing signal with the duty cycle of the external pulse signal; (c) a control unit is provided to receive the cycle-capturing signal and produce a control signal; and (d) a driven signal generator is provided to receive the control signal and produce a plurality of switch driven signals for controlling the driven circuit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims.

FIG. 1A is a schematic circuit diagram of a modularized control circuit with a signal-capturing function for a three-phase-driven fan motor according to the present invention;

FIG. 1B is a schematic circuit diagram of the modularized control circuit with the signal-capturing function for a full-bridge-driven fan motor according to the present invention;

FIGS. 2-4 are schematic circuit diagrams of a signal-capturing module of the modularized control circuit in accordance with some embodiments of the present invention;

FIG. 5A is a schematic view of operating a duty cycle of an external pulse signal by the signal-capturing module in FIG. 2 according to the present invention;

FIG. 5B is a schematic view of operating a duty cycle of an external pulse signal by the signal-capturing module in FIG. 3 according to the present invention; and

FIG. 6 is a flowchart of a method of controlling a modularized control circuit with a signal-capturing function for a fan motor according to the present invention.

Reference will now be made to the drawing figures to describe the present invention in detail.

Reference is made to FIG. 1A which is a schematic circuit diagram of a modularized control circuit with a signal-capturing function for a three-phase-driven fan motor according to the present invention. The modularized control circuit is provided to operate a duty cycle of an external pulse signal Sp for a fan motor 30 . The modularized control circuit includes a driven circuit 20 and a microcontroller integrated circuit 10 . More specifically, the external pulse signal Sp can be a pulse-width modulation signal or a pulse signal with arbitrary frequency for regulating and controlling speed of the fan motor 30 . In this embodiment, the pulse-width modulation signal is exemplified as the external pulse signal Sp to further demonstrate the present invention.

The driven circuit 20 is electrically connected to the fan motor 30 to produce at least one analog driven voltage signal (not shown) for driving the fan motor 30 . In this embodiment, the driven circuit 20 is a three-phase driven circuit having six switches on three sets of legs (not labeled). In addition, the fan motor 30 is a three-phase motor. Hence, the fan motor 30 is driven by a three-phase analog voltage signal, which is produced from the driven circuit 20 , composed of U-, V-, and W-phase analog voltage components. In addition, reference is made to FIG. 1B which is a schematic circuit diagram of the modularized control circuit with the signal-capturing function for a full-bridge-driven fan motor according to the present invention. In this embodiment, the driven circuit 20 is a full-bridge driven circuit having four switches on two sets of legs (not labeled). In addition, the fan motor 30 is a single-phase motor. Hence, the fan motor 30 is driven by a single-phase analog voltage signal which is produced from the driven circuit 20 . Furthermore, the driven circuit 20 can be also a half-bridge driven circuit (not shown) having two switches on a set of leg to drive a single-phase fan motor 30 . For convenience explanation, the three-phase motor and the three-phase driven circuit are exemplified as the fan motor 30 and the driven circuit 20 , respectively, to further demonstrate the present invention.

The microcontroller integrated circuit 10 is electrically connected to the driven circuit 20 . The microcontroller integrated circuit 10 includes a signal-capturing module 102 , a control unit 104 , and a driven signal generator 106 . In particular, the microcontroller integrated circuit 10 can be a microprocessor (μP), a microcontroller (μC), a field-programmable gate array (FPGA), a programmable integrated circuit, an application-specific integrated circuit (ASIC), or so on, but not limited. The signal-capturing module 102 receives the external pulse signal Sp to produce a cycle-capturing signal Sca with the duty cycle of the external pulse signal Sp. The control unit 104 is connected to the signal-capturing module 102 and receives the cycle-capturing signal Sca to produce a control signal Scn. The driven signal generator 106 is connected to the control unit 104 and receives the control signal Scn to produce a plurality of switch driven signals (not labeled) for controlling the driven circuit 20 . In particular, the switch driven signals are provided to control the six switches on three sets of legs.

The detailed description of operating the modularized control circuit will be made hereinafter. Reference is made to FIG. 2 which is a schematic circuit diagram of a signal-capturing module of the modularized control circuit according to a first embodiment of the present invention. The signal-capturing module 102 includes a trigger control circuit 1021 , a count unit 1022 , a first register 1023 , a second register 1024 , a divider unit 1025 , and a third register 1026 .

The trigger control circuit 1021 has an input terminal (not labeled), a trigger select terminal (not labeled), and a plurality of control output terminals (not labeled). The input terminal receives the external pulse signal Sp. The trigger select terminal receives a trigger select signal St to provide a rising-edge trigging operation or a falling-edge trigging operation. That is, the trigger control circuit 1021 executes a duty cycle operation to the external pulse signal Sp when a level transition of the external pulse signal Sp, namely, high level to low level or low level to high level thereof. In particular, these control output terminals produce a plurality of control signals, respectively. In this embodiment, these control signals are a rest signal Srt to a count unit, an enable signal EN to the count unit 1022 , a reset signal Sr 1 to a first register 1023 , a reset signal Sr 2 to a second register 1024 , a latch signal Sh 1 to the first register 1023 , and a latch signal Sh 2 to the second register 1024 , but not limited. Note that, other different control signals may be provided depending on different implementations.

The count unit 1022 is connected to the trigger control circuit 1021 to receive a system clock signal CLK, the reset signal Srt to the count unit 1022 , and the enable signal EN to the count unit 1022 to produce a first count value C 1 and a second count value C 2 . In particular, the count unit 1022 is either synchronously or asynchronously reset. The first register 1023 is connected to the trigger control circuit 1021 to receive the reset signal Sr 1 to the first register 1023 , the first count value C 1 , and the latch signal Sh 1 to the first register 1023 . The second register 1024 is connected to the trigger control circuit 1021 to receive the reset signal Sr 2 to the second register 1024 , the second count value C 2 , and the latch signal Sh 2 to the second register 1024 . The divider unit 1025 is connected to the first register 1023 and the second register 1024 to receive the first count value C 1 and the second count value C 2 and the divider unit 1025 provides a division operation on the first count value C 1 and the second count value C 2 to produce the cycle-capturing signal Sca. The third register 1026 is connected to the divider unit 1025 to receive and output the cycle-capturing signal Sca.

The detailed operation of the trigger control circuit 1021 will be made hereinafter with reference to FIG. 5A which is a schematic view of operating a duty cycle of an external pulse signal by the signal-capturing module in FIG. 2 according to the present invention. In this embodiment, the trigger control circuit 1021 provides a time difference between a rising-edge trigging operation and a falling-edge trigging operation as a turned-on-period time of the external pulse signal Sp and provides a time difference between two rising-edge trigging operations as a full-period time of the external pulse signal Sp.

The trigger control circuit 1021 sends the high-level enable signal EN to the count unit 1022 to enable the count unit 1022 starting to count when the trigger control circuit 1021 detects that a level transition from a low level to a high level of the external pulse signal Sp. In particular, the count unit 1022 can provide either an up-count mode operation or a down-count mode operation. In addition, the trigger control circuit 1021 sends the a high-level reset signal Srt to reset the count value of the count unit 1022 in zero or the maximum value according to the up-count mode or down-count mode operation before the count unit 1022 acts.

The trigger control circuit 1021 sends the latch signal Sh 1 to latch the first register 1023 and sends the first count value C 1 of the count unit 1022 to the first register 1023 and the divider unit 1025 when the trigger control circuit 1021 detects that a level transition from a high level to a low level of the external pulse signal Sp. Similarly, the trigger control circuit 1021 sends the latch signal Sh 2 to latch the second register 1024 and sends the second count value C 2 of the count unit 1022 to the second register 1024 and the divider unit 1025 when the trigger control circuit 1021 detects that a level transition from a low level to a high level of the external pulse signal Sp.

The divider unit 1025 receives the first count value C 1 in the first register 1023 and the second count value C 2 in the second register 1024 , respectively, to provide a division operation on the first count value C 1 and the second count value C 2 to produce the cycle-capturing signal Sca with the duty cycle of the external pulse signal Sp. That is, in this embodiment, the duty cycle of the external pulse signal Sp is equal to a ratio of the first count value C 1 to the second count value C 2 . If it is assumed that the first count value C 1 is 80 and the second count value C 2 is 100, the duty cycle of the external pulse signal Sp is equal to 80% (namely, 80/100×100%=80%).

Especially, the above-mentioned turned-on-period time and full-period time are not limited to be provided by the first register 1023 and the second register 1024 , respectively. In other words, the first register 1023 can exchange its role with the second register 1024 to provide the full-period time and the turned-on-period time is provided by the second register 1024 .

Reference is made to FIG. 5B which is a schematic view of operating a duty cycle of an external pulse signal by the signal-capturing module in FIG. 3 according to the present invention. In this embodiment, the trigger control circuit 1021 provides a time difference between a rising-edge trigging operation and a falling-edge trigging operation as a turned-on-period time of the external pulse signal Sp and provides a time difference between a falling-edge trigging operation and a rising-edge trigging operation as a turned-off-period time of the external pulse signal Sp. Especially, the signal-capturing module 102 further has an adder unit 1027 . The adder unit 1027 is connected to the first register 1023 and the second register 1024 to receive the first count value C 1 ′ and the second count value C 2 ′ and provides an addition operation on the first count value C 1 ′ and the second count value C 2 ′ to produce an added value.

The trigger control circuit 1021 sends the high-level enable signal EN to the count unit 1022 to enable the count unit 1022 starting to count when the when trigger control circuit 1021 detects that a level transition from a low level to a high level of the external pulse signal Sp. In particular, the count unit 1022 can provide either an up-count mode operation or a down-count mode operation. In addition, the trigger control circuit 1021 sends the a high-level reset signal Srt to reset the count value of the count unit 1022 in zero or the maximum value according to the up-count mode or down-count mode operation before the count unit 1022 acts.

The trigger control circuit 1021 sends the latch signal Sh 1 to latch the first register 1023 and sends the first count value C 1 ′ of the count unit 1022 to the first register 1023 and the divider unit 1025 when the trigger control circuit 1021 detects that a level transition from a high level to a low level of the external pulse signal Sp. Moreover, the trigger control circuit 1021 sends the high-level reset signal Srt to reset the count value of the count unit 1022 in zero or the maximum value. In addition, the trigger control circuit 1021 sends the latch signal Sh 2 to latch the second register 1024 and sends the second count value C 2 ′ of the count unit 1022 to the second register 1024 and the adder unit 1027 when the trigger control circuit 1021 detects that a level transition from a low level to a high level of the external pulse signal Sp.

The divider unit 1025 receives the first count value C 1 ′ in the first register 1023 and a sum value of the first count value C 1 ′ and the second count value C 2 ′ (namely, C 1 ′+C 2 ′) and the divider unit 1025 provides a division operation on the first count value C 1 ′ and the sum value C 1 ′+C 2 ′ to produce the cycle-capturing signal Sca with the duty cycle of the external pulse signal Sp. That is, in this embodiment, the duty cycle of the external pulse signal Sp is equal to a ratio of the first count value C 1 ′ to the sum value C 1 ′+C 2 ′. If it is assumed that the first count value C 1 ′ is 80 and the second count value C 2 ′ is 20, the duty cycle of the external pulse signal Sp is equal to 80% (namely, 80/(80+20)×100%=80%).

Especially, the above-mentioned turned-on-period time and turned-off-period time are not limited to be provided by the first register 1023 and the second register 1024 , respectively. In other words, the first register 1023 can exchange its role with the second register 1024 to provide the turned-off-period time and the turned-on-period time is provided by the second register 1024 .

In addition, the signal-capturing module 102 further has an overflow count unit (not shown), a first overflow register (not shown), and a second overflow register (not shown). The overflow count unit is connected to the trigger control circuit 1021 to provide an overflow operation of the count unit 1022 . That is, the trigger control circuit 1021 sends a reset signal or a set signal to control the overflow count unit when an overflow occurs during the count operation of the count unit 1022 .

The first overflow register is connected to the trigger control circuit 1021 to provide an overflow operation of the first register 1023 . That is, the trigger control circuit 1021 sends a reset signal or a set signal to control the first overflow register when an overflow occurs during the data-registering operation of the first register 1023 . Similarly, the second overflow register is connected to the trigger control circuit 1021 to provide an overflow operation of the second register 1024 . That is, the trigger control circuit 1021 sends a reset signal or a set signal to control the second overflow register when an overflow occurs during the data-registering operation of the second register 1024 .

Reference is made to FIG. 4 which is a schematic circuit diagram of the signal-capturing module of the modularized control circuit according to a third embodiment of the present invention. The main difference between the third embodiment and the first embodiment is that the signal-capturing module 102 further has a prescaler unit 1028 , but the rest is the same. The prescaler unit 1028 is connected to the count unit 1022 to receive the system clock signal CLK and process a duty cycle of the system clock signal CLK, and then the processed system clock signal, namely, a prescale clock signal CLK 2 , is sent to the count unit 1022 to be a system clock reference for the count unit 1022 . Because the operation is the same at the third embodiment and the first embodiment except the prescaler unit 1028 , the detail description is omitted here for conciseness.

Reference is made to FIG. 6 which is a flowchart of a method of controlling a modularized control circuit with a signal-capturing function for a fan motor according to the present invention. The method of controlling the modularized control circuit with a signal-capturing function operates a duty cycle of an external pulse signal for a fan motor. The method includes following steps: A driven circuit is provided to produce at least one analog driven voltage to drive the fan motor (S 100 ). More specifically, the external pulse signal can be a pulse-width modulation signal or a pulse signal with arbitrary frequency for regulating and controlling speed of the fan motor.

A signal-capturing module is provided to receive the external pulse signal and produce a cycle-capturing signal with the duty cycle of the external pulse signal (S 200 ). In particular, the signal-capturing module has a trigger control circuit, a count unit, a first register, a second register, a divider unit, and a third register.

The trigger control circuit has an input terminal, a trigger select terminal, and a plurality of control output terminals. The input terminal receives the external pulse signal. The trigger select terminal receives a trigger select signal to provide a rising-edge trigging operation and a falling-edge trigging operation. That is, the trigger control circuit executes a duty cycle operation to the external pulse signal when a level transition of the external pulse signal, namely, high level to low level or low level to high level thereof. The control output terminals output a rest signal to the count unit, an enable signal to the count unit, a rest signal to the first register, a rest signal to the second register, a latch signal to the first register, and a latch signal to the second register.

The count unit is connected to the trigger control circuit to receive a system clock signal, the reset signal to the count unit, and the enable signal to the count unit to produce a first count value and a second count value. In particular, the count unit is either synchronously or asynchronously reset. The first register is connected to the trigger control circuit to receive the reset signal to the first register, the first count value, and the latch signal to the first register. The second register is connected to the trigger control circuit to receive the reset signal to the second register, the second count value, and the latch signal to the second register. The divider unit is connected to the first register and the second register to receive the first count value and the second count value and the divider unit provides a division operation on the first count value and the second value to produce the cycle-capturing signal. The third register is connected to the divider unit to receive and output the cycle-capturing signal.

The signal-capturing module further has an adder unit. The adder unit is connected to the first register and the second register to receive the first count value and the second count value and provides an addition operation on the first count value and the second count value to produce an added value. In particular, the added value is sent to the divider unit. The divider unit provides a division operation on the first count value and the added value to produce a divided result and the divided result is sent to the third register to produce the cycle-capturing signal. The signal-capturing module further has an overflow count unit, a first overflow register, a second overflow register. The overflow count unit is connected to the trigger control circuit to provide an overflow operation of the count unit. The first overflow register is connected to the trigger control circuit to provide an overflow operation of the first register. The second overflow register is connected to the trigger control circuit to provide an overflow operation of the second register. The signal-capturing module further has a prescaler unit. The prescaler unit is connected to the count unit to receive the system clock signal and process a duty cycle of the system clock signal, and then the processed system clock signal is sent to the count unit. A control unit is provided to receive the cycle-capturing signal with the duty cycle of the external pulse signal (S 300 ). A driven signal generator is provided to receive the control signal and produce a plurality of switch driven signals for controlling the driven circuit (S 400 ). Especially, the signal-capturing module, the control unit, and the driven signal generator are packaged into a microcontroller integrated circuit. In addition, the microcontroller integration circuit is a microprocessor (μP), a microcontroller (μC), a field-programmable gate array (FPGA), a programmable integrated circuit, an application-specific integrated circuit (ASIC), or so on, but not limited.

In conclusion, the present invention has following advantages:

1. The signal-capturing module 102 , the control unit 104 , and the driven signal generator 106 are packaged into a microcontroller integrated circuit, which is controlled by software, firmware, or hardware to increase reliability of operating the modularized control circuit and convenience of replacing thereof; and

2. The signal-capturing module 102 is provided to operate a duty cycle of the external pulse signal Sp. When the trigger control circuit 1021 detects that a level transition of the external pulse signal Sp, the count unit 1022 is used to provide count operations and a plurality of registers are used to provide consecutive access without resetting triggering times.

Although several embodiments of the present invention have been described in detail, it will be understood that the disclosure is not limited to such details. Various substitutions will occur to those of ordinary skill in the art of the foregoing description. Therefore, all such substitutions and modifications are intended to be embraced within the scope of this disclosure.