Display controller and related method of operation

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0104349 filed on Oct. 13, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

The inventive concept relates generally to display technologies. More particularly, the inventive concept relates to a display controller for a three-dimensional (3D) display system and related methods of operation.

Many 3D display systems rely on the principle of stereoscopy, which is a technique for creating the illusion of depth in a two-dimensional (2D) image by presenting two offset images separately to a viewer's left and right eyes. The two offset images are combined in the viewer's brain to create a perception of 3D depth.

A 3D display system can use various alternative formats to display the two offset images. The most common formats use interleaved pixel data to represent the two offset images. In general, the format used to display the images can influence the required processing and components required. This in turn can influence factors such as cost and performance of the 3D display system.

In an embodiment of the inventive concept, a display controller comprises a merger and an alpha blender. The merger is configured to mix a first left frame comprising first left pixel data and a first right frame comprising first right pixel data based on a 3D display format, and is further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame.

In another embodiment of the inventive concept, a method of operating a display controller comprises receiving a first left frame comprising multiple units of first left pixel data, receiving a first right frame comprising multiple units of first right pixel data, and generating a first mixed frame and a second mixed frame by mixing the first left frame and the first right frame according to a 3D display format.

In another embodiment of the inventive concept, a method of operating a display controller comprises operating a merger to mix a first left frame comprising first left pixel data and a first right frame comprising first right pixel data based on a three-dimensional (3D) display format to produce a first mixed frame and a second mixed frame, and operating an alpha blender to blend the first mixed frame and the second mixed frame to produce a first blended frame.

These and other embodiments of the inventive concept may provide stereoscopic perception of 3D depth to a viewer according to the format of pixel data displayed on a 3D display by using a merger. Among other things, this can potentially eliminate a need for an extra chip.

The drawings illustrate selected embodiments of the inventive concept. In the drawings, like reference numbers indicate like features.

FIG. 1 is a block diagram of a 3D display system comprising a display controller according to an embodiment of the inventive concept.

FIG. 2 is a block diagram of a 3D display illustrated in FIG. 1 according to an embodiment of the inventive concept.

FIGS. 3 through 5 are diagrams of various formats of pixel data that can be used in the 3D display illustrated in FIG. 1 according to embodiments of the inventive concept.

FIG. 6 is a block diagram of a processor illustrated in FIG. 1 according to an embodiment of the inventive concept.

FIG. 7 is a block diagram of a display controller illustrated in FIG. 1 according to an embodiment of the inventive concept.

FIG. 8 is a timing chart showing the operation of a merger illustrated in FIG. 7 according to an embodiment of the inventive concept.

FIG. 9 is a timing chart showing the operation of the merger illustrated in FIG. 7 according to an embodiment of the inventive concept.

FIG. 10 is a flowchart of a method for operating the display controller illustrated in FIG. 1 according to an embodiment of the inventive concept.

Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

In the description that follows, where a feature is referred to as being “connected” or “coupled” to another feature, it can be directly connected or coupled to the other feature or intervening features may be present. In contrast, where a feature is referred to as being “directly connected” or “directly coupled” to another feature, there are no intervening features present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

Although the terms first, second, etc., may be used to describe various features, these features should not be limited by these terms. Rather, these terms are used merely to distinguish between different features. For example, a first feature could alternatively be termed a second feature and vice versa without changing the meaning of the relevant description.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to encompass the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises” and/or “comprising,” or “includes” and/or “including” indicate the presence of stated features but do not preclude the presence other features.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram of a 3D display system 100 comprising a display controller 10 according to an embodiment of the inventive concept. 3D display system 100 may take various alternative forms and can be used in various types of systems. For instance, it can be implemented as part of a television, a cellular phone, a smart phone, a tablet, a personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal or portable navigation device (PND), a handheld game console, or a hand held device such as an e-reader.

Referring to FIG. 1 , 3D display system 100 comprises a processor 1 , a memory 110 , an input device 120 , and a 3D display 130 .

Processor 1 controls operation of 3D display system 100 . Processor 1 is typically implemented as an application processor, and it can be formed in a single integrated circuit. However, processor 1 is not limited to these characteristics and can take alternative forms as well.

During typical operation, processor 1 reads and executes program instructions, and it reads data from memory 110 . Processor 1 may execute program instructions in response to signals input through input device 120 or other portions of 3D display system 100 .

A part of memory 110 stores a plurality of frames to be displayed as a 3D image in 3D display 130 . In other words, part of memory 110 functions as a frame buffer.

Input device 120 can comprise any type of interface capable of receiving input from a user. For example, it can be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

FIG. 2 is a block diagram of 3D display 130 according to an embodiment of the inventive concept. 3D display 130 can take various alternative forms, such as a liquid crystal display, a light emitting diode (LED) display, an organic LED (OLED) display, or an active matrix OLED display, to name but a few.

Referring to FIG. 2 , 3D display 130 comprises a parallax barrier 131 and a pixel array 133 . It generates a left image LI and a right image RI to be presented to a viewer 125 having a right eye 127 and a left eye 129 .

Pixel array 133 emits light corresponding to left and right images LI and RI, and parallax barrier 131 filters the emitted light to generate left image LI and right image RI. In other words, parallax barrier 131 creates effects that give viewer 125 the stereoscopic perception of 3D depth. Parallax barrier 131 comprises a plurality of barrier elements that perform the filtering of light emitted from pixel array 133 .

3D display 130 may support various 3D display formats to present left image LI and right image RI to viewer 125 . These formats may include, for instance, a pixel barrier format, a sub-pixel barrier format, and a line barrier format.

Right image RI and left image LI are separately presented to right eye 127 and left eye 129 of viewer 125 and combined in the brain of viewer 125 . Accordingly, viewer 125 receives the stereoscopic perception of 3D depth. To present left image LI and right image RI in a 3D display format (e.g., the pixel barrier format, the sub-pixel barrier format or the line barrier format), the display controller provides a frame in the 3D display format to 3D display 130 . The barrier elements may be arranged in various ways according to the 3D display formats.

Pixel array 133 comprises a plurality of pixels, which emit light comprising pixel data. The emitted light is filtered by parallax barrier 131 . Parallax barrier 131 operates as an image filter to filter the emitted light. 3D display system 100 using parallax barrier 131 is referred to as an auto-stereoscopic system. 3D glasses (not shown) may be used instead of parallax barrier 131 in other embodiments.

FIGS. 3 through 5 are diagrams of various formats of pixel data that can be used in the 3D display illustrated in FIG. 1 according to embodiments of the inventive concept. In particular, FIG. 3 shows a pixel barrier format, FIG. 4 shows a sub-pixel barrier format, and FIG. 5 shows a line barrier format. In FIGS. 3 through 5 , each square represents pixel data. The pixel data may be referred to a color component or a sub pixel.

In FIGS. 3 through 5 , “L R ”, “L G ” and “L B ” denote respective red, green and blue components that form left image LI and “R R ”, “R G ” and “R B ” denote respective red, green and blue components that form right image RI. In alternative embodiments, the red, green and blue components may be replaced with a single luminance (luma) component and two chrominance components, for example.

The color of each pixel in left image LI may be represented using pixel data L R , L G and L B , and the color of each pixel in right image RI may be represented using pixel data R R , R G and R B . For instance, a pixel color may be represented by 24-bit color, with each unit of pixel data L R , L G and L B being represented by 8 bits. As an example, in left image LI, where a pixel color is red, all bits in the corresponding pixel data L R are 1 and every bit in the corresponding pixel data L G and L B is 0. Alternatively, the pixel color can be represented by 16-bit color. For example, pixel data L R and pixel data L G may be represented by 5 bits and pixel data L B may be represented by 6 bits. In various alternative embodiments, the pixel color can be represented using other numbers of bits.

3D display 130 displays pixel data L R , L G and L B , R R , R G and R B in a format shown in FIG. 3 , 4 , or 5 using pixel array 133 . The pixel data is typically provided to 3D display 130 by display controller 10 . Multiple units of left pixel data L R , L G and L B form left image LI in parallax barrier 131 , and multiple units of right pixel data R R , R G and R B form right image RI in parallax barrier 131 .

FIG. 6 is a block diagram of processor 1 according to an embodiment of the inventive concept.

Referring to FIG. 6 , processor 1 comprises a central processing unit (CPU) 3 , a system peripheral unit 5 , a media acceleration unit 6 , a connectivity unit 7 , a memory interface unit 9 , and display controller 10 . These features communicate with each other through a system bus 11 .

CPU 3 reads and executes program instructions and controls the operation of display controller 10 . System peripheral unit 5 comprises a real-time clock (RTC), a phase-locked loop (PLL), and a watch dog timer.

The PLL is used to generate a clock for driving processor 1 . Memory interface unit 9 receives a plurality of frames from the part of memory 110 that functions as a frame buffer. Display controller 10 provides 3D display 130 a plurality of control signals and frames comprising a plurality of pixels so that right image RI and left image LI are separately presented to right eye 127 and left eye 129 of viewer 125 .

Multimedia acceleration unit 6 comprises a graphics engine. In some embodiments, multimedia acceleration unit 6 comprises a camera interface, a graphics engine integrated with a video display circuitry to carry out graphic calculation, or a high-definition multimedia interface (HDMI). In some embodiments, multimedia acceleration unit 6 comprises an interface complying with national television system committee/phase alternate line (HTSC/PAL) standards instead of the HDMI.

Connectivity unit 7 communicates with input device 120 and comprises an audio interface, a storage interface such as an advanced technology attachment (ATA) interface, and a connectivity interface.

FIG. 7 is a block diagram of display controller 10 illustrated in FIG. 1 according to an embodiment of the inventive concept.

Referring to FIG. 7 , display controller 10 comprises a timing generator 13 and a 3D formatter 20 .

Timing generator 13 generates a plurality of control signals CS according to a 3D display format. For instance, control signals CS may comprise a horizontal synchronous signal and a vertical synchronous signal which are used for synchronization of a plurality of pixel data.

3D formatter 20 receives a first left frame LF 1 and a first right frame RF 1 from memory 110 and outputs a blended frame BF 1 according to a 3D display format. First left frame LF 1 comprises multiple units of left pixel data L R , L G and L B and first right frame RF 1 comprises multiple units of right pixel data R R , R G and R B . First left frame LF 1 and first right frame RF 1 are mixed with each other according to a predetermined 3D display format, such as the pixel barrier format, the sub-pixel barrier format, or the line barrier format. In the embodiment of FIG. 6 , memory interface unit 9 can be used to receive first left frame LF 1 and first right frame RF 1 .

3D formatter 20 comprises a first merger 21 , a control register block 23 , and a first alpha blender 35 . First merger 21 mixes first left frame LF 1 with first right frame RF 1 according to the 3D display format and outputs a first mixed frame MF 1 and a second mixed frame MF 2 . For instance, where the 3D display format is the pixel barrier format, first mixed frame MF 1 may be organized similar to FIG. 3 . First mixed frame MF 1 may be generated by alternating the order in which units of left pixel data in first left frame LF 1 are arranged and the order in which units of right pixel data in first right frame RF 1 are arranged. First mixed frame MF 1 and second mixed frame MF 2 may be complementary to each other. In other words, where first mixed frame MF 1 comprises pixel data in order of L R , L G , L B , R R , R G , and R B , second mixed frame MF 2 may comprise pixel data in order of R R , R G , R B , L R , L G , and L B .

Where the 3D display format is the sub-pixel barrier format, first mixed frame MF 1 may be organized similar to FIG. 4 . In this format, first mixed frame MF 1 may comprise pixel data in order of L R , R G , L B , R R , L G , and R B , and second mixed frame MF 2 may comprise a plurality of pixel data in order of R R , L G , R B , L R , R G , and L B .

Where the 3D display format is the line barrier format, first mixed frame MF 1 may be organized similar to FIG. 5 . In this format, first mixed frame MF 1 may comprise left pixel data L R , L G , L B , L R , L G , L B , L R , L G , and L B in odd-numbered lines Line 1 and Line 3 and right pixel data R R , R G , R B , R R , R G , R B , R R , R G , and R B in even-numbered lines Line 2 and Line 4 .

First merger 21 also receives a first input valid signal ILV 1 indicating the input of first left frame LF 1 and a second input valid signal IRV 1 indicating the input of first right frame RF 1 from the part of memory 110 . First merger 21 outputs a first output valid signal OV 1 indicating the output of first mixed frame MF 1 and a second output valid signal OV 2 indicating the output of second mixed frame MF 2 .

Control register block 23 comprises a plurality of control registers 25 , 27 , 29 and 31 . Each of control registers 25 , 27 , 29 and 31 may be referred to as a special function register (SFR). Control registers 25 , 27 , 29 and 31 are used to control the operation of first merger 21 . For instance, where a bit value of the first control register 25 is set to “1”, first merger 21 performs a mixing operation in which first left frame LF 1 is mixed with first right frame RF 1 according to the 3D display format and first and second mixed frames MF 1 and MF 2 are output.

Second control register 27 is used to determine which of left pixel data (e.g., L R ) and right pixel data (e.g., R R ) will come first in first mixed frame MF 1 . For instance, where a bit value of the second control register 27 is set to “1”, the left pixel data (e.g., L R ) comes first in first mixed frame MF 1 . Where the bit value of the second control register 27 is set to “0”, the right pixel data (e.g., R R ) comes first in first mixed frame MF 1 .

First merger 21 may also perform interpolation. The interpolation typically comprises averaging at least two pixel data among a plurality of left pixel data in first left frame LF 1 and averaging at least two pixel data among a plurality of right pixel data in first right frame RF 1 in order to maintain high display quality.

After performing interpolation, first merger 21 outputs first and second mixed frames MF 1 and MF 2 comprising pixel data (e.g., (L R +L G )/2) resulting from averaging at least two pixel data among the plurality of left pixel data, and pixel data (e.g., (R R +R G )/2) resulting from averaging at least two pixel data among the plurality of right pixel data.

Third control register 29 may also be used to perform the interpolation. For instance, where a bit value of the third control register 29 is set to “1”, interpolation may be performed. Where the 3D display format is the line barrier format, 3D formatter 20 may further comprise a line counter 33 which counts lines in first left and right frames LF 1 and RF 1 .

First merger 21 selects lines from first left and right frames LF 1 and RF 1 according to counter values counted by line counter 33 and mixes the selected lines with one another to produce first mixed frame MF 1 and the second mixed frame MF 2 .

Fourth control register 31 is used to support the line barrier format. For instance, where a bit value of the fourth control register 31 is set to “1”, first merger 21 outputs first and second mixed frames MF 1 and MF 2 supporting the line barrier format.

First alpha blender 35 outputs a first blended frame BF 1 by blending the first and second mixed frames MF 1 and MF 2 using the following equation (1).

C=Aα+B (1−α)  (1)

In equation (1), “C” represents first blended frame BF 1 , “A” represents first mixed frame MF 1 , “B” represents second mixed frame MF 2 , and “α” is an alpha value of first alpha blender 35 . The alpha value of first alpha blender 35 is typically “0” or “1”. Accordingly, first blended frame BF 1 is either first mixed frame MF 1 or the second mixed frame MF 2 . Display controller 10 provides first blended frame BF 1 to 3D display 130 .

3D formatter 20 further comprises a second merger 41 , a control register block 43 , a line counter 53 , and a plurality of alpha blenders 55 and 57 . Second merger 41 mixes a second left frame LF 2 comprising a plurality of left pixel data and a second right frame RF 2 comprising a plurality of right pixel data and outputs a third mixed frame MF 3 and a fourth mixed frame MF 4 .

Each of third and fourth mixed frames MF 3 and MF 4 has a format illustrated in FIG. 3 , 4 , or 5 . Second alpha blender 55 blends third mixed frame MF 3 and first blended frame BF 1 and outputs a second blended frame BF 2 . An alpha value of second alpha blender 55 is between “0” and “1”. Third alpha blender 57 blends fourth mixed frame MF 4 and the second blended frame BF 2 and outputs a third blended frame BF 3 . Display controller 10 provides third blended frame BF 3 to 3D display 130 . An alpha value of third alpha blender 57 is between “0” and “1”.

Frames LF 2 and RF 2 , input valid signals ILV 2 and IRV 2 , mixed frames MF 3 and MF 4 , and output valid signals OV 3 and OV 4 are similar to the frames LF 1 and RF 1 , input valid signals ILV 1 and IRV 1 , mixed frames MF 1 and MF 2 , and output valid signals OV 1 and OV 2 . Accordingly, further description of these features will be omitted in order to avoid redundancy.

The operations and functions of control registers 45 , 47 , 49 , and 51 in the control register block 43 and a line counter 53 are similar to those of control registers 24 , 27 , 29 , and 31 in the control register block 23 and line counter 33 . Accordingly, further description of these features will be omitted in order to avoid redundancy.

3D formatter 20 further comprises a fourth alpha blender 59 . Fourth alpha blender 59 blends third blended frame BF 3 and a third frame F 3 and outputs a fourth blended frame BF 4 . Third frame F 3 is a two-dimensional (2D) video or image output from the part of memory 110 .

Display controller 10 provides fourth blended frame BF 4 to 3D display 130 . An alpha value of fourth alpha blender 59 is between “0” and “1”.

For clarity of the description, two mergers 21 and 41 and four alpha blenders 35 , 55 , 57 , and 59 are illustrated in FIG. 7 . However, the numbers of mergers and alpha blenders may change in other embodiments.

FIG. 8 is a timing chart showing the operation of merger 21 illustrated in FIG. 7 according to an embodiment of the inventive concept.

Referring to FIG. 8 , it is assumed that the bit values of the first and second control registers 25 and 27 are “1” and bit values of third and fourth control registers 29 and 31 are “0”. A clock signal CLK is generated by the PLL.

Where first input valid signal ILV 1 is high, first merger 21 receives first left frame LF 1 from the part of memory 110 that corresponds to a frame buffer. Here, signals labeled X 0 through X 8 represent left pixel data (e.g., L R , L G , or L B ) or left pixel color comprising a plurality of left pixel data (e.g., L R , L G , and L B ). Similarly, where second input valid signal IRV 1 is high, first merger 21 receives first right frame RF 1 from the part of memory 110 . Here, signals labeled Y 0 through Y 8 represent right pixel data (e.g., R R , R G , or R B ) or right pixel color comprising a plurality of right pixel data (e.g., R R , R G , and R B ).

Where first output valid signal OV 1 is high, first merger 21 performs the mixing operation and outputs first mixed frame MF 1 . First mixed frame MF 1 typically comprises left pixel data (e.g., L R , L G , or L B ) and right pixel data (e.g., R R , R G , or R B ) or left pixel color and right pixel color. Where first mixed frame MF 1 comprises the left pixel color and the right pixel color, first mixed frame MF 1 typically has the pixel barrier format illustrated in FIG. 3 . On the other hand, where first mixed frame MF 1 comprises left pixel data (e.g., L R , L G , or L B ) and right pixel data (e.g., R R , R G , or R B ), first mixed frame MF 1 has the sub-pixel barrier format illustrated in FIG. 4 . Where second output valid signal OV 2 is high, first merger 21 performs the mix operation and outputs second mixed frame MF 2 .

First mixed frame MF 1 and second mixed frame MF 2 are complementary to each other. For example, where first mixed frame MF 1 comprises X 0 , Y 1 , X 2 , Y 3 , X 4 and Y 5 in order, second mixed frame MF 2 may comprise Y 0 , X 1 , Y 2 , X 3 , Y 4 and X 5 in order.

FIG. 9 is a timing chart showing the operation of merger 21 illustrated in FIG. 7 according to an embodiment of the inventive concept.

Referring to FIG. 9 , it is assumed that the bit values of the first through third control registers 25 , 27 , and 29 are “1” and the bit value of the fourth control register 31 is “0”.

Clock signal CLK, input valid signals ILV 1 and IRV 1 , frames LF 1 and RF 1 and the output valid signals OV 1 and OV 2 illustrated in FIG. 9 are similar to those illustrated in FIG. 8 . Accordingly, further description of these features will be omitted in order to avoid redundancy.

Here, signals labeled X 0 through X 8 represent left pixel data (e.g., L R , L G , or L B ) or left pixel color comprising a plurality of left pixel data (e.g., L R , L G , and L B ). Signals labeled Y 0 through Y 8 represent right pixel data (e.g., R R , R G , or R B ) or right pixel color comprising a plurality of right pixel data (e.g., R R , R G , and R B ).

Because the bit value of third control register 29 used to perform the interpolation is set to “1”, each of first and second mixed frames MF 1 and MF 2 comprises average pixel data or average pixel color. Here, (X 0 +X 1 )/ 2 through (Y 4 +Y 5 )/ 2 each indicates average pixel data or average pixel color.

FIG. 10 is a flowchart illustrating a method for operating display controller 10 illustrated in FIG. 1 according to an embodiment of the inventive concept.

Referring to FIG. 10 , display controller 10 receives first left frame LF 1 and first right frame RF 1 (S 10 ).

Display controller 10 mixes first left frame LF 1 and first right frame RF 1 according to the 3D display format and outputs first mixed frame MF 1 and second mixed frame MF 2 (S 20 ). Display controller 10 blends first mixed frame MF 1 and second mixed frame MF 2 using alpha blender 35 and outputs first blended frame BF 1 (S 30 ).

As indicated by the foregoing, in various embodiments of the inventive concept, stereoscopic perception of 3D depth is provided to a viewer according to the format of pixel data displayed on a 3D display by using a merger. This can potentially eliminate a need for an extra chip.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.