Drive circuit

1. Field of the Invention

The present invention relates to a drive circuit for driving a switching element in, for example, a switching power source apparatus.

2. Description of Related Art

An example of a switching power source apparatus is described in Japanese Unexamined Patent Application Publication No. H04-105552 (Patent Document 1). This apparatus connects a primary winding of a transformer and a switching element, which is a MOSFET, in series to both ends of a DC power source. The apparatus turns on/off the switching element to generate an AC voltage on a secondary winding of the transformer. The AC voltage on the secondary winding is rectified and smoothed with a first rectifying-smoothing circuit into a DC output voltage, which is supplied to a load.

The DC output voltage is fed back through, for example, a photocoupler to a controller on the primary side of the transformer. Based on the fed-back voltage, the controller controls the switching frequency of the switching element in such a way as to bring the DC output voltage to a target value.

The transformer is provided with an auxiliary winding to generate an AC voltage, which is rectified and smoothed with a second rectifying-smoothing circuit into a DC voltage and is supplied as a control power source to the controller that is a part of the drive circuit. The controller is driven by the control power source and outputs a pulse signal according to which the drive circuit turns on/off the switching element.

According to the related art, the transformer must have the auxiliary winding, to increase the cost of the drive circuit.

The present invention provides a drive circuit that is low-cost and is capable of securing a power source for a controller without arranging an auxiliary winding for a transformer.

According to an aspect of the present invention, the drive circuit drives a normally-on high-side switch and a normally-off low-side switch being connected in a series manner and connected in parallel with a DC power source. The drive circuit includes a controller that outputs a control signal to turn on/off the high-side and low-side switches, a rectifier having a first end connected to a connection point of the high-side and low-side switches, a capacitor that is connected to a second end of the rectifier and a first end of the DC power source and serves as a power source for the controller, and a driver that turns on/off the high-side and low-side switches according to the control signal from the controller and a voltage from the capacitor.

FIG. 1 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 1 of the present invention;

FIG. 2 is a timing chart illustrating a startup operation of the apparatus of FIG. 1 ;

FIG. 3 is a timing chart illustrating a normal operation of the apparatus of FIG. 1 ;

FIG. 4 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 2 of the present invention;

FIG. 5 is a timing chart illustrating a startup operation of the apparatus of FIG. 4 ;

FIG. 6 is a timing chart illustrating a normal operation of the apparatus of FIG. 4 ;

FIG. 7 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 3 of the present invention;

FIG. 8 is a timing chart illustrating a startup operation of the apparatus of FIG. 7 ;

FIG. 9 is a timing chart illustrating a normal operation of the apparatus of FIG. 7 ;

FIG. 10 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 4 of the present invention;

FIG. 11 is a circuit diagram illustrating the details of the apparatus of FIG. 10 ;

FIG. 12 is an internal connection diagram illustrating a flip-flop FF 1 of the apparatus of FIG. 11 ;

FIG. 13 is a timing chart illustrating a startup operation of the apparatus of FIG. 11 ;

FIG. 14 is a timing chart illustrating a normal operation of the apparatus of FIG. 11 ;

FIG. 15 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 1 of Embodiment 4 of the present invention;

FIG. 16 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 1 of Embodiment 1 of the present invention;

FIG. 17 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 2 of Embodiment 4 of the present invention;

FIG. 18 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 2 of Embodiment 1 of the present invention;

FIG. 19 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 3 of Embodiment 1 of the present invention;

FIG. 20 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 4 of Embodiment 1 of the present invention; and

FIG. 21 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 5 of Embodiment 1 of the present invention.

Switching power source apparatuses having drive circuits according to embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 1 of the present invention. In FIG. 1 , both ends of a DC power source V 1 are connected to a series circuit including a primary winding P 1 of a transformer T 1 , a switching element Q 1 , and a switching element Q 2 . The switching element Q 1 is a normally-on switch and is made of, for example, GaN. The switching element Q 2 is a normally-off MOSFET.

The switching elements Q 1 and Q 2 are alternately or simultaneously turned on/off by a controller 10 . The transformer T 1 has a secondary winding S 1 whose first end is connected to an anode of a diode D 1 . A cathode of the diode D 1 is connected to a first end of a capacitor C 1 . A second end of the capacitor C 1 is connected to a second end of the secondary winding S 1 . The diode D 1 and capacitor C 1 form a rectifying-smoothing circuit that rectifies and smoothes an AC voltage generated by the secondary winding S 1 into a DC output voltage to be supplied to a load (not illustrated).

A voltage detector 12 detects a voltage across the capacitor C 1 , i.e., the DC output voltage and outputs the detected voltage as a feedback signal FB to the controller 10 . According to the feedback signal FB, the controller 10 controls ON/OFF duty ratios of the switching elements Q 1 and Q 2 , thereby controlling the DC output voltage to a predetermined value.

Between a drain and a source of the switching element Q 2 , a zener diode D 3 is connected. A connection point of the switching elements Q 1 and Q 2 is connected to an anode of a diode D 2 . A cathode of the diode D 2 is connected to a power source terminal of the controller 10 , a first end of a capacitor C 2 , a first end of a resistor R 1 , and a first end of a resistor R 4 .

Both ends of the capacitor C 2 are connected to a series circuit including resistors R 1 , R 2 , and R 3 and are also connected to a series circuit including the resistor R 4 and a zener diode D 4 . A connection point of the resistors R 1 and R 2 is connected to a non-inverting input terminal (+) of a comparator A 1 . A connection point of the resistor R 4 and zener diode D 4 is connected to an inverting input terminal (−) of the comparator A 1 .

The comparator A 1 is a hysteresis comparator having an upper threshold Hth and a lower threshold Lth. If a voltage VC 2 of the capacitor C 2 increases to the upper threshold Hth or over, the comparator A 1 outputs a high-level signal, and if the voltage VC 2 decreases to the lower threshold Lth or below, the comparator A 1 outputs a low-level signal.

The hysteresis comparator is realized with the resistors R 1 to R 3 , a NOT gate NOT 2 , a transistor Q 5 , and the zener diode D 4 . A resistance ratio of R 1 :R 2 is, for example, 1:1 and R 3 is 0.1×R 2 .

An output terminal of the comparator A 1 is connected to a first input terminal of an AND gate AND 1 and an input terminal of the NOT gate NOT 2 . A connection point of the resistors R 2 and R 3 is connected to a drain of the transistor Q 5 that is an n-type MOSFET. A gate of the transistor Q 5 is connected to an output terminal of the NOT gate NOT 2 . A source of the transistor Q 5 is connected to a second end of the capacitor C 2 , a first end of the resistor R 3 , an anode of the zener diode D 4 , a ground terminal of the controller 10 , and a source of a transistor Q 4 that is an n-type MOSFET.

An output terminal of the controller 10 is connected to a second input terminal of the AND gate AND 1 and an input terminal of a NOT gate NOT 1 . An output terminal of the NOT gate NOT 1 is connected to a gate of a transistor Q 3 that is a p-type MOSFET and a gate of the transistor Q 4 . Drains of the transistors Q 3 and Q 4 are connected to a gate of the switching element Q 1 . A source of the transistor Q 3 is connected to a source of the switching element Q 1 and a drain of the switching element Q 2 . An output terminal of the AND gate AND 1 is connected to a gate of the switching element Q 2 .

Operation of the drive circuit according to Embodiment 1 will be explained. First, a startup operation thereof will be explained with reference to FIG. 2 . In FIG. 2 , V 1 is a voltage of the DC power source V 1 , VC 2 is a voltage across the capacitor C 2 , VgsQ 1 is a gate-source voltage of the switching element Q 1 , VgsQ 2 is a gate-source voltage of the switching element Q 2 , and IdD 2 is a current passing through the diode D 2 .

At time t0, the switching element Q 1 turns on to clockwise pass a current through a path extending along a positive electrode of V 1 , P 1 , Q 1 , D 2 , C 2 , and a negative electrode of V 1 , thereby charging the capacitor C 2 . The voltage VC 2 of the capacitor C 2 starts to increase.

At time t1, the voltage VC 2 of the capacitor C 2 reaches an operation start voltage of the controller 10 and the controller 10 , comparator A 1 , and AND gate AND 1 start to operate. At this time, the voltage VC 2 is lower than a gate threshold voltage Q 1 th of the switching element Q 1 , and therefore, the switching element Q 1 is continuously ON.

At time t2, the voltage VC 2 of the capacitor C 2 reaches the gate threshold voltage Q 1 th of the switching element Q 1 . The controller 10 outputs a pulse signal to alternately turn on/off the transistors Q 3 and Q 4 , thereby starting an ON/OFF operation of the switching element Q 1 . During every ON period of the switching element Q 1 , the capacitor C 2 is charged to continuously increase the voltage VC 2 of the capacitor C 2 .

At this time, the voltage VC 2 of the capacitor C 2 is not an overvoltage, and therefore, the comparator A 1 provides the AND gate AND 1 with a low-level signal to keep the switching element Q 2 off.

At time t3, the voltage VC 2 of the capacitor C 2 becomes an overvoltage, and therefore, the comparator A 1 provides the AND gate AND 1 with a high-level signal. The AND gate AND 1 provides an AND logic of the pulse signal of the controller 10 and the high-level signal from the comparator A 1 . As a result, the switching element Q 2 starts an ON/OFF operation in synchronization with the ON/OFF operation of the switching element Q 1 . This results in limiting the current IdD 2 passing through the diode D 2 and shifting to a normal operation.

The normal operation of the switching power source apparatus will be explained with reference to FIG. 3 . In FIG. 3 , IdQ 1 is a drain current of the switching element Q 1 , VdQ 1 is a drain-source voltage of the switching element Q 1 , IdD 1 is a current passing through the diode D 1 , and A 1 is an output from the comparator A 1 .

At time t11, the controller 10 outputs a high-level signal, and therefore, the NOT gate NOT 1 outputs a low-level signal to the gate of the transistor Q 3 , to turn on the transistor Q 3 and switching element Q 1 . The DC power source V 1 provides the current IdQ 1 through the primary winding P 1 to the switching element Q 1 and the current IdD 2 to the diode D 2 to charge the capacitor C 2 .

The voltage VC 2 of the capacitor C 2 is not an overvoltage, and therefore, the comparator A 1 provides the AND gate AND 1 with a low-level signal, to keep the switching element Q 2 off.

At time t12, the voltage VC 2 of the capacitor C 2 exceeds the upper threshold Hth and the comparator A 1 provides the AND gate AND 1 with a high-level signal to turn on the switching element Q 2 . As a result, the current IdD 2 of the diode D 2 disappears and the voltage VC 2 of the capacitor C 2 stops increasing.

At time t13, the controller 10 outputs a low-level signal to turn on the transistor Q 4 and off the switching element Q 1 . As a result, the current IdQ 1 disappears. The low-level signal of the controller 10 is applied to the AND gate AND 1 , to turn off the switching element Q 2 .

At time t14, the voltage VC 2 of the capacitor C 2 decreases to the lower threshold Lth and the comparator A 1 provides the AND gate AND 1 with a low-level signal.

In this way, the switching power source apparatus employing the drive circuit according to Embodiment 1 charges the capacitor C 2 through the connection point of the normally-on switching element Q 1 and normally-off switching element Q 2 and the diode D 2 and applies the voltage VC 2 of the capacitor C 2 to the controller 10 . Without arranging an auxiliary winding for the transformer T 1 , Embodiment 1 secures the power source for the controller 10 , there by reducing the cost of the switching power source apparatus.

In addition, Embodiment 1 needs no startup circuit for supplying power to the controller 10 at startup of the DC power source V 1 .

FIG. 4 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 2 of the present invention. In FIG. 4 , a connection point of resistors R 1 and R 2 is connected to an inverting input terminal (−) of a comparator A 1 and a connection point of a resistor R 4 and a zener diode D 4 is connected to a non-inverting input terminal (+) of the comparator A 1 .

An output terminal of the comparator A 1 is connected to a set terminal S of a flip-flop FF 1 . A reset terminal R of the flip-flop FF 1 is connected to a gate of a transistor Q 3 and a gate of a transistor Q 4 . An output terminal Qb of the flip-flop FF 1 is connected to a first input terminal of an AND gate AND 1 .

The remaining configuration of Embodiment 2 is the same as Embodiment 1, and therefore, like parts are represented with like reference marks to omit overlapping explanations.

Unlike Embodiment 1 that charges the capacitor C 2 (serving as a power source for the controller 10 ) in every switching operation of the switching element Q 1 , Embodiment 2 detects when the voltage of a capacitor C 2 decreases below a threshold voltage VD 4 (breakdown voltage) of the zener diode D 4 , and only in the next ON period (one pulse) of a switching element Q 1 , charges the capacitor C 2 .

With the one-pulse charging, the voltage VC 2 of the capacitor C 2 increases higher than the threshold voltage VD 4 of the zener diode D 4 . Namely, Embodiment 2 conducts a plurality of switching operations of the switching element Q 1 without charging the capacitor C 2 unless the voltage VC 2 of the capacitor C 2 decreases below the threshold voltage VD 4 of the zener diode D 4 .

The number of switching operations of the switching element Q 1 carried out without charging the capacitor C 2 is determined according to the capacity of the capacitor C 2 . The larger the capacity of the capacitor C 2 , the larger the number of switching operations of the switching element Q 1 carried out without charging the capacitor C 2 increases. In FIG. 6 , for the sake of simplicity of explanation, the capacitor C 2 is charged whenever the switching element Q 1 carries out two switching operations.

The threshold voltage VD 4 of the zener diode D 4 and a threshold voltage Q 1 th of the switching element Q 1 are set to be higher than a minimum operating voltage of a controller 10 . A relationship of (operation start voltage of controller 10 )<(threshold voltage Q 1 th of switching element Q 1 )<(threshold voltage VD 4 of zener diode D 4 ) is satisfied as illustrated in FIGS. 5 and 6 .

Operation of the drive circuit according to Embodiment 2 will be explained with reference to a startup operation timing chart illustrated in FIG. 5 and a normal operation timing chart illustrated in FIG. 6 .

At time t0, the switching element Q 1 turns on to cause a current clockwise through a path extending along a positive electrode of V 1 , P 1 , Q 1 , D 2 , C 2 , and a negative electrode of V 1 . This charges the capacitor C 2 to increase the voltage VC 2 of the capacitor C 2 .

At time t1, the voltage VC 2 of the capacitor C 2 reaches the operation start voltage of the controller 10 , to start the controller 10 , comparator A 1 , and AND gate AND 1 . At this time, the voltage VC 2 is lower than the gate threshold voltage Q 1 th of the switching element Q 1 , and therefore, the switching element Q 1 is continuously ON.

At time t2, the voltage VC 2 of the capacitor C 2 reaches the gate threshold voltage Q 1 th of the switching element Q 1 , so that an ON/OFF output signal of the controller 10 starts ON/OFF operation of the switching element Q 1 .

At this time, the voltage VC 2 of the capacitor C 2 is lower than the threshold voltage VD 4 of the diode D 4 , and therefore, the comparator A 1 outputs a high-level signal to set the flip-flop FF 1 . The inverting output terminal Qb of the flip-flop FF 1 outputs a low-level signal. This low-level signal is supplied through the AND gate AND 1 to a gate of a switching element Q 2 . Accordingly, the gate signal of the switching element Q 2 is low without regard to the ON/OFF output signal of the controller 10 . As a result, the switching element Q 2 is OFF.

In a period from t2 to t3, the switching element Q 2 is OFF, and therefore, the switching element Q 1 charges the capacitor C 2 through the diode D 2 only when the switching element Q 1 is ON, thereby continuously increasing the voltage VC 2 of the capacitor C 2 .

At time t3, the voltage VC 2 of the capacitor C 2 exceeds the threshold voltage VD 4 of the diode D 4 and the output from the comparator A 1 changes from high to low.

After time t4, the set terminal S of the flip-flop FF 1 receives the low-level signal and the inverting output terminal Qb of the flip-flop FF 1 outputs a high-level signal in synchronization with an ON signal from the controller 10 . As a result, the switching element Q 2 carries out an ON/OFF operation in synchronization with the ON/OFF operation of the switching element Q 1 , to stop the charging of the capacitor C 2 through the diode D 2 during a period from t4 to t6.

At time t5, the voltage VC 2 of the capacitor C 2 decreases below the threshold voltage VD 4 of the diode D 4 and the output of the comparator A 1 changes from low to high. At time t6, the inverting output terminal Qb of the flip-flop FT becomes low. This turns off the switching element Q 2 and restarts the charging of the capacitor C 2 through the diode D 2 .

At time t7, the voltage VC 2 of the capacitor C 2 exceeds the threshold voltage VD 4 of the diode D 4 and the comparator A 1 again outputs a low-level signal. Accordingly, the charging of the capacitor C 2 terminates in a single pulse period from t6 to t8.

In this way, the switching power source apparatus having the drive circuit according to Embodiment 2 sets the flip-flop FF 1 through the comparator A 1 when the voltage VC 2 of the capacitor C 2 decreases, to keep the switching element Q 2 off in the next ON period of the switching element Q 1 . Namely, the switching element Q 1 turns on and the switching element Q 2 turns off at this time, so that a current passes through the diode D 2 to the capacitor C 2 , to increase the voltage VC 2 of the capacitor C 2 . This operation is intermittently carried out to maintain the capacitor C 2 at a predetermined voltage or over.

The switching power source apparatus having the drive circuit according to Embodiment 2 provides effects similar to those provided by the switching power source apparatus having the drive circuit according to Embodiment 1.

Unlike Embodiment 2 that charges the capacitor C 2 in a single switching operation (one pulse) among a plurality of switching operations of the switching element Q 1 , Embodiment 3 charges the capacitor C 2 in a first half of one pulse in which the current IdD 2 of the diode D 2 is small.

FIG. 7 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 3 of the present invention. Differences of the apparatus of Embodiment 3 illustrated in FIG. 7 from the apparatus of Embodiment 2 illustrated in FIG. 3 will be explained.

An output terminal of a comparator A 1 is connected to an anode of a diode D 5 . A cathode of the diode D 5 is connected to a first end of a resistor R 3 , a first end of a capacitor C 3 , and an inverting input terminal of an AND gate AND 2 . A second end of the resistor R 3 is connected to an anode of a diode D 6 . A cathode of the diode D 6 is connected to gates of transistors Q 3 and Q 4 and an output terminal of a NOT gate NOT 1 .

A second end of the capacitor C 3 is connected to a ground terminal of a controller 10 , an anode of a diode D 4 , a second end of the capacitor C 2 , a second end of a resistor R 2 , and a source of the transistor Q 4 . The AND gate AND 2 performs an AND logic of an inverted signal of a signal from the diode D 5 and an output of the controller 10 to a gate of a transistor Q 2 .

Instead of the flip-flop FF 1 of Embodiment 2, Embodiment 3 employs a time constant circuit including D 5 , D 6 , R 3 , and C 3 . Instead of the AND gate AND 1 of Embodiment 2, the present embodiment arranges the AND gate AND 2 . One of the input terminals of the AND gate AND 2 is a NOT input terminal.

The remaining configuration of Embodiment 3 is the same as Embodiment 2, and therefore, like parts are represented with like reference marks to omit overlapping explanations.

Operation of the drive circuit according to the present embodiment will be explained with reference to a startup operation timing chart of FIG. 8 and a normal operation timing chart of FIG. 9 .

Operation from time t10 to t13 of FIG. 8 is the same as the operation from time t0 to t3 of Embodiment 2, and therefore, will not be explained.

At time t13, the voltage VC 2 of the capacitor C 2 exceeds the threshold voltage VD 4 of the diode D 4 and an output from the comparator A 1 changes from high to low. As a result, the capacitor C 3 discharges through the resistor R 3 and diode D 6 to the NOT gate NOT 1 .

When a time constant time A elapses after time t13, an output from the AND gate AND 2 changes from low to high. Here, the time constant time A is determined by a time constant of the resistor R 3 and capacitor C 3 and a NOT input threshold voltage of the AND gate AND 2 .

At time t14, the switching element Q 2 changes from OFF to ON. When the switching element Q 2 turns on, a drain current of the switching element Q 1 , which has charged the capacitor C 2 through the diode D 2 , passes through the switching element Q 2 to the ground.

After time t14, the controller 10 stops the ON signal. Even with the next ON signal, the voltage VC 2 of the capacitor C 2 is above the threshold voltage VD 4 of the diode D 4 , and therefore, the output from the comparator A 1 is low. As a result, the capacitor C 3 is not charged and the AND gate AND 2 outputs a signal, which is synchronous to the ON/OFF signal of the controller 10 , to the gate of the switching element Q 2 . Accordingly, the switching element Q 2 carries out an ON/OFF operation in synchronization with the ON/OFF operation of the switching element Q 1 . In a period from t14 to t15, the charging of the capacitor C 2 through the diode D 2 stops.

At time t15, the voltage VC 2 of the capacitor C 2 decreases below the threshold voltage VD 4 of the diode D 4 and the output from the comparator A 1 becomes high to charge the capacitor C 3 . In synchronization with the next ON signal of the controller 10 , the capacitor C 2 is charged.

The capacitor C 2 is charged at once, and at time t16, the voltage VC 2 of the capacitor C 2 again exceeds the threshold voltage VD 4 of the diode D 4 . At time t18 after the time constant time A elapses from time t16, the charging of the capacitor C 2 stops. Since the capacitor C 2 starts to be charged in synchronization with the ON signal from the controller 10 , the charging of the capacitor C 2 starts from a drain current IdQ 1 of the switching element Q 1 being 0 A.

According to the present embodiment, the voltage VC 2 of the capacitor C 2 is suppressed by properly setting the time constant time A. Namely, the charge voltage of the capacitor C 2 is adjustable not to become an overvoltage.

The switching power source apparatus having the drive circuit according to the present embodiment outputs a high-level signal from the comparator A 1 to charge the capacitor C 3 if the voltage VC 2 of the capacitor C 2 decreases. In the next ON period of the switching element Q 1 , the comparator A 1 outputs a low-level signal, to discharge the capacitor C 3 through the resistor R 3 .

Until the voltage VC 3 of the capacitor C 3 decreases to a predetermined value or below, the switching element Q 1 is ON and the switching element Q 2 OFF, to pass a current through the diode D 2 to the capacitor C 2 , thereby increasing the voltage VC 2 of the capacitor C 2 . This operation is carried out every cycle or intermittently, to maintain the voltage VC 2 of the capacitor C 2 at a predetermined value or over.

The switching power source apparatus according to Embodiment 3 provides effects similar to those provided by the switching power source apparatus according to Embodiment 1.

FIG. 10 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Embodiment 4 of the present invention. In FIG. 10 , a cathode of a diode D 2 is connected to a first end of a switch SW. A second end of the switch SW is connected to a first end of a capacitor C 2 , a first end of a UVLO (undervoltage lockout) circuit 15 , and a first end of a controller 10 . A gate of a switching element Q 1 is connected to a negative electrode of a DC power source V 1 , i.e., the ground. The gate of the switching element Q 1 may be connected to a predetermined potential.

The controller 10 outputs a pulse signal to turn on/off a low-side switching element Q 2 . According to the pulse signal of the controller 10 and a voltage of the capacitor C 2 , the switch SW turns on/off.

The UVLO circuit 15 is a low-voltage detector that includes, for example, resistors R 1 , R 2 , R 3 , and R 4 , a transistor Q 5 , a comparator A 1 , a NOT gate NOT 2 , and a zener diode D 4 as illustrated in FIG. 11 . These elements of the UVLO circuit 15 correspond to the same elements illustrated in FIG. 1 . An output from the comparator A 1 of the UVLO circuit 15 is connected to a reset terminal R of a flip-flop FF 1 . An inverting output terminal Qb of the flip-flop FF 1 is connected to a control terminal of the switch SW. An output terminal of the controller 10 is connected to a set terminal S of the flip-flop FF 1 and a gate of the switching element Q 2 .

The remaining configuration of Embodiment 4 is the same as Embodiment 1 illustrated in FIG. 1 , and therefore, like parts are represented with like reference marks.

Operation of the drive circuit according to the present embodiment will be explained. In a normal state (with a low-level signal), the switch SW is ON. When the inverting output terminal Qb of the flip-flop FF 1 provides a high-level signal, the switch SW turns off.

At first, the gate of the switching element Q 1 is connected to the ground. When a DC power source V 1 is activated, a current passes to the switching element Q 1 to charge the capacitor C 2 through the diode D 2 and switch SW.

If the charge voltage of the capacitor C 2 exceeds a reference voltage of the UVLO circuit 15 , the UVLO circuit 15 outputs a high-level signal to the reset terminal R of the flip-flop FF 1 . As a result, the inverting output terminal Qb of the flip-flop FF 1 outputs a high-level signal to the switch SW to turn off the switch SW.

Before the charge voltage of the capacitor C 2 exceeds the reference voltage of the UVLO circuit 15 , the controller 10 starts to output an ON/OFF pulse signal to the gate of the switching element Q 2 .

At this time, the switching element Q 1 is continuously ON until a gate voltage to the switching element Q 1 exceeds a threshold voltage of the switching element Q 1 . When the gate voltage to the switching element Q 1 exceeds the threshold voltage of the switching element Q 1 , the switching element Q 1 starts an ON/OFF operation in synchronization with the ON/OFF operation of the switching element Q 2 .

If the charge voltage of the capacitor C 2 decreases below the reference voltage of the UVLO circuit 15 during the period in which the controller 10 outputs the ON/OFF pulse signal, the UVLO circuit 15 outputs a low-level signal to the reset terminal R of the flip-flop FF 1 . As a result, the inverting output terminal Qb of the flip-flop FF 1 outputs a low-level signal to the control terminal of the switch SW to turn on the switch SW.

When the controller 10 changes the ON pulse signal to an OFF pulse signal, the switching element Q 2 turns off and the drain voltage of the switching element Q 2 increases. When this drain voltage exceeds the charge voltage of the capacitor C 2 , a current of the switching element Q 1 charges the capacitor C 2 .

When the charge voltage of the capacitor C 2 exceeds the reference voltage of the UVLO circuit, the switch SW turns off. As a result, the current of the switching element Q 1 passes through a drain-source capacitance (not illustrated) of the switching element Q 2 and the source voltage of the switching element Q 1 increases. Then, the gate voltage of the switching element Q 1 quickly exceeds its threshold voltage to turn off the switching element Q 1 .

In this way, the drive circuit according to Embodiment 4 provides effects similar to those provided by the drive circuit of Embodiment 1.

FIG. 11 is a circuit diagram illustrating the details of the switching power source apparatus having the drive circuit according to Embodiment 4 of the present invention.

In FIG. 11 , the resistors R 1 , R 2 , R 3 , and R 4 , transistor Q 5 , comparator A 1 , NOT gate NOT 2 , and zener diode D 4 form the UVLO circuit 15 illustrated in FIG. 10 .

A transistor Q 6 that is a p-channel MOSFET corresponds to the switch SW illustrated in FIG. 10 . Between a gate of the transistor Q 6 and the cathode of the diode D 2 , a resistor R 5 is connected. The gate of the transistor Q 6 is connected to an anode of a diode D 5 . A cathode of the diode D 5 is connected to the inverting output terminal Qb of the flip-flop FF 1 .

FIG. 12 is an internal connection diagram of the flip-flop FF 1 in the switching power source apparatus of FIG. 11 . The flip-flop FF 1 of FIG. 12 is a set preference circuit.

In FIG. 12 , a power source Vcc is connected to a first end of a resistor R 6 and a first end of a resistor R 8 . A second end of the resistor R 6 is connected to the set terminal S of the flip-flop FF 1 and a first input terminal of a NOR gate NOR 2 . The ground is connected to a first end of a resistor R 7 and a first end of a resistor R 9 . A second end of the resistor R 7 is connected to the reset terminal R of the flip-flop FF 1 and a first input terminal of a NOR gate NOR 1 .

A second end of the resistor R 8 is connected to an output terminal Q of the flip-flop FF 1 , an output terminal of the NOR gate NOR 1 , and a second input terminal of the NOR gate NOR 2 . A second end of the resistor R 9 is connected to the inverting output terminal Qb of the flip-flop FF 1 , an output terminal of the NOR gate NOR 2 , and a second input terminal of the NOR gate NOR 1 .

Operation of the drive circuit according to the present embodiment illustrated in FIG. 11 will be explained. When the DC power source V 1 is activated, a divided voltage by the gate resistor R 5 and the resistor R 9 , which is present between the inverting output terminal Qb of the flip-flop FF 1 and the ground, is applied to the gate of the transistor Q 6 , to turn on the transistor Q 6 .

At the startup of the power source, the switching element Q 1 is ON, and therefore, a charge current passes through a primary winding P 1 , the switching element Q 1 , and the diode D 2 to the transistor Q 6 .

After the transistor Q 6 turns on, the current passes through the capacitor C 2 and the voltage VC 2 of the capacitor C 2 increases to operate the controller 10 . An operation start voltage of the controller 10 is so set that the switching element Q 2 carries out an ON/OFF operation.

When the voltage VC 2 of the capacitor C 2 exceeds the reference voltage of the UVLO circuit 15 , the UVLO circuit 15 provides the reset terminal R of the flip-flop FF 1 with a reset signal, so that the inverting output terminal Qb of the flip-flop FF 1 outputs a high-level signal. This turns off the transistor Q 6 to protect the transistor Q 6 from the overvoltage of the capacitor C 2 .

In a normal operation, the flip-flop FF 1 detects the voltage VC 2 of the capacitor C 2 when the switching element Q 2 turns off, and if the detected voltage is low, turns on the transistor Q 6 .

A drain current IdQ 1 of the switching element Q 1 passes through the diode D 2 to the capacitor C 2 , thereby charging the capacitor C 2 . The flip-flop FF 1 turns on/off the transistor Q 6 , to prevent the charging current from the switching element Q 1 from always passing through the capacitor C 2 .

In this way, Embodiment 4 secures source power for the controller 10 without providing the transformer T 1 with an auxiliary winding. In addition, the present embodiment needs no startup circuit for supplying source power to the controller 10 at startup.

FIG. 13 is a timing chart illustrating the startup operation of the switching power source apparatus having the drive circuit according to Embodiment 4. FIG. 14 a timing chart illustrating the normal operation of the switching power source apparatus having the drive circuit according to Embodiment 4.

Drive circuits according to modifications of the above-mentioned embodiments will be explained.

(Modification 1 of Embodiment 4)

FIG. 15 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 1 of Embodiment 4 of the present invention. Compared with the drive circuit of Embodiment 4 illustrated in FIG. 11 , the drive circuit of Modification 1 of Embodiment 4 illustrated in FIG. 15 is characterized in that it arranges a regulator 17 serving as a constant voltage source between both ends of the controller 10 . The regulator 17 supplies a gate voltage to the switching element Q 1 .

In an optimum condition, the controller 10 receives a source voltage of |Vth(Q 1 )|−VF(D 2 ). The regulator 17 increases the source voltage for the controller 10 by the voltage of the regulator 17 . This is effective when the threshold voltage of the switching element Q 1 is insufficient to operate the controller 10 .

It is possible to replace the diode D 2 , transistor Q 6 , and resistor R 5 with a regulator block. It is also possible to replace the comparator A 1 with the UVLO circuit 15 .

(Modification 1 of Embodiment 1)

FIG. 16 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 1 of Embodiment 1 of the present invention. The drive circuit of FIG. 16 is characterized in that it employs a regulator 18 instead of the diode D 2 of Embodiment 1.

The regulator 18 is a constant voltage source that supplies a voltage from a connection point of the switching elements Q 1 and Q 2 to the capacitor C 2 , which supplies source power to the controller 10 .

Employing the regulator 18 as a constant voltage source is effective to suppress an overvoltage to be applied to the controller 10 .

(Modification 2 of Embodiment 4)

FIG. 17 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 2 of Embodiment 4 of the present invention. Compared with the drive circuit of Embodiment 4 illustrated in FIG. 11 , the drive circuit of Modification 2 of Embodiment 4 illustrated in FIG. 17 employs a normally-on switching element Q 1 A and normally-on switching element Q 1 B to serve as a power source for the controller 10 . A source of the switching element Q 1 A is connected to the anode of the diode D 2 and a source of the switching element Q 1 B is connected to the drain of the switching element Q 2 . Gates of the switching elements Q 1 A and Q 2 B are connected to the ground.

A block A encircled with a dotted line in FIG. 17 can be integrated into a one-chip configuration, to reduce the size of the drive circuit. For example, if the switching element Q 1 is made of a GaN-FET chip, the elements in the block A can be formed in the GaN-FET chip, to provide an integrated circuit.

Operation of the drive circuit according to Modification 2 of Embodiment 4 will be explained. A drain-source capacitance CQ 2 of the switching element Q 2 is very small compared to the capacitance of the capacitor C 2 .

A current of the switching element Q 1 B at the time of switching off instantaneously charges the drain-source capacitance CQ 2 , to increase a source voltage of the switching element Q 1 B. Since the gate of the switching element Q 1 B is connected to the ground, a turn-off switching speed of the switching element Q 1 B becomes quicker.

With respect to the switching-off of the switching element Q 1 B, there is a delay until the switching element Q 1 A reaches a threshold voltage because the source of the switching element Q 1 A is connected through the diode D 2 and transistor Q 6 to the capacitor C 2 .

As a result, a current at the time of switching off passes through the switching element Q 1 A and the capacitor C 2 , so that a switching loss of the switching element Q 1 B is partly born by the switching element Q 1 A. Namely, the switching loss is thermally distributed.

Surge energy by a leakage inductance of the transformer T 1 is used as a charging current for the capacitor C 2 , to reduce a surge voltage to be applied to the drains of the switching elements Q 1 A and Q 1 B.

(Modification 2 of Embodiment 1)

FIG. 18 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 2 of Embodiment 1 of the present invention. Compared with the drive circuit of Embodiment 1 illustrated in FIG. 1 , the drive circuit of Modification 2 of Embodiment 1 illustrated in FIG. 18 is characterized in that it employs a switching element Q 1 A that is an n-channel MOSFET and a switching element Q 1 B that is an n-channel MOSFET, to serve as a power source for the controller 10 .

Drains of the switching elements Q 1 A and Q 1 B are connected to each other and gates thereof are also connected to each other. A source of the switching element Q 1 A is connected to the anode of the diode D 2 . The cathode of the diode D 2 is connected to the first end of the capacitor C 2 . A source of the switching element Q 1 B is connected to a drain of a switching element Q 2 B.

The controller 10 supplies a pulse signal to turn on/off the two high-side switching elements Q 1 A and Q 1 B and the low-side switching element Q 2 B.

The drive circuit according to Modification 2 of Embodiment 1 provides effects similar to those provided by the drive circuit of Embodiment 1 and the drive circuit of Modification 2 of Embodiment 4.

(Modification 3 of Embodiment 1)

FIG. 19 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 3 of Embodiment 1 of the present invention. Compared with the drive circuit of Embodiment 1 illustrated in FIG. 1 , the drive circuit of Modification 3 of Embodiment 1 illustrated in FIG. 19 is characterized in that it connects a series circuit including a switching element Q 1 A (a second normally-on high-side switch) and a switching element Q 2 A (a second normally-off low-side switch) in parallel with the series circuit of the switching elements Q 1 and Q 2 .

Gates of the high-side switching elements Q 1 and Q 1 A are connected to each other and gates of the low-side switching elements Q 2 and Q 2 A are connected to each other.

Adding the switching elements Q 1 A and Q 2 A increases a current in addition to the current passing through the switching elements Q 1 and Q 2 .

In addition, Modification 3 of Embodiment 1 distributes a loss of the switching element Q 1 , thereby distributing generated heat and improving reliability.

(Modification 4 of Embodiment 1)

FIG. 20 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 4 of Embodiment 1 of the present invention. Compared with the drive circuit according to Embodiment 1 illustrated in FIG. 1 , the drive circuit of Modification 4 of Embodiment 1 illustrated in FIG. 20 is characterized in that it additionally employs a normally-off switching element Q 7 in parallel with the series circuit of the switching elements Q 1 and Q 2 .

A gate of the normally-off switching element Q 7 is connected to the gate of the switching element Q 2 .

This configuration reduces a loss due to an ON resistance of the switching elements Q 1 and Q 2 .

The switching elements Q 1 , Q 2 , and Q 7 may be formed in a single chip. Alternatively, the switching element Q 7 may be connected as an external FET, to increase a current passing through the transformer T 1 , thereby realizing a large output capacity.

For example, the switching elements Q 1 to Q 4 , controller 10 , and UVLO circuit may be integrated into a one-package integrated circuit. In this case, power to be controlled by the switching elements Q 1 and Q 2 may freely be increased by connecting the switching element Q 7 thereto. Also, heat generated by the switching elements Q 1 , Q 2 , and Q 7 may be distributed to improve reliability.

(Modification 5 of Embodiment 1)

FIG. 21 is a circuit diagram illustrating a switching power source apparatus having a drive circuit according to Modification 5 of Embodiment 1 of the present invention. Compared with the drive circuit of Embodiment 1 illustrated in FIG. 1 , the drive circuit of Modification 5 of Embodiment 1 illustrated in FIG. 21 is characterized in that it employs a high-side circuit configuration also for a low-side part. A source of a high-side switching element Q 2 H is connected in series with a drain of a low-side switching element Q 2 L. A source of the switching element Q 2 L is connected to the negative electrode of the DC power source V 1 . In this way, the present invention is applicable to such a drive circuit of bridge configuration.

The present invention is not limited to the drive circuits mentioned above. For example, the present invention is applicable to a drive circuit employing an n-channel MOSFET instead of the diode D 2 .

As mentioned above, the drive circuit according to the present invention employs a normally-on element as a high-side switch and charges a capacitor from a DC power source through the high-side switch, so that the voltage of the capacitor is supplied to a controller. This configuration of the present invention secures source power for the controller without arranging an auxiliary winding for a transformer, and therefore, is low-cost.

The present invention is applicable to AC-DC converters, DC-DC converters, and the like.

This application claims benefit of priority under 35 USC §119 to Japanese Patent Applications No. 2011-203414, filed on Sep. 16, 2011 and No. 2012-167941, filed on Jul. 30, 2012, the entire contents of which are incorporated by reference herein.