Nonvolatile semiconductor memory device

This application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2011-286515, filed Dec. 27, 2011; and No. 2011-287855, filed Dec. 28, 2011, the entire contents of all of which are incorporated herein by reference.

Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

For example, a floating gate NAND flash memory which is a nonvolatile semiconductor memory device has a memory cell of a stack gate structure in which a gate insulating film (tunnel insulating film), a floating gate electrode, a gate insulating film (intergate insulating film), and a control gate electrode are stacked. In this memory cell structure, the upper part of the floating gate electrode becomes thinner along with the advance of generations, and the concentration of an electric field in this upper part is increased, so that a leakage current in the intergate insulating film is increased during writing.

Therefore, when the above-mentioned memory cell is miniaturized with no change of the conventional structure, electrons injected into the floating gate electrode escape toward the control gate electrode because of the increased leakage current even though a high write voltage is applied to increase a tunnel current passing through the tunnel insulating film and thereby increase the amount of electrons injected into the floating gate electrode. Consequently, a multivalued memory cell may reach write saturation that prevents writing up to a threshold necessary for multivalue writing.

FIG. 1 is a plan view showing the configuration of a nonvolatile semiconductor memory device according to a first embodiment;

FIG. 2 is a sectional view taken along line 2 - 2 in FIG. 1 ;

FIG. 3 is a sectional view taken along line 3 - 3 in FIG. 1 ;

FIGS. 4 to 9 are sectional views showing a method of manufacturing a memory cell array in the nonvolatile semiconductor memory device according to the first embodiment;

FIGS. 10 to 14 are sectional views showing the configuration of a nonvolatile semiconductor memory device according to a second embodiment;

FIGS. 15 and 16 are sectional views showing the configuration of a nonvolatile semiconductor memory device according to a third embodiment;

FIG. 17A is a graph of an energy band in an intergate insulating (NONON) film between a floating gate electrode and a control gate electrode;

FIG. 17B is a graph of an energy band in an intergate insulating (NONO) film between the floating gate electrode and the control gate electrode according to the third embodiment;

FIGS. 18 to 22 are sectional views showing a method of manufacturing a memory cell array in the nonvolatile semiconductor memory device according to the third embodiment;

FIG. 23 is a sectional view showing the configuration of a nonvolatile semiconductor memory device according to a fourth embodiment; and

FIGS. 24 to 26 are sectional views showing a method of manufacturing a memory cell array in the nonvolatile semiconductor memory device according to the fourth embodiment.

Hereinafter, a nonvolatile semiconductor memory device according to embodiments is described with reference to the drawings. Here, a NAND flash memory is shown as an example of the nonvolatile semiconductor memory device. In the following explanation, components having the same functions and configurations are provided with the same reference signs and are repeatedly described only when necessary.

In general, according to one embodiment, a nonvolatile semiconductor memory device includes a gate insulating film, a floating gate electrode, a first silicon oxide film, an insulating film, a second silicon oxide film and a control gate electrode. The gate insulating film is formed on a semiconductor substrate. The floating gate electrode is formed on the gate insulating film. The first silicon oxide film is formed on an upper surface of the floating gate electrode. The insulating film is formed on the first silicon oxide film on the upper surface of the floating gate electrode. The insulating film has a dielectric constant higher than that of the silicon oxide film. The second silicon oxide film is formed on the insulating film on the upper surface of the floating gate electrode and on a side surface of the floating gate electrode. The control gate electrode is formed on the second silicon oxide film formed on the upper surface and side surface of the floating gate electrode.

First Embodiment

[1] Configuration of Memory Cell Array

FIG. 1 is a plan view showing the configuration of a memory cell array in a NAND flash memory according to the first embodiment. FIG. 2 is a sectional view taken along line 2 - 2 in FIG. 1 . FIG. 3 is a sectional view taken along line 3 - 3 in FIG. 1 . FIG. 2 shows a section along the channel length direction (bit-line direction) of a memory cell MC. FIG. 3 shows a section along the channel width direction (word-line direction) of the memory cell MC.

As shown in FIG. 1 , an element isolation region, and element regions (active areas) AA isolated by the element isolation region are formed in the surface region of a semiconductor substrate 10 . The element regions AA are arranged in the word-line direction, and each of the element regions AA extends in the bit-line direction. A plurality of memory cells MC and select transistors STD and STS are formed on the element region AA.

The memory cells MC arranged on the element region AA are connected in series. The memory cells MC connected in series will hereinafter be referred to as a memory string. Select transistors STD and STS are located at both ends of this memory string. Further, a configuration including the memory string and select transistors STD and STS will hereinafter be referred to as a NAND cell unit.

Word lines WL (WL 1 to WLn) and select gate lines SGL 1 and SGL 2 are arranged in the bit-line direction, and each of these lines extends in the word-line direction. That is, the word lines WL (WL 1 to WLn) and select gate lines SGL 1 and SGL 2 are disposed to intersect at right angles with the element regions AA.

A plurality of NAND cell units are arranged in the word-line direction. The memory cells MC of the NAND cell units are respectively connected to the word lines WL (WL 1 to WLn). Here, the memory cells MC located in the word-line direction are connected to the common word line WL. Further, select transistors STD and STS are respectively connected to select gate lines SGL 1 and SGL 2 .

One end of the NAND cell unit is connected, via a bit-line contact BC, to a bit line (not shown) extending in the same direction as the element region AA. The other end of the NAND cell unit is connected, via a source-line contact SC, to a source line (not shown) extending in the word-line direction.

Now, the sectional structure of the memory cell array according to the first embodiment is described.

As shown in FIG. 2 and FIG. 3 , the memory cell MC is a memory cell transistor having a stack gate structure in which a control gate electrode 14 A is stacked on a floating gate electrode 12 A.

A well region (not shown) is provided in the semiconductor substrate 10 , and the NAND cell unit is formed on the well region. An element isolation region 15 , and the element regions AA isolated by the element isolation region 15 are arranged in the surface region of the semiconductor substrate 10 .

Disposed on the semiconductor substrate (element region AA) 10 are the memory cell MC including a gate insulating film 11 A, the floating gate electrode 12 A, an intergate insulating film 13 T, and the control gate electrode 14 A, and select transistors STD and STS including a gate insulating film 11 B, a bottom gate electrode 12 B, an intergate insulating film 13 T, and a top gate electrode 14 B.

The gate insulating film 11 A is formed on the element region AA. This gate insulating film 11 A functions as a tunnel insulating film between the element region AA and the floating gate electrode 12 A. The gate insulating film 11 A of the memory cell MC will hereinafter be referred to as a tunnel insulating film.

The floating gate electrode 12 A is formed on the tunnel insulating film 11 A. The floating gate electrode 12 A functions as a charge storage layer to hold data written to the memory cell MC. This floating gate electrode 12 A is made of, for example, a polysilicon film.

The floating gate electrodes 12 A of the memory cells MC arranged on the element regions AA adjacent in the channel width direction (word-line direction) are electrically insulated by the element isolation region 15 embedded in the semiconductor substrate 10 . Here, the upper surface of the element isolation region 15 is set back toward the semiconductor substrate 10 in comparison with the upper surface of the floating gate electrode 12 A. That is, the upper surface of the element isolation region 15 is located higher than the lower surface of the floating gate electrode 12 A and lower than the upper surface of the floating gate electrode 12 A.

Intergate insulating film 13 T is formed on the upper surface of the floating gate electrode 12 A, and an intergate insulating film 13 S is formed on the side surface of the floating gate electrode 12 A and on the element isolation region 15 .

Intergate insulating film 13 T formed on the upper surface of the floating gate electrode 12 A has a stack film (what is known as a NONON film) in which a bottom silicon nitride film 13 A, a bottom silicon oxide film 13 B, an insulating film (for example, center silicon nitride film) 13 C, a top silicon oxide film 13 D, and a top silicon nitride film 13 E are stacked in this order from the side of the floating gate electrode 12 A. The symbol “N” denotes a silicon nitride film, and the symbol “O” denotes a silicon oxide film.

Intergate insulating film 13 S formed on the side surface of the floating gate electrode 12 A and on the element isolation region 15 has a stack film (what is known as a NON film) in which a bottom silicon nitride film 13 A, a top silicon oxide film 13 D, and a top silicon nitride film 13 E are stacked in this order from the side of the floating gate electrode 12 A and the element isolation region 15 .

Intergate insulating film 13 T on the upper surface of the floating gate electrode 12 A has the insulating film (for example, center silicon nitride film) 13 C, and intergate insulating film 13 S on the side surface of the floating gate electrode 12 A does not have the insulating film 13 C.

The materials used for intergate insulating films 13 T and 13 S are not limited to the above-mentioned materials, and other materials may be used instead. A silicon oxynitride (SiON) film or a metal oxide film may be used for the insulating film 13 C instead of an insulating (high-k) film such as the above-mentioned silicon nitride (SiN) film having a dielectric constant higher than that of the silicon oxide film. The metal oxide film includes, for example, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminate (LaAlO 3 ), hafnium aluminate (HfAlOx), tantalum oxide (Ta 2 O 5 ), and titanium oxide (TiO 2 ). These materials are not limited to the composition ratios in parentheses.

Intergate insulating film 13 T on the upper surface of the floating gate electrode 12 A has a five-layer structure (NONON film), and intergate insulating film 13 S on the side surface of the floating gate electrode 12 A and on the element isolation region 15 has a three-layer structure (NON film). However, these intergate insulating films are not limited to such multilayer structures, may have other multilayer structures.

The control gate electrode 14 A is formed on intergate insulating films 13 T and 13 S. That is, the control gate electrode 14 A is disposed on the upper surface of the floating gate electrode 12 A via intergate insulating film 13 T. The control gate electrode 14 A is disposed on the side surface of the floating gate electrode 12 A via intergate insulating film 13 S. The control gate electrode 14 A is equivalent to the word line WL.

For example, a silicide film is used for the control gate electrode 14 A to reduce electric resistance. However, the control gate electrode 14 A is not limited to the silicide film, and may have a single-layer structure of a polysilicon film or a double-layer structure (polycide structure) in which a polysilicon film and a silicide film are stacked. As the silicide film, for example, a tungsten silicide film, a molybdenum silicide film, a cobalt silicide film, a titanium silicide film, or a nickel silicide film is used.

The control gate electrode 14 A functions as a word line, and is shared between the adjacent memory cells MC. Therefore, the control gate electrode 14 A is formed not only on the floating gate electrode 12 A but also on the element isolation region 15 .

As shown in FIG. 2 , source/drain diffusion layers 16 A of the memory cell MC are formed in the semiconductor substrate 10 . The source/drain diffusion layers 16 A are formed in the element regions AA on both sides of the memory cell MC, and shared between the adjacent memory cells MC. Accordingly, the memory cells MC are connected in series, and one memory cell string is formed.

Select transistors STD and STS are formed at one end and the other of the memory cells MC connected in series, that is, the memory cell string.

Select transistors STD and STS are formed in a process similar to that of the memory cells MC. Therefore, in the gate structure of each of select transistors STD and STS, the top gate electrode 14 B is stacked on the bottom gate electrode 12 B via intergate insulating film 13 T. The bottom gate electrode 12 B has the same structure as the floating gate electrode 12 A, and the top gate electrode 14 B has the same structure as the control gate electrode 14 A.

However, in select transistors STD and STS, intergate insulating film 13 T has an opening. The bottom gate electrode 12 B and the top gate electrode 14 B are electrically connected to each other via the opening.

A diffusion layer 16 B is formed on the memory cell side of select transistor STD, and a diffusion layer 16 D is formed on the opposite side. The diffusion layer 16 B is formed on the memory cell side of select transistor STS, and a diffusion layer 16 S is formed on the opposite side.

The diffusion layers 16 B, 16 D, and 16 S function as source/drain regions of select transistors STD and STS. Select transistors STD and STS share the diffusion layer 16 B with the adjacent memory cells MC. As a result, the memory cells MC and select transistors STD and STS are connected in series in the element region AA, and the NAND cell unit is formed.

Select transistor STD is located on the drain side of the NAND cell unit. The diffusion layer 16 D of select transistor STD is connected to the bit-line contact BC formed in an interlayer insulating film 17 . The bit-line contact BC is connected to a bit line BL via a metal interconnect M 0 and a via contact VC disposed in an interlayer insulating film 18 .

Select transistor STS is located on the source side of the NAND cell unit. The diffusion layer 16 S of select transistor STS is connected to a source line SL via the source-line contact SC formed in the interlayer insulating film 17 .

According to the first embodiment, intergate insulating film 13 T is formed on the upper surface of the floating gate electrode 12 A. In this intergate insulating film 13 T, the bottom silicon nitride film 13 A, the bottom silicon oxide film 13 B, the insulating film (for example, center silicon nitride film) 13 C, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order. Intergate insulating film 13 S is formed on the on the side surface of the floating gate electrode 12 A. In intergate insulating film 13 S, the bottom silicon nitride film 13 A, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order. That is, intergate insulating film 13 S on the side surface of the floating gate electrode 12 A does not have the insulating film 13 C, and intergate insulating film 13 T on the upper surface of the floating gate electrode 12 A has the insulating film 13 C.

As the insulating film 13 C is not present on the side surface of the floating gate electrode 12 A, it is possible to inhibit the spread of a threshold distribution caused when electrons are trapped by the insulating film 13 C on the side surface of the floating gate electrode 12 A because of repeated writing and erasing. Moreover, as a result of the elimination of the insulating film 13 C on the side surface of the floating gate electrode 12 A, the insulating film 13 C on the upper surface of the floating gate electrode 12 A can be increased in thickness without the side effects of the above-mentioned spread of the threshold distribution, in comparison with the case where the NONON film is formed on the upper surface and side surface of the floating gate electrode. Consequently, a leakage current in the intergate insulating film can be reduced, and write saturation that prevents writing up to a necessary threshold can be improved.

Furthermore, according to the first embodiment, the leakage current in the intergate insulating film can be reduced without the increase in the thickness of the insulating film on the side surface of the floating gate electrode 12 A. Thus, the thickness of the intergate insulating film on the side surface of the floating gate electrode 12 A can be reduced. As the thickness of the intergate insulating film on the side surface of the floating gate electrode 12 A can be reduced, the following advantages are provided.

Firstly, as the thickness of the intergate insulating film on the side surface of the floating gate electrode can be reduced, a coupling ratio between the floating gate electrode 12 A and the control gate electrode 14 A can be increased. Secondly, the distance between the floating gate electrodes 12 A to embed the control gate electrode 14 A can be increased, and the control gate electrode 14 A can therefore be easily embedded between the floating gate electrodes 12 A. Thirdly, as the distance between the floating gate electrodes 12 A to embed the control gate electrode 14 A can be increased, the volume of the control gate electrode 14 A can be increased, and the depletion of the control gate electrode 14 A can be inhibited. Fourthly, as the thickness of the intergate insulating film can be reduced, the floating gate electrode 12 A can be reduced in thickness while the coupling ratio between the floating gate electrode 12 A and the control gate electrode 14 A is maintained.

As described above, according to the present embodiment, as the intergate insulating film disposed between the floating gate electrode and the control gate electrode, the insulating film 13 C is formed on the upper surface of the floating gate electrode 12 A without the insulating film 13 C disposed on the side surface of the floating gate electrode 12 A. Consequently, the spread of the threshold distribution of the memory cell resulting from repeated writing and erasing can be inhibited, and the leakage current in the intergate insulating film can be reduced.

[2] Method of Manufacturing Memory Cell Array

Now, a method of manufacturing the NAND flash memory according to the first embodiment is described. FIG. 4 to FIG. 9 are sectional views showing the method of manufacturing the memory cell array in the NAND flash memory according to the first embodiment.

First, as shown in FIG. 4 , a film 11 to be a gate insulating film is formed on a semiconductor substrate 10 , and a film 12 to be a floating gate electrode is formed on the film 11 . For example, the film 11 is made of a silicon oxide film, and the film 12 is made of a polysilicon film.

As shown in FIG. 5 , the surface of the film 12 is then nitrided to form a silicon nitride film 13 A on the film 12 . Further, a silicon oxide film 13 B and a silicon nitride film 13 C are formed on the silicon nitride film 13 A in order.

The silicon nitride film 13 C, the silicon oxide film 13 B, the silicon nitride film 13 A, the film 12 , the film 11 , and the surface region of the semiconductor substrate 10 are then etched to isolate these films for each memory cell. Further, an insulating film (element isolation region) is embedded in the gaps between the element regions AA and the floating gate electrodes 12 A. The element isolation region is made of, for example, a silicon oxide film.

As shown in FIG. 6 , an element isolation region 15 is then etched back and thereby set back. As a result, the side surface of the floating gate electrode 12 A is exposed, and the silicon nitride film 13 C, the silicon oxide film 13 B, and the silicon nitride film 13 A are left on the upper surface of the floating gate electrode 12 A.

The side surface of the floating gate electrode 12 A and the surface of the element isolation region 15 are then nitrided to form the silicon nitride film 13 A on the side surface of the floating gate electrode 12 A and the upper surface of the element isolation region 15 , as shown in FIG. 7 .

As shown in FIG. 8 , a silicon oxide film 13 D is then formed on the silicon nitride film 13 C on the upper surface of the floating gate electrode 12 A, on the side surface of the floating gate electrode 12 A, and on the element isolation region 15 . That is, the silicon oxide film 13 D is formed on the silicon nitride films 13 A and 13 C.

As shown in FIG. 9 , the surface of the silicon oxide film 13 D is then nitrided to form a silicon nitride film 13 E on the silicon oxide film 13 D. As a result, an intergate insulating film 13 T in which the bottom silicon nitride film 13 A, the bottom silicon oxide film 13 B, the center silicon nitride film 13 C, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order is formed on the upper surface of the floating gate electrode 12 A. Moreover, an intergate insulating film 13 S in which the bottom silicon nitride film 13 A, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order is formed on the side surface of the floating gate electrode 12 A.

On the structure shown in FIG. 9 , that is, on the silicon nitride film 13 E, a control gate electrode 14 A is then formed, as shown in FIG. 3 . Consequently, the NAND flash memory according to the first embodiment is manufactured.

Second Embodiment

In an example described in the second embodiment, a three-layer structure (ONO film) is formed between the upper surface of a floating gate electrode and a control gate electrode, and a single-layer structure (O film) is formed between the side surface of the floating gate electrode and the control gate electrode.

[1] Configuration of Memory Cell Array

FIG. 10 is a sectional view showing the configuration of a memory cell array in a NAND flash memory according to the second embodiment.

An element isolation region 15 , and element regions AA isolated by the element isolation region 15 are arranged in the surface region of a semiconductor substrate 10 . A memory cell MC is disposed on the semiconductor substrate (element region AA) 10 . In the memory cell MC, a gate insulating film (tunnel insulating film) 11 A, a floating gate electrode 12 A, an intergate insulating film 13 P, and a control gate electrode 14 A are stacked in this order.

Intergate insulating film 13 P is formed on the upper surface of the floating gate electrode 12 A. Intergate insulating film 13 P has a stack film (what is known as an ONO film) in which a bottom silicon oxide film 13 B, an insulating film (for example, center silicon nitride film) 13 C, and a top silicon oxide film 13 D are stacked in this order from the side of the floating gate electrode 12 A. The silicon oxide film 13 D is formed on the side surface of the floating gate electrode 12 A. The configuration is similar in other respects to that according to the first embodiment.

According to the second embodiment, intergate insulating film 13 P in which the bottom silicon oxide film 13 B, the insulating film (for example, center silicon nitride film) 13 C, and the top silicon oxide film 13 D are stacked in this order is formed on the upper surface of the floating gate electrode 12 A. The top silicon oxide film 13 D is formed on the side surface of the floating gate electrode 12 A. That is, the intergate insulating film on the side surface of the floating gate electrode 12 A does not have the insulating film 13 C, and intergate insulating film 13 P on the upper surface of the floating gate electrode 12 A has the insulating film 13 C.

As the insulating film 13 C is not present on the side surface of the floating gate electrode 12 A, it is possible to inhibit the spread of a threshold distribution caused when electrons are trapped by the insulating film 13 C on the side surface of the floating gate electrode 12 A because of repeated writing and erasing. Moreover, as a result of the elimination of the insulating film 13 C on the side surface of the floating gate electrode 12 A, the insulating film 13 C on the upper surface of the floating gate electrode 12 A can be increased in thickness without the side effects of the above-mentioned spread of the threshold distribution, in comparison with the case where a NONON film is formed on the upper surface and side surface of the floating gate electrode. Consequently, a leakage current in the intergate insulating film can be reduced, and write saturation that prevents writing up to a necessary threshold can be improved.

As described above, according to the present embodiment, as the intergate insulating film disposed between the floating gate electrode and the control gate electrode, the insulating film 13 C is disposed on the upper surface of the floating gate electrode 12 A without the insulating film 13 C disposed on the side surface of the floating gate electrode 12 A. Consequently, the spread of the threshold distribution of the memory cell resulting from repeated writing and erasing can be inhibited, and the leakage current in the intergate insulating film can be reduced.

[2] Method of Manufacturing Memory Cell Array

Now, a method of manufacturing the NAND flash memory according to the second embodiment is described. FIG. 11 to FIG. 14 are sectional views showing the method of manufacturing the memory cell array in the NAND flash memory according to the second embodiment.

As in the first embodiment, first, as shown in FIG. 11 , a film 11 to be a gate insulating film is formed on a semiconductor substrate 10 , and a film 12 to be a floating gate electrode is formed on the film 11 . For example, the film 11 is made of a silicon oxide film, and the film 12 is made of a polysilicon film.

As shown in FIG. 12 , a silicon oxide film 13 B and a silicon nitride film 13 C are then formed on the film 12 in order. The silicon nitride film 13 C, the silicon oxide film 13 B, the film 12 , the film 11 , and the surface region of the semiconductor substrate 10 are then etched to isolate these films for each memory cell. Further, an insulating film (element isolation region) is embedded in the gaps between the element regions AA and between the floating gate electrodes 12 A. The element isolation region is made of, for example, a silicon oxide film.

As shown in FIG. 13 , an element isolation region 15 is then etched back and thereby set back. As a result, the side surface of the floating gate electrode 12 A is exposed, and the silicon oxide film 13 B and the silicon nitride film 13 C are left on the upper surface of the floating gate electrode 12 A.

As shown in FIG. 14 , a silicon oxide film 13 D is formed on the silicon nitride film 13 C on the upper surface of the floating gate electrode 12 A, on the side surface of the floating gate electrode 12 A, and on the element isolation region 15 . As a result, an intergate insulating film 13 P in which the bottom silicon oxide film 13 B, the center silicon nitride film 13 C, and the top silicon oxide film 13 D are stacked in this order is formed on the upper surface of the floating gate electrode 12 A. Moreover, a single-layer intergate insulating film including the top silicon oxide film 13 D is formed on the side surface of the floating gate electrode 12 A.

On the structure shown in FIG. 14 , that is, on the silicon oxide film 13 D, a control gate electrode 14 A is then formed, as shown in FIG. 10 . The process is similar in other respects to that according to the first embodiment. Consequently, the NAND flash memory according to the second embodiment is manufactured.

Third Embodiment

In an example described in the third embodiment, an intergate insulating film having a four-layer structure (NONO film) is formed on the upper surface of a floating gate electrode, and an intergate insulating film having a five-layer structure (NONON film) is formed on the side surface of the floating gate electrode.

[1] Configuration of Memory Cell Array

FIG. 15 and FIG. 16 are sectional views of a memory cell array in a NAND flash memory according to the third embodiment. FIG. 15 shows a section along the channel length direction (bit-line direction) of a memory cell MC. FIG. 16 shows a section along the channel width direction (word-line direction) of the memory cell MC.

As shown in FIG. 15 and FIG. 16 , an intergate insulating film 13 T is formed on the upper surface of a floating gate electrode 12 A, and an intergate insulating film 13 S is formed on the side surface of the floating gate electrode 12 A and on an element isolation region 15 .

Intergate insulating film 13 T formed on the upper surface of the floating gate electrode 12 A has a stack film (what is known as a NONO film) in which a bottom silicon nitride film 13 A, a bottom silicon oxide film 13 B, an insulating film (for example, center silicon nitride film) 13 C, and a top silicon oxide film 13 D are stacked in this order from the side of the floating gate electrode 12 A. The symbol “N” denotes a silicon nitride film, and the symbol “O” denotes a silicon oxide film.

Intergate insulating film 13 S formed on the side surface of the floating gate electrode 12 A and on the element isolation region 15 has a stack film (what is known as a NONON film) in which a bottom silicon nitride film 13 A, a bottom silicon oxide film 13 B, an insulating film (for example, center silicon nitride film) 13 C, a top silicon oxide film 13 D, and a top silicon nitride film 13 E are stacked in this order from the side of the floating gate electrode 12 A and the element isolation region 15 .

The silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is thicker than the silicon oxide film 13 D on the side surface of the floating gate electrode 12 A and on the element isolation region 15 .

The materials used for intergate insulating films 13 T and 13 S are not limited to the above-mentioned materials, and other materials may be used instead. A silicon oxynitride (SiON) film or a metal oxide film may be used for the insulating film 13 C instead of an insulating (high-k) film such as the above-mentioned silicon nitride (SiN) film having a dielectric constant higher than that of the silicon oxide film. The metal oxide film includes, for example, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminate (LaAlO 3 ), hafnium aluminate (HfAlOx), tantalum oxide (Ta 2 O 5 ), and titanium oxide (TiO 2 ). These materials are not limited to the composition ratios in parentheses.

Intergate insulating film 13 T has a four-layer structure (NONO film) on the upper surface of the floating gate electrode 12 A, and intergate insulating film 13 S has a five-layer structure (NONON film) on the side surface of the floating gate electrode 12 A and on the element isolation region 15 . However, these intergate insulating films are not limited to such structures. For example, a three-layer structure (ONO film) may be provided on the upper surface of the floating gate electrode 12 A, and a four-layer structure (ONON film) may be provided on the side surface of the floating gate electrode 12 A and on the element isolation region 15 . Other multilayer structures may be provided.

The control gate electrode 14 A is formed on intergate insulating films 13 T and 13 S. That is, the control gate electrode 14 A is formed on the upper surface and side surface of the floating gate electrode 12 A via intergate insulating films 13 T and 13 S, respectively. The control gate electrode 14 A is equivalent to a word line WL.

For example, a silicide film is used for the control gate electrode 14 A to reduce electric resistance. However, the control gate electrode 14 A is not limited to the silicide film, and may have a single-layer structure of a polysilicon film or a double-layer structure (polycide structure) in which a polysilicon film and a silicide film are stacked. As the silicide film, for example, a tungsten silicide film, a molybdenum silicide film, a cobalt silicide film, a titanium silicide film, or a nickel silicide film is used.

The control gate electrode 14 A functions as a word line, and is shared between the adjacent memory cells MC. Therefore, the control gate electrode 14 A is formed not only on the floating gate electrode 12 A but also on the element isolation region 15 . The configuration is similar in other respects to that according to the first embodiment.

According to the third embodiment, intergate insulating film 13 T is formed on the upper surface of the floating gate electrode 12 A. In this intergate insulating film 13 T, the bottom silicon nitride film 13 A, the bottom silicon oxide film 13 B, the insulating film (for example, center silicon nitride film) 13 C, and the top silicon oxide film 13 D are stacked in this order. Intergate insulating film 13 S is formed on the side surface of the floating gate electrode 12 A. In intergate insulating film 13 S, the bottom silicon nitride film 13 A, the bottom silicon oxide film 13 B, the insulating film 13 C, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order. The top silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is thicker than the top silicon oxide film 13 D on the side surface of the floating gate electrode 12 A. Consequently, in the memory cell according to the third embodiment, a leakage current in the intergate insulating film can be reduced, and write saturation that prevents writing up to a necessary threshold can be improved.

The leakage current can be reduced and the write saturation can be improved for the following reasons. For example, when the intergate insulating film which is in contact with the control gate electrode is a silicon nitride film, holes tend to be injected into the center silicon nitride film from the control gate electrode because the barrier against holes is lower in the silicon nitride film than in a silicon oxide film. FIG. 17A shows an energy band graph when the intergate insulating film is a NONON film. As apparent from FIG. 17A , the amount of holes injected into the center silicon nitride film from the control gate electrode is great because the NONON film has a low barrier against holes. Thus, electrons trapped by the center silicon nitride film are recombined with the holes, so that the trapped electrons in the center silicon nitride film are reduced, and the leakage current in the intergate insulating film more easily runs.

On the other hand, as in the present embodiment, when the intergate insulating film which is in contact with the control gate electrode 14 A is the top silicon oxide film 13 D instead of the silicon nitride film, the barrier against holes is higher, and the injection of holes from the control gate electrode 14 A is reduced. FIG. 17B shows an energy band graph when the intergate insulating film is a NONO film. As apparent from FIG. 17B , in this case, the injection of holes is less, and the recombination of the trapped electrons in the insulating film 13 C and the holes is also less. Thus, in comparison with the NONON film, the NONO film can reduce the leakage current in the intergate insulating film because the amount of trapped electrons in the insulating film 13 C is greater.

Here, a high leakage current is generated in the vicinity of the upper surface of the floating gate electrode 12 A by the concentration of an electric field. Therefore, the top silicon oxide film 13 D is used on the upper surface of the floating gate electrode 12 A instead of the silicon nitride film, and the thickness of the top silicon oxide film 13 D is increased. This allows a considerable reduction of the leakage current in intergate insulating film 13 T.

Furthermore, according to the third embodiment, the intergate insulating (NONON) film in which the bottom silicon nitride film 13 A, the bottom silicon oxide film 13 B, the insulating film (for example, center silicon nitride film) 13 C, the top silicon oxide film 13 D, and the top silicon nitride film 13 E are stacked in this order is formed on the side surface of the floating gate electrode 12 A. It is thereby possible to inhibit the phenomenon in which the threshold distribution of each of multiple values in the memory cell spreads when writing and erasing are repeated.

The phenomenon of the spread of the threshold distribution of the memory cell can be inhibited for the following reasons. For example, when the intergate insulating film which is in contact with the control gate electrode 14 A on the side surface of the floating gate electrode 12 A is a silicon oxide film, electrons trapped by the insulating film 13 C do not easily escape toward the control gate electrode 14 A. As a result, it is difficult to inhibit the phenomenon in which the threshold distribution of each of multiple values in the memory cell spreads.

On the other hand, as in the present embodiment, when intergate insulating film 13 S which is in contact with the control gate electrode 14 A on the side surface of the floating gate electrode 12 A is the top silicon nitride film 13 E, the electrons trapped by the insulating film 13 C easily escape toward the control gate electrode 14 A via the top silicon nitride film 13 E. As a result, it is possible to inhibit the phenomenon in which the threshold distribution of each of multiple values spreads.

Furthermore, according to the third embodiment, the leakage current in the intergate insulating film can be reduced, so that the thickness of the intergate insulating film can be reduced. As the thickness of the intergate insulating film can be reduced, the following advantages are provided.

Firstly, as the thickness of the intergate insulating film can be reduced, a coupling ratio between the floating gate electrode 12 A and the control gate electrode 14 A can be increased. Secondly, the distance between the floating gate electrodes 12 A to embed the control gate electrode 14 A can be increased, and the control gate electrode 14 A can therefore be easily embedded between the floating gate electrodes 12 A. Thirdly, as the distance between the floating gate electrodes 12 A to embed the control gate electrode 14 A can be increased, the volume of the control gate electrode 14 A can be increased, and the depletion of the control gate electrode 14 A can be inhibited. Fourthly, as the thickness of the intergate insulating film can be reduced, the floating gate electrode 12 A can be reduced in thickness while the coupling ratio between the floating gate electrode 12 A and the control gate electrode 14 A is maintained.

As described above, according to the present embodiment, the intergate insulating film which is in contact with the control gate electrode on the upper surface of the floating gate electrode is a silicon oxide film. The thickness of this film is larger than the thickness of the silicon oxide film on the side surface of the floating gate electrode. Consequently, the leakage current in the intergate insulating film can be reduced.

Moreover, as the intergate insulating film disposed between the floating gate electrode and the control gate electrode, the NONO film is disposed on the upper surface of the floating gate electrode, and the NONON film is disposed on the side surface of the floating gate electrode. Consequently, the leakage current in the intergate insulating film can be reduced without deterioration of the threshold distribution of the memory cell.

[2] Method of Manufacturing Memory Cell Array

Now, a method of manufacturing the NAND flash memory according to the third embodiment is described. FIG. 18 to FIG. 22 are sectional views showing the method of manufacturing the memory cell array in the NAND flash memory according to the third embodiment.

A gate insulating film and a floating gate electrode are formed on a semiconductor substrate, and then an insulating film (element isolation region) is embedded between element regions AA and between the floating gate electrodes. For example, the gate insulating film and the element isolation region are made of silicon oxide films, and the floating gate electrode is made of a polysilicon film.

In the structure described above, first, as shown in FIG. 18 , an element isolation region 15 is etched back and thereby set back. As a result, the upper surface and side surface of the floating gate electrode 12 A are exposed.

The upper surface and side surface of the floating gate electrode 12 A and the surface of the element isolation region 15 are then nitrided to form a silicon nitride film 13 A on the upper surface and side surface of the floating gate electrode 12 A and on the upper surface of the element isolation region 15 .

As shown in FIG. 20 , a silicon oxide film 13 B, a silicon nitride film 13 C, and a silicon oxide film 13 D are then formed on the silicon nitride film 13 A in this order. Further, as shown in FIG. 21 , the surface of the silicon oxide film 13 D is nitrided to form a silicon nitride film 13 E on the silicon oxide film 13 D.

The silicon nitride film 13 E on the upper surface of the floating gate electrode 12 A is then anisotropically oxidized, and as shown in FIG. 22 , the silicon nitride film 13 E on the upper surface of the floating gate electrode 12 A is oxidized and thus transformed into a silicon oxide film. As a result, the silicon oxide film 13 D disposed on the silicon nitride film 13 C on the upper surface of the floating gate electrode 12 A is thicker than the silicon oxide film 13 D on the silicon nitride film 13 C on the side surface of the floating gate electrode 12 A. The anisotropic oxidation only oxidizes the upper surface of the floating gate electrode 12 A by plasma oxidation or by oxygen (O) ion implantation and does not oxidize its side surface.

As shown in FIG. 16 , a control gate electrode 14 A is then formed on the structure shown in FIG. 22 , that is, on the silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A, and on the silicon nitride film 13 E on the side surface of the floating gate electrode 12 A and on the element isolation region 15 . Consequently, the NAND flash memory according to the third embodiment is manufactured.

As described above, the following process is used in the manufacturing method according to the present embodiment. As shown in FIG. 21 , the NONON film is formed on the upper surface and side surface of the floating gate electrode 12 A. The uppermost silicon nitride film 13 E on the upper surface of the floating gate electrode 12 A is then anisotropically oxidized and thus transformed into a silicon oxide film. As a result, the uppermost silicon oxide film on the upper surface of the floating gate electrode 12 A can be thicker than the uppermost silicon oxide film on the side surface of the floating gate electrode 12 A.

Fourth Embodiment

In an example described in the fourth embodiment, an intergate insulating film having a three-layer structure (ONO film) is formed between a floating gate electrode and a control gate electrode.

[1] Configuration of Memory Cell Array

FIG. 23 is a sectional view showing the configuration of a memory cell array in a NAND flash memory according to the fourth embodiment.

An element isolation region 15 , and element regions AA isolated by the element isolation region 15 are arranged in the surface region of a semiconductor substrate 10 . A memory cell MC is disposed on the semiconductor substrate (element region AA) 10 . In the memory cell MC, a gate insulating film (tunnel insulating film) 11 A, a floating gate electrode 12 A, an intergate insulating film 13 F, and a control gate electrode 14 A are stacked in this order.

Intergate insulating film 13 F is formed on the upper surface and side surface of the floating gate electrode 12 A and on the element isolation region 15 .

Intergate insulating film 13 F has a stack film (what is known as an ONO film) in which a bottom silicon oxide film 13 B, an insulating film (for example, center silicon nitride film) 13 C, and a top silicon oxide film 13 D are stacked in this order from the side of the floating gate electrode 12 A and the element isolation region 15 . The silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is thicker than the silicon oxide film 13 D on the side surface of the floating gate electrode 12 A and on the element isolation region 15 . The configuration is similar in other respects to that according to the third embodiment.

According to the fourth embodiment, intergate insulating film 13 F is formed on the upper surface and side surface of the floating gate electrode 12 A. In this intergate insulating film 13 F, the bottom silicon oxide film 13 B, the center silicon nitride film 13 C, and the top silicon oxide film 13 D are stacked in this order. The top silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is thicker than the top silicon oxide film 13 D on the side surface of the floating gate electrode 12 A. Consequently, in the memory cell according to the fourth embodiment, a leakage current in intergate insulating film 13 F can be reduced, and write saturation that prevents writing up to a necessary threshold can be improved.

As described above, according to the present embodiment, the intergate insulating film which is in contact with the control gate electrode on the upper surface of the floating gate electrode is a silicon oxide film. The thickness of this film is larger than the thickness of the silicon oxide film on the side surface of the floating gate electrode. Consequently, the leakage current in the intergate insulating film can be reduced.

[2] Method of Manufacturing Memory Cell Array

Now, a method of manufacturing the NAND flash memory according to the fourth embodiment is described. FIG. 24 to FIG. 26 are sectional views showing the method of manufacturing the memory cell array in the NAND flash memory according to the fourth embodiment.

As in the third embodiment, first, as shown in FIG. 24 , an element isolation region 15 is etched back and thereby set back. As a result, the upper surface and side surface of the floating gate electrode 12 A are exposed.

As shown in FIG. 25 , a silicon oxide film 13 B, a silicon nitride film 13 C, and a silicon oxide film 13 D are then formed on the upper surface and side surface of the floating gate electrode 12 A and on the element isolation region 15 in this order.

The silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is then anisotropically oxidized, and as shown in FIG. 26 , the silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is increased in thickness. As a result, the silicon oxide film 13 D disposed on the silicon nitride film 13 C on the upper surface of the floating gate electrode 12 A is thicker than the silicon oxide film 13 D on the silicon nitride film 13 C on the side surface of the floating gate electrode 12 A. The process is similar in other respects to that according to the third embodiment.

As described above, the following process is used in the manufacturing method according to the present embodiment. As shown in FIG. 25 , the ONO film is formed on the upper surface and side surface of the floating gate electrode 12 A. The uppermost silicon oxide film 13 D on the upper surface of the floating gate electrode 12 A is then increased in thickness by the anisotropic oxidation as shown in FIG. 26 . As a result, the uppermost silicon oxide film on the upper surface of the floating gate electrode 12 A can be thicker than the uppermost silicon oxide film on the side surface of the floating gate electrode.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.