Voltage regulator

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0127910 filed on Dec. 1, 2011, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

1. Technical Field

The present invention relates generally to a semiconductor integrated circuit, and more particularly to a voltage regulator.

2. Related Art

A semiconductor memory apparatus has a voltage regulator is in order to generate a voltage used therein. In designing the voltage regulator, it is important to stably provide a voltage of a desired target level.

In an embodiment of the present invention, a voltage regulator includes: a voltage generation unit configured to compare a reference voltage level with a voltage level of a first node and generate an output voltage at an output terminal thereof; a first resistor section including a first sub-resistor and a second sub-resistor between the first node and a ground voltage, and controlling a connection between the first sub-resistor and the second sub-resistor to change a size of the resistors; and a second resistor section including a reference resistor, a plurality of unit resistors, and a plurality of step resistors obtained by dividing a size of the unit resistors between the output terminal and the first node, and controlling connections of the unit resistors and the step resistors to change a size of the resistors.

In an embodiment of the present invention, a voltage regulator includes: a voltage generation unit configured to compare a reference voltage level with a voltage level of a first node and generate an output voltage at an output terminal thereof; a first resistor section including a first sub-resistor and a second sub-resistor between the first node and a ground voltage, and controlling a connection of the first sub-resistor according to a division signal; and a second resistor section including a reference resistor and a plurality of second resistors between the output terminal and the first node, controlling connections of the plurality of second resistors to change a size of the resistors, and reducing a size of each second resistor to ½ according to the division signal.

In an embodiment of the present invention, a voltage regulator includes: a voltage generation unit configured to compare a reference voltage level with a voltage level of a first node and generate an output voltage at an output terminal thereof; a first sub-resistor and a second sub-resistor serially connected between the first node and a ground voltage; a first transistor having source and drain terminals connected at both ends of the first sub-resistor and a gate terminal for receiving a division signal; a reference resistor, a unit resistor, and a plurality of step resistors serially connected between the output terminal and the first node; a second transistor having source and drain terminals connected at both ends of the unit resistor and a gate terminal for receiving a unit resistor selection signal; and a plurality of third transistors having source terminals, which are connected to a plurality of nodes through which the unit resistor is connected to the plurality of step resistors, drain terminals connected to the first node, and gate terminals for receiving a step resistor selection signal, respectively, wherein the step resistor has a value obtained by dividing a size of the unit resistor by a plural number.

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a circuit diagram of a voltage regulator according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a resistor unit of FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a resistor unit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a resistor unit according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of a resistor unit according to an embodiment of the present invention; and

FIG. 6 is a detailed circuit diagram of a second resistor unit of FIG. 5 .

Hereinafter, a voltage regulator according to the present invention will be described in detail with reference to the accompanying drawings through an exemplary embodiment of the present invention.

FIG. 1 is a circuit diagram of a voltage regulator according to an embodiment of the present invention.

The voltage regulator includes a voltage generation unit 2 and a resistor unit 1 .

The voltage generation unit 2 compares a reference voltage VREF with a voltage level of a first node ND 1 , and controls an output voltage VOUT according to a result of the comparison. That is, when the output voltage VOUT changes from a target level, the voltage generation unit 2 adjusts the supply of a pumping voltage VPUMP according to the output of a comparator OP 1 , thereby stably controlling the output voltage VOUT.

The resistor unit 1 has a function of adjusting a resistance value to adjust the level of the output voltage VOUT. In the voltage regulator, the output voltage VOUT may be expressed by Equation below.

V OUT=(1+ R 2/ R 1)* V REF

Since the voltage regulator is a negative feedback circuit, the level of the output voltage VOUT corresponds to (1+R 2 /R 1 ) times the reference voltage VREF. This represents that it is possible to generate an output voltage VOUT of another target level by adjusting the ratio of a second resistor R 2 with respect to a first resistor R 1 in the resistor unit 1 .

FIG. 2 is a circuit diagram of a resistor unit 1 according to an embodiment of the present invention. In a known art, in order to adjust the resistor ratio (R 2 /R 1 ), the resistance value of the second resistor R 2 is changed.

The resistor unit 1 includes a first resistor R 1 connected between a first node ND 1 and a ground voltage VSS, and a reference resistor R 2 _ 0 and a plurality of second resistors R 2 _ 1 to R 2 _ 39 connected between an output voltage VOUT and the first node ND 1 . Here, the number of second resistors R 2 to be connected is adjusted in response to a plurality of selection signals S 1 to S 39 .

For example, when it is assumed that the resistance value of the reference resistor R 2 _ 0 is set to 40Ω and the resistance value of each of the plurality of second resistors R 2 _ 1 to R 2 _ 39 is set to 1Ω, connections of the second resistors R 2 _ 1 to R 2 _ 39 are controlled using the selection signals S 1 to S 39 , so that it is possible to adjust the resistance ratio (i.e., R 2 /R 1 ). Thus, if the first resistor R 1 is 10Ω, since an output voltage VOUT, when only the reference resistor R 2 _ 0 is connected, has a level of 5*VREF and the level of the output voltage VOUT increases by 0.1*VREF per every additional connection of the second resistor R 2 , the output voltage VOUT has a maximum level of 8.9*VREF.

However, the method for adjusting the level of the output voltage VOUT in the resistor unit 1 requires many resistors R 2 _ 1 to R 2 _ 39 and selection transistors N 1 to N 39 in order to perform fine adjustment, and thus the area of the resistor unit 1 may increase.

FIG. 3 is a circuit diagram illustrating a resistor unit of a voltage regulator according to an embodiment of the present invention.

According to an embodiment of the present invention, a resistor unit for adjusting the resistor ratio (R 2 /R 1 ) is configured in the voltage regulator having the feedback structure in which the output voltage VOUT has a voltage level corresponding to (1+R 2 /R 1 ) times the reference voltage VREF.

A resistor unit 10 of FIG. 3 includes a first resistor section R 1 and a second resistor section R 2 .

The first resistor section R 1 is coupled between a first node ND 1 and a ground voltage VSS and has a resistance value set to a predetermined level.

The second resistor section R 2 includes a reference resistor R 2 A_ 0 , a plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 , and a plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 serially coupled to one another. Here, the resistance value of each step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 may be obtained by dividing the resistance value of each unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 . Furthermore, the second resistor section R 2 includes a plurality of selection transistors NA 1 , NA 2 , . . . , NA 4 and NB 1 , NB 2 , . . . , NB 7 which control connections of the plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 and connections of the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 , respectively.

The plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 may be configured for rough adjustment, and the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 may be configured for fine adjustment.

The connections of the plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 are controlled using the plurality of unit selection transistors NA 1 , NA 2 , . . . , NA 4 and a plurality of unit resistor selection signals S 1 , S 2 , . . . , S 4 . The plurality of unit selection transistors NA 1 , NA 2 , . . . , NA 4 have gate terminals for receiving the corresponding unit resistor selection signals S 1 , S 2 , . . . , S 4 , source terminals coupled to nodes, through which the reference resistor R 2 A_ 0 is coupled to the plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 , and drain terminals coupled to a second node ND 2 , respectively.

The connections of the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 are controlled using the plurality of step selection transistors NB 1 , NB 2 , . . . , NB 7 and a plurality of step resistor selection signals STEP 1 , STEP 2 , . . . , STEP 7 . The plurality of step selection transistors NB 1 , NB 2 , . . . , NB 7 have gate terminals for receiving the corresponding step selection signals STEP 1 , STEP 2 , . . . , STEP 7 , source terminals coupled to a plurality of nodes, through which the second node ND 2 and the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 are coupled to each other, and drain terminals coupled to the first node ND 1 , respectively.

For example, the reference resistor R 2 A_ 0 may be set to 40Ω, each unit resistor R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 may be set to 8Ω, and each step resistor R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 may be set to 1Ω. In this case, the connections of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 can be controlled so as to adjust the resistance value of the second resistor section R 2 by multiples of 8Ω such as 48Ω, 56Ω, or 64Ω, and the connections of the step resistors R 2 B can be controlled so as to adjust the resistance value of the second resistor section R 2 by multiples of 1Ω smaller than the unit resistance of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 .

As a consequence, the resistance value of the second resistor section R 2 can be adjusted from 40Ω to 79Ω at an interval of 1Ω using the reference resistor R 2 A_ 0 , the four unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 , the seven step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 , and the 11 selection transistors NA 1 , NA 2 , . . . , NA 4 and NB 1 , NB 2 , . . . , NB 7 . Here, a number of the unit resistors and the step resistors may vary.

In an embodiment of the present invention, the resistor unit 10 of the voltage regulator according to an embodiment of the present invention adjusts a resistance value using relatively large resistors and small resistors obtained by dividing the resistance value of the large resistors, thereby obtaining the same voltage division effect using a smaller number of elements.

FIG. 4 is a circuit diagram of a resistor unit 100 according to an embodiment of the present invention.

The resistor unit 100 includes a first resistor section 110 and a second resistor section 120 .

The first resistor section 110 includes a plurality of sub-resistors R 1 _ 1 and R 1 _ 2 as a first resistor. In an embodiment of the present invention, the first resistor section 110 includes a first sub-resistor R 1 _ 1 and a second sub-resistor R 1 _ 2 between a first node ND 1 and a ground voltage VSS. Here, a connection of the first sub-resistor R 1 _ 1 may be controlled according to a division signal DV.

The second resistor section 120 may include a plurality of second resistors, control the number of the second resistors to be connected, and change the resistance value of the resistors.

In detail, the second resistor section 120 may include a plurality of resistors, having the same resistance value, between the output voltage VOUT and the first node ND 1 , or may include a plurality of unit resistors, e.g., four unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 and a plurality of step resistors, e.g., seven step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 . In an embodiment of the present invention, the number of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_n to be connected is adjusted in response to unit resistor selection signals S[ 1 : 4 ], and the number of the step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_m to be connected is adjusted in response to step resistor selection signals S[ 1 : 7 ].

In an embodiment of the present invention, only the resistance value of the second resistor R 2 can be adjusted in order to adjust the resistor ratio (R 2 /R 1 ). However, in another embodiment of the present invention, the resistance value of the first resistor R 1 can also be adjusted so as to effectively change the level of the output voltage VOUT using a relatively small number of elements.

In detail, the first resistor section 110 includes the first sub-resistor R 1 _ 1 and the second sub-resistor R 1 _ 2 coupled between the first node ND 1 and the ground voltage VSS, and a division transistor N 11 which controls the connection of the first sub-resistor R 1 _ 1 in response to the division signal DV.

When the resistance value of first sub-resistor R 1 _ 1 and the resistance value of the second sub-resistor R 1 _ 2 are set as the same value, the first resistor section 110 has a resistance value of R 1 when receiving a deactivated division signal DV and a resistance value of R 1 / 2 when receiving an activated division signal DV. Consequently, when the resistance value of the second resistor section 120 varies in the range of 40Ω to 79Ω, the division signal DV is activated, so that it is possible to increase the resistance ratio (R 2 /R 1 ) to a value twice as large as the resistance ratio in the case of FIG. 2 . As a consequence, by reducing the resistance value of R 1 by half, the value of the output voltage may increase to a level corresponding to (1+2*(R 2 /R 1 ))*VREF. In an embodiment of the present invention, the first resistor R 1 is divided into two resistors. However, the present invention is not limited thereto. For example, the first resistor R 1 may be divided into various numbers of sub-resistors.

The target level of the output voltage VOUT can be adjusted at an interval of 0.2*VREF in this case while the target level of the output voltage VOUT can be adjusted at an interval of 0.1*VREF in the case of the first resistor R 1 is 10Ω. That is, the output voltage VOUT may increase effectively, but fine adjustment ability may deteriorate.

FIG. 5 is a circuit diagram of a resistor unit 100 according to an embodiment of the present invention.

The resistor unit 100 of FIG. 5 includes a first resistor section 110 and a second resistor section 120 .

The first resistor section 110 includes the first sub-resistor R 1 _ 1 and the second sub-resistor R 1 _ 2 between the first node ND 1 and the ground voltage VSS as described with reference to FIG. 4 . Here, the connection of the first sub-resistor R 1 _ 1 may be controlled according to the division signal DV so as to effectively change the target level of an output voltage VOUT.

The second resistor section 120 includes a unit division part 121 and a step division part 122 coupled between the output voltage VOUT and the first node ND 1 .

The unit division part 121 changes a resistance value by the relatively high level in response to the unit resistor selection signals S[ 1 : 4 ], and reduces the changed resistor level, for example, by half in response to the division signal DV.

The step division part 122 changes a resistance value by the relatively low level in response to the step selection signals STEP[ 1 : 7 ], and reduces the changed resistor level, for example, by half in response to the division signal DV.

According to an embodiment of the present invention, for example, when the division signal DV is activated and the resistance value of the first resistor R 1 is reduced by half, each of the unit division part 121 and the step division part 122 reduces the changed resistor level by half, thereby adjusting the output voltage VOUT by the unit the same as that when the division signal DV is deactivated.

FIG. 6 is a detailed circuit diagram of the second resistor unit 120 of FIG. 5 according to an embodiment of the present invention.

The second resistor section 120 includes the unit division part 121 coupled between the output voltage VOUT and a second node ND 2 and the step division part 122 coupled between the second node ND 2 and the first node ND 1 .

The unit division part 121 includes a reference resistor R 2 A_ 0 , a plurality of unit resistors R 2 A_ 1 (e.g., R 2 A_ 11 and R 2 A_ 12 ), R 2 A_ 2 (e.g., R 2 A_ 21 and R 2 A_ 22 ), R 2 A_ 3 (e.g., R 2 A_ 31 and R 2 A_ 32 ), R 2 A_ 4 (e.g., R 2 A_ 41 and R 2 A_ 42 ), and a plurality of unit selection transistors NA 11 , NA 12 , . . . , NA 14 for controlling the connections of the plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 in response to the unit resistor selection signals S 1 , S 2 , . . . , S 4 . Here, the reference resistor R 2 A_ 0 and the plurality of unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 are serially coupled to one another. Furthermore, the unit division part 121 includes a plurality of division transistors ND 21 , ND 22 , . . . , ND 24 for reducing each resistance value of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 by half in response to the division signal DV.

When a deactivated division signal DV is received, the unit division part 121 controls the connections of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 according to the unit resistor selection signals S 1 , S 2 , . . . , S 4 .

When an activated division signal DV is received, the unit division part 121 reduces the resistance value of each of the unit resistors R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 by half to create divided unit resistors R 2 A_ 11 , R 2 A_ 21 , . . . , R 2 A_ 41 , and controls the connections of the divided unit resistors R 2 A_ 11 , R 2 A_ 21 , . . . , R 2 A_ 41 according to the unit resistor selection signals S 1 , S 2 , . . . , S 4 .

The step division part 122 includes a plurality of step resistors R 2 B_ 1 (e.g., R 2 B_ 11 and R 2 B_ 12 ), R 2 B_ 2 (e.g., R 2 B_ 21 and R 2 B_ 22 ), . . . , R 2 B_ 7 (e.g., R 2 B_ 71 and R 2 B_ 72 ), and a plurality of step selection transistors NB 11 , NB 12 , . . . , NB 17 for controlling the connections of the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 in response to the step resistor selection signals STEP 1 , STEP 2 , . . . , STEP 7 . Here, the plurality of step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 are serially coupled to one another. Furthermore, the step division part 122 includes a plurality of division transistors ND 11 , ND 12 , . . . , ND 17 for reducing each resistance value of the step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 by half in response to the division signal DV.

When the deactivated division signal DV is received, the is step division part 122 controls the connections of the step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 according to the step resistor selection signals STEP 1 , STEP 2 , . . . , STEP 7 .

When the activated division signal DV is received, the step division part 122 reduces the resistance value of each of the step resistors R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 by half to create divided step resistors R 2 B_ 11 , R 2 B_ 21 , . . . , R 2 B_ 71 , and controls the connections of the divided step resistors R 2 B_ 11 , R 2 B_ 21 , . . . , R 2 B_ 71 according to the step resistor selection signals STEP 1 , STEP 2 , . . . , STEP 7 .

For example, the reference resistor R 2 A_ 0 may be set to 40Ω, each unit resistor R 2 A_ 1 , R 2 A_ 2 , . . . , R 2 A_ 4 may be set to 8Ω, and each step resistor R 2 B_ 1 , R 2 B_ 2 , . . . , R 2 B_ 7 may be set to 1Ω. When the division signal DV is activated, the divided unit resistors R 2 A_ 11 , R 2 A_ 21 , . . . , R 2 A_ 41 are set to 4Ω and the divided step resistors R 2 B_ 11 , R 2 B_ 21 , . . . , R 2 B_ 71 are set to 0.5Ω.

If the first resistor R 1 is set to 10Ω and the deactivated division signal DV is input, the first resistor section 110 has a resistance value of 10Ω, and the second resistor section 120 may vary from 40Ω to 79Ω at an interval of 1Ω. That is, the output voltage VOUT may vary from 5*VREF to 8.9*VREF at an interval of 0.1*VREF.

When the activated division signal DV is input, the first resistor section 110 has a resistance value of 5Ω, and the second resistor section 120 may vary from 40Ω to 59.5Ω at an interval of 0.5Ω. That is, the output voltage VOUT may vary from 9*VREF to 11.9*VREF at an interval of 0.1*VREF.

That is, the resistance level of the first resistor section 110 and a variable resistance level of the second resistor section 120 are reduced by half using the division signal DV, so that it is possible to finely adjust the level of the output voltage VOUT while effectively increasing the level of the output voltage VOUT.

While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the voltage regulator described herein should not be limited based on the described embodiments. Rather, the voltage regulator described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.