Package systems including passive electrical components

The present application claims priority of U.S. Provisional Patent Application No. 61/530,652, filed on Sep. 2, 2011, which is incorporated herein by reference in its entirety.

The present disclosure relates generally to the field of semiconductor and, more particularly, to package systems including passive electrical components.

Portable devices, such as mobile phones, laptops, etc., are widely used, and are equipped with various functionalities. For example, mobile phones are used to place telephone calls, take photographs, access the Internet, send and receive email, check stock quotes and sports scores, as well as operate as a personal digital assistant (or PDA) and/or MP3 player.

The present disclosure is understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the numbers and dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic top view of an exemplary package system.

FIGS. 2A-2C are schematic cross-sectional views of various exemplary package systems taken along section line A-A of FIG. 1

FIGS. 3A-3E are schematic drawings of various exemplary DC/DC converters.

FIG. 3F is a schematic drawing of an exemplary inductive switch regulator.

Portable devices usually are powered by small batteries so as to be carried easily and lightly. The batteries are configured to provide a voltage level of around, e.g., 3.6 V, depending on the type of the portable device. To supply power to integrated circuits in the portable device, the battery voltage is regulated down to a small voltage, e.g., 1 V. In some techniques, a DC/DC converter which includes inductors is adopted to regulate the battery voltage.

A DC/DC converter that is known to the applicants includes a plurality of discrete inductors. To regulate the battery voltage, the inductors are bonded on a printed circuit board (PCB). The inductors are wired bonded with the PCB to electrically communicate with other circuitries that are also bonded on the PCB. Applicants found that the discrete inductors are expensive. Additionally, the discrete inductors are disposed on a certain area of the PCB, leaving large footprints on the PCB. Applicants also found that due to the wire bonding, the efficiency of the DC/DC converter may not reach a desired level.

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

FIG. 1 is a schematic top view of an exemplary package system. In FIG. 1 , a package system 100 includes a plurality of passive electrical components 110 that are disposed over a surface of a passivation structure (not labeled). In some embodiments, the passive electrical components 110 are arranged in an array fashion. In some embodiments, at least two of the passive electrical components 110 are electrically coupled to each other in a parallel or series fashion. In other embodiments, the passive electrical components 110 are electrically isolated from each other. The passive electrical components 110 each can be a capacitor, an inductor or a resistor.

FIG. 2A is a schematic cross-sectional view of a first exemplary package system taken along section line A-A of FIG. 1 . In FIG. 2A , the package system 100 includes at least one active circuitry, e.g., an active circuitry 120 that is disposed over a substrate 101 . In some embodiments, the active circuitry 120 includes at least one switch, at least one logic circuitry, at least one controller, at least one analog circuitry, at least one mixed-signal circuitry, at least one processor, other active circuitries, and/or any combinations thereof.

For example, the package system 100 includes a DC/DC converter. The active circuitry 120 includes one or more switches that are operable to electrically couple one or more of the passive electrical components 110 to each other. FIGS. 3A-3E are schematic drawing of various types of exemplary DC/DC converters. In FIG. 3A , the active circuitry 120 includes switches S 1 -S 6 and the passive electrical components 110 includes capacitors C 1 -C 3 . In FIG. 3B , the active circuitry 120 includes switches S 7 -S 15 and the passive electrical components 110 includes capacitors C 4 -C 6 . In FIG. 3C , the active circuitry 120 includes switches S 16 -S 23 and the passive electrical components 110 includes capacitors C 7 -C 9 . In FIG. 3D , the active circuitry 120 includes switches S 24 -S 33 and the passive electrical components 110 includes capacitors C 10 -C 14 . In FIG. 3E , the active circuitry 120 includes switches S 34 -S 43 and the passive electrical components 110 includes capacitors C 15 -C 17 .

In some embodiments, the capacitors C 1 -C 17 each have a capacitance ranging from about 100 nanofarad (nF) to about 5 micro farad (μF). By using one of the various DC/DC converters shown in FIGS. 3A-3E , an input voltage (V in ), e.g., 3.6 V from a battery can be regulated down to an output voltage (V out ) of about 1 V that is supplied to the active circuitry 120 . In some embodiments, the capacitors C 1 -C 17 each are a surface-mount device (SMD) capacitor. It is noted that the various types of the DC/DC converters described above in conjunction with FIGS. 3A-3E are merely exemplary. In some embodiments, the passive electrical components 110 and the active circuitry 120 are arranged to form different DC/DC converters. In other embodiments, one or more inductors are used in place of one or more of the capacitors C 1 -C 17 to regulate the battery.

In some embodiments, the package system 100 includes an inductive switch regulator as shown in FIG. 3F . The active circuitry 120 includes switches S 43 and S 44 that are operable to electrically couple one or more of a capacitor C 18 and an inductor L to each other. It is noted that the DC/DC converters and the inductive switch regulator described above in conjunction with FIGS. 3A-3F are merely exemplary. The scope of the application is not limited thereto. In some embodiments, the package system 100 includes at least one of a boost switch regulator, a buck converter, other types of regulators or converters, other circuitries that include passive electrical components, and/or any combinations thereof.

In some embodiments, the substrate 101 is made of an elementary semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In one embodiment, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In yet another embodiment, a SiGe substrate is strained. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some examples, the semiconductor substrate includes a doped epi layer or a buried layer. In other examples, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.

Referring to FIG. 2A , an interconnect structure 130 is disposed over the active circuitry 120 . In some embodiments, the interconnect structure 130 includes at least one dielectric layer and at least one electrical connection structure (not shown). For example, the interconnect structure 130 includes multiple dielectric layers and multiple layers of electrical connection structures. The electrical connection structures each are between two dielectric layers. The electrical connection structures are configured to provide electrical connection among transistors, diodes, devices, circuitries, and/or other electrical components of the active circuitry 120 . In some embodiments, the dielectric layers and the conductive structures are arranged to form various passive devices, e.g., capacitors, resistors, and/or inductors.

In some embodiments, the dielectric layers include at least one material, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectric material, ultra low-k dielectric material, other dielectric materials, and/or any combinations thereof. The electrical connection structures include at least one structure, such as via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, metallic slats, other electrical connection structures, and/or any combinations thereof. In some embodiments, the via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, and metallic slats are made of at least one material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other proper conductive materials, and/or combinations thereof.

Referring again to FIG. 2A , a passivation structure 150 is disposed over the active circuitry 120 . The passivation structure 150 has at least one opening, e.g., openings 151 a - 151 d configured to expose at least one electrical pad, e.g., electrical pads 140 a - 140 d , respectively. In some embodiments, the electrical pads 140 a - 140 d are electrically coupled with the active circuitry 120 through the interconnect structure 130 .

In some embodiments, the electrical pads 140 a - 140 d are made of at least one material, such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other conductive materials, and/or any combinations thereof. In some embodiments, the electrical pads 140 a - 140 d each include an under bump metallization (UBM) layer (not shown).

In some embodiments, the passivation structure 150 includes at least one dielectric layer and/or at least one polymer layer. The dielectric layer can include a material such as oxide, nitride, oxynitride, other dielectric materials, and/or any combinations thereof. The polymer layer can include a material such as thermoplastic, thermoset, elastomer, coordination polymer, other suitable polymers, and/or any combinations thereof. In some embodiments, the passivation structure 150 is a single layer structure. In other embodiments, the passivation structure 150 is a multi-layer structure.

Referring to FIG. 2A , the passive electrical components 110 a and 110 b are disposed over the passivation structure 150 . In some embodiments, an adhesive material, e.g., epoxy (not shown) is disposed between the respective passive electrical components 110 a and 110 b and the passivation structure 150 . The adhesive material is applied to facilitate the physical connection between the passive electrical components 110 a and 110 b and the passivation structure 150 .

Referring again to FIG. 2A , the passive electrical components 110 a and 110 b are electrically coupled with the respective electrical pads 140 a - 140 d . For example, the passive electrical component 110 a is electrically coupled with the electrical pads 140 a and 140 b through wires 161 a and 161 b , respectively. The passive electrical component 110 b is electrically coupled with the electrical pads 140 c and 140 d through wires 161 c and 161 d , respectively. In some embodiments, the wires 161 a and 161 b are electrically coupled with opposite nodes of the passive electrical component 110 a , and the wires 161 c and 161 d are electrically coupled with opposite nodes of the passive electrical component 110 b . In some embodiments, the wires 161 a - 161 d are made of at least one material such as gold, copper, aluminum, tin, silver, lead, other metallic materials, and/or any combinations thereof.

Referring to FIG. 2A , the package system 100 can be disposed over a printed circuit board (PCB). As noted, the passive electrical components 110 a and 110 b are disposed over the passivation structure 150 . The passive electrical components 110 a and 110 b do not consume any space of the PCB, such that more space on the PCB can be available to accommodate other circuitries. Little or no footprint of the passive electrical components 110 a and 110 b is left on the PCB.

As the passive electrical components 110 a and 110 b are disposed over the passivation structure 150 and electrically coupled with the active circuitry 120 through the electrical pads 140 a - 140 d , the electrical communication speed between the passive electrical components 110 a and 110 b and the active circuitry 120 is increased. In some embodiments, the passive electrical components 110 a and 110 b are SMD capacitors which are cheaper than discrete inductors that were used and disposed on a PCB. In contrast, in accordance with one or more of the embodiments, the cost of manufacturing discrete inductors disposed on a PCB is expensive and the discrete inductors occupy a large area of the circuit board, which can minimize the space available to accommodate other circuitries or to reduce the size of the package system 100 . The cost of manufacturing the package system 100 can be desirably reduced.

FIG. 2B is a schematic cross-sectional view of a second exemplary package system taken along section line A-A of FIG. 1 . Items of the package system 100 in FIG. 2B that are the same or similar items of the package system 100 in FIG. 2A are indicated by the same reference numerals. In FIG. 2B , the package system 100 includes electrical connection structures 166 a - 166 d disposed in the respective openings of the passivation structure 150 . In some embodiments, the electrical connection structures 166 a - 166 d each are a via plug, a contact plug, a damascene structure, a dual damascene structure, a metallic region, a metallic line, a metallic slat, or one of other electrical connection structures. In some embodiments, the via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, and metallic slats are made of at least one material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other proper conductive materials, and/or any combinations thereof.

Referring to FIG. 2B , at least one electrical pad, e.g., electrical pads 170 a - 170 d are disposed over and electrically coupled with the electrical connection structures 166 a - 166 d , respectively. The electrical pads 170 a - 170 d are separated from each other. In some embodiments, the electrical pads 170 a - 170 d are made of at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other conductive materials, and/or any combinations thereof.

Referring again to FIG. 2B , the passive electrical component 110 a is disposed over and electrically coupled with the electrical pads 170 a and 170 b . The passive electrical component 110 b is disposed over and electrically coupled with the electrical pads 170 c and 170 d . In some embodiments, the electrical pads 170 a and 170 b are electrically coupled with opposite nodes of the passive electrical component 110 a , and the electrical pads 170 c and 170 d are electrically coupled with opposite nodes of the passive electrical component 110 b.

In some embodiments, adhesive materials 171 a and 171 b are optionally disposed between the passive electrical component 110 a and the passivation structure 150 and between the passive electrical component 110 b and the passivation structure 150 , respectively. The adhesive material 171 a is disposed between and separated from the electrical pads 170 a and 170 b . The adhesive material 171 b is disposed between and separated from the electrical pads 170 c and 170 d . In some embodiments, the adhesive materials 171 a and 171 b can include a material such as a thermosetting resin to facilitate connection between the passive electrical components 110 a and 110 b and the passivation structure 150 .

It is noted that the configuration of the electrical connection structures 166 a - 166 d , the electrical pads 170 a - 170 d , the adhesive materials 171 a and 171 b , and/or the passive electrical components 110 a and 110 b described above in conjunction with FIG. 2 B is merely exemplary. The scope of this application is not limited thereto. In some embodiments, the electrical connection structures 166 a - 166 d continuously extend over a surface 150 a of the passivation structure 150 .

FIG. 2C is a schematic cross-sectional view of a third exemplary package system taken along section line A-A of FIG. 1 . Items of the package system 100 in FIG. 2C that are the same or similar items of the package system 100 in FIG. 2A are indicated by the same reference numerals. In FIG. 2C , the package system 100 includes electrical connection structures 175 a - 175 d disposed in the respective openings of the passivation structure 150 and continuously extend above the surface 150 a of the passivation structure 150 . In some embodiments, the electrical connection structures 175 a - 175 d each are a via plug, a contact plug, a damascene structure, a dual damascene structure, a metallic region, a metallic line, a metallic slat, or one of other electrical connection structures. In some embodiments, the via plugs, contact plugs, damascene structures, dual damascene structures, metallic regions, metallic lines, and metallic slats are made of at least one material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other proper conductive materials, and/or any combinations thereof.

Referring to FIG. 2C , the passive electrical component 110 a is disposed between and electrically coupled with the electrical connection structures 175 a and 175 b . The passive electrical component 110 b is disposed between and electrically coupled with the electrical connection structures 175 c and 175 d . In some embodiments, the electrical connection structures 175 a and 175 b are electrically coupled with opposite nodes of the passive electrical component 110 a , and the electrical connection structures 175 c and 175 d are electrically coupled with opposite nodes of the passive electrical component 110 b.

In some embodiments, the top surface of the passive electrical component 110 a is substantially leveled with the top surfaces of the electrical connection structures 175 a and 175 b . In other embodiments, the top surface of the passive electrical component 110 a is higher or lower than the top surfaces of the electrical connection structures 175 a and 175 b.

It is noted that though the package system 100 of FIGS. 2A-2B shows that the passive electrical components 110 a and 110 b are disposed directly on or over the passivation structure 150 , the scope of this application is not limited thereto. In some embodiments, other dielectric layers and/or materials are disposed between the passive electrical components 110 a and 110 b and the passivation structure 150 . In other embodiments, at least one interposer and/or additional die is disposed between the passive electrical components 110 a and 110 b and the passivation structure 150 . In still other embodiments, at least one interposer and/or additional die is disposed over the passive electrical components 110 a and 110 b.

In a first embodiment of the application, a package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.

In a second embodiment of this application, a package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has a first opening exposing a first electrical pad and a second opening exposing a second electrical pad. A first electrical connection structure and a second electrical connection structure are disposed in the first and second openings, respectively. A first surface-mount device (SMD) capacitor is disposed over the passivation structure. The first SMD capacitor is electrically coupled with the first and second electrical pads through the first and second electrical connection structures, respectively.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.