Bi-directional switch using series connected N-type MOS devices in parallel with series connected P-type MOS devices

This application claims the benefit, under 35 U.S.C. §119(e), of U.S. Provisional Patent Application No. 61/613,269and U.S. Provisional Patent Application No. 61/613,260 , both filed on Mar. 20, 2012, the contents of which are hereby incorporated by reference in its entirety. This application is also related to U.S. patent application Ser. No. 13/674,250 , filed Nov. 12, 2012.

Two NDMOS devices can be connected in series with their sources connected to each other and their gates connected to each other to make an NDMOS switch. Two PDMOS devices can also be connected in series with their sources connected to each other and their gates connected to each other to make a PDMOS switch. However, no switches have been formed using a combination of series connected NDMOS and series connected PDMOS devices. The reason why these two types of series connections have not been combined into a single switch is that in a conventional DMOS manufacturing process one of the device types has to have its source tied to the silicon substrate. For example in a P-type silicon substrate every NDMOS device has to have its source connected to the substrate. Similarly, in an N-type silicon substrate every PDMOS device has to have its source connected to the substrate. Therefore, a plurality of processes (e.g., a conventional NDMOS process plus a conventional PDMOS process) would be required in order to form a single switch having both types of series connections—which would be costly and time consuming. Since both types of series connections would not have been used together, a parallel configuration of both types of series connections would also not have been considered feasible or practical.

A new process has been developed which allows the source of a DMOS device to be at a different potential from the substrate, thereby allowing the series connection of both NDMOS and PDMOS in the same process. Circuits that include both types of series connections, such as the bi-directional switch of the present invention, are therefore possible to manufacture with less expense.

In one embodiment, a bi-directional switch is formed using a pair of series connected N-type MOS devices connected in parallel with a pair of series connected P-type MOS devices.

In a second embodiment, the bi-directional switch is a DMOS switch including a pair of series connected NDMOS devices connected in parallel with a pair of series connected PDMOS devices. One advantage of the bi-directional DMOS switch in accordance with the second embodiment is that the switch allows rail-to-rail operation without the need to use a charge pump, e.g., a charge pump to generate the gate voltage for a conventional DMOS switch. To support rail-to-rail operation, the charge pump generates a supply voltage that exceeds the maximum allowed input signal in order to keep the conventional DMOS switch turned on. Disadvantages of using the charge pump in this manner include high supply current and slow switching speed. The DMOS switch of the present invention would avoid these disadvantages.

FIG. 1 shows a schematic of a bi-directional switch circuit according to an example embodiment of the present invention.

The present invention relates to a bi-directional switch that is formed using a pair of series connected N-type MOS devices connected in parallel with a pair of series connected P-type MOS devices. In one embodiment, the MOS devices are DMOS devices. The switch is capable of being operated as a rail-to-rail switch, meaning that the input to the switch can vary between the value of a positive supply rail (LHI) and the value of a negative supply rail (VSS) without adversely affecting switch operation. LHI and VSS are not shown in the drawings and represent the power supplies to a circuit that generates the input to the switch. For example, LHI and VSS may supply an amplifier circuit that boosts the voltage level of an input signal before the input is sent to the switch.

FIG. 1 shows a schematic of a DMOS switch 10 according to an example embodiment of the present invention. The switch 10 includes a pair of series connected PDMOS devices mp 29 /mp 30 and a pair of series connected NDMOS devices mn 47 /mn 48 . While the example embodiments are described with respect to series connections of two MOS devices, it is possible for more than two MOS devices to be connected in series. However, the use of more than two series connected MOS devices is neither required nor necessarily preferred from the perspective of manufacturing cost and performance. Each of the series connections is formed between an input/output (I/O) point s 1 and an I/O point d 1 . The sources of mp 29 and mp 30 are connected together. The gates of mp 29 and mp 30 are also connected together. Similarly, the sources of mn 47 and mn 48 are connected together, as are the gates of mn 47 and mn 48 . The DMOS devices mp 29 /mp 30 /mn 47 /mn 48 may be formed using an isolated process in which isolation regions are included in the silicon substrate of each DMOS device to allow the source regions of the DMOS devices to be at a differential potential from the substrate, e.g., at any voltage between LHI and VSS. Rail-to-rail operation is therefore made possible because the sources are no longer tied to the substrate potential.

The switch 10 is bi-directional, meaning s 1 and d 1 can be used for input as well as output. The devices mp 29 /mp 30 /mn 47 /mn 48 are high voltage DMOS devices, suitable for use with power circuits and other circuits that operate with voltages beyond those typically found in CMOS circuits. As shown in FIG. 1 , the drains of mp 29 and mp 48 are connected together at s 1 . The drains of mp 30 and mn 47 are connected together at d 1 . In this manner, the series DMOS devices are connected in parallel between the input and output of the switch 10 .

The switch 10 may also include one or more protection devices that protect the DMOS devices from high voltages. For example, the switch 10 may include Zener diodes d 36 /d 37 , which operate to restrict the maximum gate-to-source voltage (Vgs) of mn 47 /mn 48 and mp 29 /mp 30 , respectively. The diode d 36 is connected between the common gate of mn 47 /mn 48 and the common source of mn 47 /mn 48 . The diode d 37 is connected between the common gate of mp 29 /mp 30 and the common source of mp 29 /mp 30 .

The switch 10 can be operated by turning the devices mp 29 /mp 30 /mn 47 /mn 48 on and off simultaneously through their respective gate inputs. The gates of mp 29 /mp 30 are labeled “pgate” and the gates of mn 47 /mn 48 are labeled “ngate”. The switch 10 may also be controlled based on signals at the common sources of the DMOS devices. Specifically, a signal “midp” is obtained from the node corresponding to the common source of mp 29 /mp 30 and a signal “midn” is obtained from the node corresponding to the common source of mn 47 /mn 48 . The functions of midp and midn are described below.

DMOS devices have a restriction on the gate-to-source voltage Vgs. The maximum allowable Vgs voltage varies depending on the manufacturing process used to make the DMOS device. In one embodiment, Vgs has a maximum allowable voltage of approximately 5.5 V. In the circuit of FIG. 1 , this means that the gate voltages of the DMOS devices must be referenced to the source voltages (midp and midn, the values of which will vary depending on the input) and controlled so as to limit Vgs to the maximum allowable voltage. In the switch 10 , the source voltages track the external voltage applied to the drains of the DMOS devices (s 1 or d 1 ) because of the inherent parasitic diodes that exist within the DMOS devices. For the NDMOS devices, the anode is connected to the common source (midn) and the cathode is connected to s 1 for mn 48 and to d 1 for mn 47 . For the PDMOS devices, the anode is connected to the drain, which is connected to s 1 for mp 29 and to d 1 for mp 30 . The cathode of the diode for the PDMOS devices is the common source (midp).

According to one embodiment, to turn on the PDMOS devices mp 29 /mp 30 , pgate must be a minimum of Vtp (the threshold voltage of the PDMOS devices) lower than midp and a maximum of 5.5 V lower than midp. In the same embodiment, to turn on the NDMOS devices, ngate must be a minimum of Vtn (the threshold voltage of the NDMOS devices) higher than midn and a maximum of 5.5 V higher than midn. If the turn-on threshold voltage for the devices Vt=Vtp=Vtn is approximately 1.2 V, a DC gate voltage of midp−5 V may be used to safely turn on the PDMOS devices while keeping within the 5.5 V limit for Vgs. Similarly, for the NDMOS devices, a gate voltage of midn+5 V may be used to safely turn on the NDMOS devices. Therefore, the drain-to-source voltage Vds can be a high voltage (e.g., Vds=80 V) while allowing the switch 10 to be turned on using a much smaller voltage (e.g., Vgs=5.5 V).

While the actual limits on Vgs may be higher or lower depending on the process used in making the DMOS devices, Vgs is preferably maintained such that it is always substantially lower than the 5.5 V maximum). The reason 5 V Vgs is used in the embodiment described above is to get the lowest on-resistance (Ron) possible. As Vgs is increased, Ron decreases. Thus, although 1.2 V would be enough Vgs to turn the devices on, performance would be significantly reduced because Ron would be high, thereby reducing the magnitude of the signal that gets passed to the output s 1 /d 1 . In sum, because midp/midn track the source voltages, the gate voltages pgate/ngate need to track midp/midn in order to keep the devices turned on.

The PDMOS devices mp 29 /mp 30 and the NDMOS devices mn 47 /mn 48 may be turned on or off simultaneously, i.e., all four devices are either all on or all off at any given time. To turn the devices off, Vgs of 0 V may be applied, e.g., by tying the gates to midp/midn. Specifically, midp is tied to pgate and midn is tied to ngate. When the switch 10 is off midp and midn will likely be at different voltages (i.e., midp will be the most positive voltage of s 1 or d 1 and midn will be the most negative voltage of s 1 or d 1 ).

In the preceding specification, the present invention has been described with reference to specific example embodiments thereof. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the present invention as set forth in the claims that follow. For example, in the example embodiments described above, DMOS devices were used because DMOS devices allow for high supply voltages. Thus, the switch 10 is especially suited for use in any application that involves use of a high voltage (e.g., a voltage from LHI to VSS of 80 V or a voltage from s 1 to d 1 of 80 V) or that requires a fault tolerant switch. However, in alternative embodiments, CMOS devices (e.g., N-type MOS in combination with P-type MOS) may be used instead of DMOS devices. The switch 10 may also be used in place of a conventional switch in low power applications, since it is capable of performing the same switching functions. The embodiments described herein may be presented combined with each other in various combinations. The specification and drawings are accordingly to be regarded in an illustrative rather than restrictive sense.