High performance class AB operational amplifier

This application is a translation of and claims the priority benefit of Italian patent application number MI2011A001832, filed on Oct. 7, 2011, entitled High Performance Class AB Operational Amplifier, which is hereby incorporated by reference to the maximum extent allowable by law.

The present invention relates to a high performance class AB operational amplifier.

The design of high-accuracy analogue circuits is becoming a difficult task with the scaling down of supply voltages and transistor channel lengths of the current mixed-signal integrated circuits. Most of these circuits require the use of high performance active cell: the operational amplifier (OpAmp). Furthermore, some low-IF transceivers make use of complex filters which require operational amplifier with a very high gain-bandwidth product in order to have enough loop gain at the higher band limit. Ultra low power circuit imposes a current reduction in order to increase the battery life-time in mobile handsets. Unfortunately, the bandwidth depends on the technology and the current used in the OpAmp output stage and hence the only way to reduce the current consumption is to reduce the complexity/consumption of the circuits around the OpAmp such as bias, common mode feed-back, start-up circuit. Designers are continuously working toward tradeoff solutions between gain, input/output swings, speed, power consumption, noise, etc.

The class-AB output stage topology allows driving a large load capacitor with a small output stage bias current. Furthermore, it gives a boost in the Gain Bandwidth product (GBW). Despite to its property, the most important problem designing class AB OpAmps is the accurate control of the output current which depends on process and supply voltage variations. To solve this problem it is necessary to introduce control circuits.

An ideal circuit to implement a class AB output stage is shown in FIG. 1 . The circuit comprises an input stage comprising a differential pair of PMOS transistors M 1a , M 1b having a differential input signal at the input terminals IN P , IN M . The drain terminals of the transistor of the differential pair are connected to the output terminals OUT P , OUT M by means of the compensation network constituted of a series of a capacitor C c and a resistance R c . The output terminals OUT P , OUT M belonging to two output stages each one comprising a couple of transistor PMOS M 7a , M 7b and NMOS M 6a , M 6b having the drain terminal in common and connected to the output terminals OUT P , OUT M and the two level shifter Δv/2 connected between the output terminals of the differential pair and the gate terminals of the transistor PMOS M 7a , M 7b and NMOS M 6a , M 6b of the couples.

The biasing of the differential pair is performed by means of the transistors NMOS M 2a , M 2b having the gate terminal connected to the bias voltage VB N and the source terminals of the differential pair transistors connected to the drain terminal of a PMOS transistor M 3 having the gate terminal connected to a bias voltage VB p and the source terminal connected to the supply voltage Vdd as the source terminals of the transistors M 7a , M 7b ; in this way a bias current Iss/2 flows in each branch of the differential pair.

The circuit in FIG. 1 allows to control the bias current and transfer the signal to both the NMOS and PMOS transistor of the output stage using two level shifter Δv/2.

A practical implementation of the circuit in FIG. 1 is shown in FIG. 2 . The two level shifter Δv/2 of the output stages are implemented by means of a PMOS and a NMOS transistor arranged in series M 4a , M 5a and M 4b , M 5b and connected between the supply voltage Vdd and ground (GND). The gate terminals of the transistors M 5a , M 5b are connected to the output terminals of the differential pair while the gate terminals of the transistors M 4a , M 4b are connected to the bias voltage VB p .

The circuit topology in FIG. 2 assures the best performance in terms of GBW, power consumption and output voltage swing. Unfortunately, this topology has many drawbacks to be solved; the output-stage current is not controlled and depends on the process, mismatch of the MOS transistors and on the supply voltage. Furthermore, this topology is not at low voltage. The minimum supply voltage which can be used depends on the MOS transistors threshold V TH and is V THN +2V THP where V THN is the threshold of the NMOS transistor while V THP is the threshold of the PMOS transistor.

Another circuit topology used is shown in FIG. 3 . This circuit solution comprises the use of a circuit 1 to control the output current Tout of the class AB output stage in FIG. 2 ; FIG. 3 shows only a part of the circuit in FIG. 2 which is relative to the input IN M and the output OUT M . The gate terminal of the transistor M 4 is not connected with the bias voltage VB P but with the circuit 1 , more precisely the gate terminal of the transistor M 4 is connected with the gate terminal and the drain terminal of a PMOS transistor M 4r and with the gate terminal of a PMOS transistor M 3 , so that the transistor M 4r and M 3r form a current mirror. Another current mirror comprises the transistor M 1r and M 6r adapted to mirror the bias current I B in the PMOS transistor M 7r having the gate terminal connected with the drain terminal of the transistor M 3r and with the source terminal of a PMOS transistor M 5r the drain terminal of which is connected to ground GND and the gate terminal is connected with the gate terminal of the transistors M 1r and M 6r . Loop consists of transistors M 3r , M 7r , M 2r and M 4r . The gate-source voltage of the transistor M 5r will be adjusted corresponding to the currents flowing through the transistors M 7r and M 6r The current flowing through the transistor M 5r is copied in the transistor M 4 by the transistor M 3r and the gate-source voltage of the transistor M 5 is adjusted to a right level forcing the output stage current to the controlled level.

The circuit in FIG. 3 is known from: H. A. Aslanzadeh, S. Mehrmanesh, M. B. Vahidfar, A. Q. Safarian, “A low power 25 Ms/s 12-bit pipelined analog to digital converter for wireless applications,” IEEE 2003.

This solution is not suitable for very low current consumption application; in the case of low bias current the output current depends on the process variation of the transistor and the performances of the class AB output stage of the operational amplifier are reduced.

In view of the state of the art, the object of the present invention is to provide a high performance class AB operational amplifier which overcomes the above-mentioned drawbacks.

According to the present invention, this object is achieved by means of a class AB operational amplifier comprising an input stage, an output stage and a level shifter stage adapted to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, a control circuit of the level shifter stage, characterized in that the control circuit comprises at least one transistor differential pair having differential input terminals, said control circuit being configured so that the differential voltage at the differential terminals of the transistor differential pair controls the level shifter stage.

The features and advantages of the present invention will become apparent from the following detailed description of an embodiment thereof, illustrated only by way of non-limitative example in the annexed drawings, in which:

FIG. 1 shows an ideal circuit scheme of a class AB operational amplifier output stage;

FIG. 2 shows a circuit implementation of the circuit scheme in FIG. 1 ;

FIG. 3 shows a circuit implementation of the circuit scheme in FIG. 1 ;

FIG. 4 shows a class AB operational amplifier according to the present invention;

FIGS. 5 and 6 are time diagrams of the gain and phase of the circuit in FIG. 4 deriving from simulations; and

FIG. 7 shows montecarlo simulations of the output stage current of the class AB operational amplifier in FIG. 4 .

FIG. 4 shows a class AB operational amplifier according to the present invention. The operational amplifier comprising an input stage 10 , an output stage 11 , a level shifter stage 12 adapted to control the bias current of the output stage and to transfer the signal from the input stage to the output stage, a control circuit 13 of the level shifter stage. Specifically, FIG. 4 shows one part of the class AB operational amplifier according to the present invention which comprises two symmetrical parts for each branch of the input stage that is two parts identical to each other.

The input stage 10 comprising a differential pair of transistors M 1a , M 1b , preferably PMOS transistor, having a differential input signal at the input terminals IN P , IN M and a common node. The input stage 10 , similar to the input stage 1 in FIG. 1 , has a bias current Iss/2 flowing through the transistor M 1a , M 1b .

The output stage 11 comprises a couple of a first M 6 and a second M 7 output transistors, in series to each other, and arranged between a first voltage reference Vdd and a second voltage reference GND and being interconnected at an output terminal OUT of the operational amplifier; the first output transistor has a control terminal connected to an output terminal of the input stage 10 .

The level shifter stage 12 comprises a couple of a first M 5 and a second M 9 intermediate transistors, connected in series to each other by means of an impedance, that is the parallel of a resistance R and a capacitor C, and coupled between a first voltage reference Vdd and a second voltage reference GND; specifically, the transistors of the level shifter stage 12 are MOS transistors and the source terminal A of the first transistor M 5 is coupled with the drain terminal B of the second transistor M 9 by means of the parallel of the resistance R and the capacitor C. The first intermediate transistor M 5 has the control terminal connected with one output terminal of the input stage 10 and the second intermediate transistor M 9 has the output terminal connected with the control terminal of the second output transistor M 7 ; the second intermediate transistor M 9 has the control terminal connected to an output terminal of a control circuit 13 . The second intermediate transistor acts as a current generator.

The control circuit 13 comprises at least one transistor differential pair M 8a , M 8b having a differential input terminals B′ and A′. The differential voltage V A′ −V B′ , applied at the input terminals A′ and B′ controls the level shifter stage 12 . In fact the level shifter stage 12 controls the output quiescent current lout of the output stage 11 of the operational amplifier by means of the voltage difference between the voltages at the terminals A and B; the control circuit 13 is configured so that the differential voltage V A′ −V B′ . is equal to the differential voltage V A −V B applied at the terminals A and B. Particularly, the level shifter stage 12 fixes the voltage V A while the voltage V B is varied by the control circuit 13 .

The control circuit 13 comprises replica circuits based on transistors M 7r , M 6r and M 5r . The term “replica” is used herein to refer to a copy or duplicate of an original, which may be of different scale to the original. Preferably, the transistors M 7r , M 6r and M 5r are a scaled version of transistors M 7 , M 6 and M 5 respectively. The scaling value depends on the current ratio desired between transistors M 5 and M 5r =M 5 /k, M 6 and M 6r =M 6 /n, M 7 and M 7r =M 7 /n. This ratio of current in the stages 10 , 11 and 12 and in the replica-circuit branches is configured to reduce the current consumption of the control circuit 13 .

The control circuit 13 comprises circuit branches 14 , 15 connected with the input terminals B′, A′ of the differential pair M 8a , M 8b ; the circuit branches 14 , 15 are replica circuits of the respective circuit branches which are connected with the respective terminals B and A and which are formed by the transistor M 7 and M 5 , M 6 among the output stage 11 and the level shifter stage 12 .

The currents of the transistors M 7r , M 6r , M 6r and M 5r are fixed through current sources to a scaled value of the desired current flowing through the transistors M 7 , M 6 and M 5 . This allows to evaluate the desired voltage on the node A and B with process and temperature variations. The evaluated value is available at the node A′ and B′.

The control circuit 13 comprises first and second circuit branches 14 , 15 respectively formed by the transistor M 7r wherein the bias current Ioutr flows, and by the transistor M 6r wherein the bias current Ioutr flows and the transistor M 5r having the gate terminal connected with the gate terminal and with the drain terminal of the transistor M 6r . The drain and source terminals of the transistors M 7r , M 5r are connected to the terminals of the differential pair M 8a , M 8b so as the differential voltage V A′ −V B′ is proportional to the bias current Ioutr.

A transistor M 9r forms a mirror with the transistor M 9 of the level shifter stage. The transistor M 9r has the gate and the drain terminals connected with the drain terminal of the transistor M 8a ; another transistor M 9r has the gate and the drain terminals connected only with the drain terminal of the transistor M 8b .

The differential pair M 8a , M 8b compares the voltages V A′ . and V B′ and change the value of current in the transistor M 9r from I Br to the value I Br −ΔI with ΔI=(V A′ −V B′ )/R r . This current is mirrored in the transistor M 9 with a mirror factor k. The current flowing through M 9 is k•(I Br +ΔI). If the currents I B and I Br are related by I B =k•I Br , an extra current k•ΔI flows through the resistor R and produces a variation k•ΔI•R between the voltage of the node A and B, that is V A −V B =k•ΔI•R=k•R•(V A′ −V B′ )/R r . If the relation chosen between R and R r is R r =k•R then it has V A −V B =V A′ −V B′ ; the control circuit 13 guarantees at the node A and B the voltage which is necessary in order to have the desired current Iout=n•Ioutr in the output stage M 7 −M 6 with process and temperature variations, that is each variation of the current Ioutr determines a variation of the current lout of the output stage 11 of the operational amplifier in class AB.

Since the transistors M 8a , M 8b are configured as follower transistors, the voltage difference at the terminals of the resistance R r is the voltage difference V A ′−V B′ . The voltage V A′ is given by the sum of the gate-source voltages of the transistors M 6r and M 5r , that is

V A ′ =  V T p  + I Br K p ⁡ ( W L ) 5 ⁢ r + V Tn + I outr K n ⁡ ( W L ) 6 ⁢ ⁢ r

wherein V Tp is the voltage threshold to the PMOS transistor, V Tn is the voltage threshold to the NMOS transistor, W/L is the form factor and K p and K n are constants. The voltage V B′ is given by the difference between the supply voltage Vdd and the gate-source voltage of the transistor M 7r , that is

V B ′ = Vdd -  V Tp  - I outr K n ⁡ ( W L ) 7 ⁢ ⁢ r .

The voltage V A is given by the sum of the gate-source voltages of the transistors M 6 and M 5 , that is

V A ′ = V T N + I out K n ⁡ ( W L ) 6 +  V Tp  + I B K p ⁡ ( W L ) 5

and the voltage V B is given by the difference between the supply voltage Vdd and the gate-source voltage of the transistor M 7 , that is

V B ′ = Vdd -  V Tp  - I out K p ⁡ ( W L ) 7 .

Since V A −V B =V A′ −V B′ with R r =k•R and I B =k•I Br by selecting

( W L ) 5 = k ⁡ ( W L ) 5 ⁢ r ′ ⁢ ( W L ) 6 = n ⁡ ( W L ) 6 ⁢ r ⁢ ⁢ and ⁢ ⁢ ( W L ) 7 = n ⁡ ( W L ) 7 ⁢ r

it occurs lout=n×loutr.

This configuration has the advantage to eliminate the dependency of the output stage quiescent current on transistor process variation and supply voltage while controlling this current in an open loop manner which does not affect the frequency response and stability of the amplifier.

FIGS. 5 and 6 show the differential-mode open-loop gain G in decibel and the phase in degrees of the operation amplifier in FIG. 4 when it is connected in unity gain feed-back with a current consumption of 150 microampere, a power supply of 1.2 V and a load capacitor of 100 fF single-ended. These curves show a perfect two pole system. The operational amplifier exhibits a DC gain G of 50 dB and a unity-gain frequency of 500 MHz and 60 degree of phase margin.

FIG. 7 shows the montecarlo simulations with process and temperature variation; in said simulations the number of cases n is in ordinate and the current lout (in microampere) is in abscissa, with the total number of cases equal to 100, at 100° C., 27° C. and −40° C. The montecarlo simulations show a very accurate control of the output-stage current.

As above mentioned FIG. 4 shows one part of the class AB operational amplifier according to the present invention which comprises two symmetrical parts for each branch of the input stage, that is two parts identical to each other and wherein each one of two parts includes the circuits 11 , 12 and 13 shown in FIG. 4 .

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.