Control integrated circuit of a switch power supply and a switch power supply using the same

This application claims priority under 35 U.S.C. §119 of Chinese Patent Application No. 201110215457.0, filed on Jul. 29, 2011, the content of which is incorporated herein by reference in its entirety.

Exemplary embodiments of the present disclosure relate generally to a control integrated circuit, and more particularly, to a control integrated circuit of a switch power supply and a switch power supply using the same.

Almost all household appliances require using low voltage direct current (DC) power supplies as the appliances' main power supplies or the controller power supplies. But city power grids can only provide either 220V or 110V alternating current (AC) power supply because of the inherent voltage transmission loss problem. Therefore, highly efficient and cost-effective AC-DC converters are needed. Traditional AC-DC converters are usually linear converters, which have several drawbacks including their large volume, heavy weight, low conversion efficiency and no-longer obvious cost advantage. Thus, they are being phased-out in the industry. Nowadays, switch power supply converters become the mainstream AC-DC conversion devices. In order to meet the accuracy and isolation safety requirements, switch power supply converters having secondary feedback control are usually used.

Consistent with the disclosed embodiments, there is provided a control integrated circuit for controlling a switch power supply. The control integrated circuit comprises: a voltage collecting module, configured to collect a feedback voltage based on an output voltage of the switch power supply; an error amplifying module, configured to compare the feedback voltage with a reference voltage and generate an error voltage; a time collecting module, configured to obtain a degaussing time signal based on the feedback voltage; and a constant voltage and current module, configured to collect a peak current feedback signal of a switch transistor, generate a control signal based on the error voltage, the degaussing time signal and the peak current feedback signal, wherein the control signal is for controlling an operating frequency and a duty ratio of the switch transistor, and control the switch transistor according to the control signal.

Consistent with the disclosed embodiments, there is provided a switch power supply. The switch power supply comprises: a control integrated circuit for controlling a switch power supply as disclosed above; an input filter and rectification module, configured to filter a first alternating current (AC) voltage for obtaining desired frequencies and convert the first alternating current (AC) voltage to a first direct current (DC) voltage; a primary winding, configured to convert the first DC voltage to an electromagnetic signal, wherein the conversion is controlled by the switch transistor; a power supply module, configured to provide a power supply voltage to the control integrated circuit; a primary side feedback module, configured to divide the power supply voltage and provide the divided power supply voltage to the control integrated circuit; a primary collecting module, configured to collect the peak current feedback signal; a secondary winding, configured to convert the electromagnetic signal to an electric signal and generate a second AC voltage corresponding to the electric signal; an output rectification module, configured to convert the second AC voltage to a second DC voltage; a voltage regulating module, configured to store the energy provided by the output rectification module and provide output power for stabilizing an output DC voltage of the switch power supply when the switch transistor is turned off; and a dummy load module, configured to consume energy generated by the secondary winding when the switch power supply carries no load.

The error amplifying module compares the feedback voltage collected by the voltage collecting module and a reference voltage, and generates an error voltage, which can be used to determine the load condition of the switch power supply. Consequently, based on the load condition of the switch power supply, the degaussing time signal, and the switch transistor's peak current feedback signal, the frequency and duty ratio of the control signal can be adjusted for generating a constant voltage and current output. In addition, the operating frequency of the control integrated circuit can be reduced when the system has a decreased load condition. Accordingly, the standby power consumption can be reduced because the switching loss of the switch power supply is reduced.

Having thus described exemplary embodiments of the present disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

FIG. 1 illustrates a circuit diagram of a prior art switch power supply;

FIG. 2 illustrates a block diagram of an exemplary control integrated circuit (IC) for a switch power supply according to an exemplary embodiment;

FIG. 3 illustrates a block diagram of an exemplary embodiment of a constant voltage and current module shown in FIG. 2 ;

FIG. 4 is an exemplary diagram illustrating the variation of the control IC's operating frequency (fosc) and peak primary winding current (Ip) in relation to load current (Iout);

FIG. 5 illustrates an exemplary circuit diagram corresponding to a Pulse Width Modulation (PWM) mode;

FIG. 6 illustrates an exemplary circuit diagram corresponding to a Pulse Frequency Modulation (PFM) mode or a BURST mode;

FIG. 7 illustrates a timing diagram of an exemplary constant voltage and current module operating under the PFM/BURST mode, corresponding to the circuit shown in FIG. 6 ;

FIG. 8 illustrates a block diagram of an exemplary switch power supply according to an exemplary embodiment;

FIG. 9 illustrates a circuit diagram of an exemplary switch power supply corresponding to the block diagram shown in FIG. 8 .

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. It is readily appreciated by those having ordinary skill in the art that the presently claimed subject matter may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

FIG. 1 shows a prior art switch power supply circuit with a feedback control. An AC power supply voltage passes through a full-wave rectifier (i.e., diodes D 1 -D 4 ), which converts the AC power supply voltage to a high DC voltage. The DC voltage is stored in a capacitor C 1 . The operating power of an control integrated circuit (IC) is provided through a resistor R 2 and a capacitor C 2 . At an output side, an output voltage is divided by resistors R 6 and R 7 , amplified by a regulator TL 431 and transmitted to the voltage sampling terminal of the control IC by an optocoupler H 1 . Based on the sampled output voltage, the control IC adjusts the conducting time and operating frequency of a switch transistor Q 1 in order to adjust the energy stored in a primary winding in a present cycle. As a result, a closed-loop negative feedback system is formed for stabilizing the output voltage. This type of switch power supply circuit, however, has high standby power consumption because the required operating current of the optocoupler H 1 and the regulator TL 431 are both above 1 mA.

FIG. 2 illustrates a block diagram of an exemplary control integrated circuit (IC) of a switch power supply according to an exemplary embodiment. The control integrated circuit connects to a switch transistor of a switching power supply and includes: a voltage collecting module 112 , configured to collect a feedback voltage based on an output voltage of the switch power supply; an error amplifying module 113 , configured to compare the feedback voltage with a reference voltage and generate an error voltage; a time collecting module 114 , configured to obtain a degaussing time signal based on the feedback voltage; and a constant voltage and current module 115 , configured to collect a peak current feedback signal of a switch transistor, generate a control signal based on the error voltage, the degaussing time signal and the peak current feedback signal, wherein the control signal is for controlling an operating frequency and a duty ratio of the switch transistor, and control the switch transistor according to the control signal.

A degaussing time signal Tds generated by the time collecting module 114 is obtained based on the feedback voltage, which is collected by the voltage collecting module 112 and determined based on the output voltage of the switch power supply. As will be discussed in association with FIG. 9 , when a switch transistor Q 1 is turned on, an auxiliary winding Nd couples with a primary winding Np of a transformer and the feedback voltage collected by the voltage collecting module 112 is a negative voltage. When the switch transistor Q 1 is turned off and a diode D 7 is turned on, the output voltage of a secondary winding Ns of a transformer is the output voltage of the switch power supply, and the auxiliary winding Nd couples with the secondary winding. Thus, the feedback voltage is a positive voltage. When the switch transistor is turned on and the diode D 7 is turned off, the feedback voltage is an oscillatory voltage. Accordingly, when the voltage collecting module 112 collects the feedback voltage, the degaussing time signal Tds (i.e., the diode's turn-on time) is also obtained.

The error amplifying module 113 compares the feedback voltage collected by the voltage collecting module 112 and a reference voltage (e.g., a 2V voltage), and generates an error voltage, which can be used to determine the load condition of the switch power supply. Consequently, based on the load condition of the switch power supply, the degaussing time signal, and the switch transistor's peak current feedback signal, the frequency and duty ratio of the control signal can be adjusted to generate a constant voltage and current output. In addition, the operating frequency of the control IC can be reduced when the system has a decreased load condition. Accordingly, the standby power consumption can be reduced because the switching loss of the switch power supply is reduced.

As shown in FIG. 2 , VDD is a power supply terminal; GND is an electrical ground; COMP is a compensation terminal; CS is a collecting terminal of the peak current feedback signal; INV is a collecting terminal of the feedback voltage; and DRI is a driving terminal for driving the switch transistor.

In some exemplary embodiments, the control IC further comprises a compensating module 116 , configured to compensate the feedback voltage, which is collected by the voltage collecting module 112 , according to the error voltage generated by the error amplifying module 113 . Consequently, different voltage compensations can be obtained depending on different load conditions. When the load increases, the voltage compensation can increase correspondingly. The voltage compensation compensates the voltage loss in the conducting wire.

In some exemplary embodiments, the control IC further comprises a circuit starting module 111 , configured to generate an enable signal when the voltage of a power supply module is equal to or greater than a preset startup voltage and provide power to voltage collecting module 112 , error amplifying module 113 , time collecting module 114 and constant voltage and current module 115 ; wherein the constant voltage and current module 115 is configured to provide the control signal when receiving the enable signal. When the control IC powers on and the voltage of the power supply module starts to increase, the circuit starting module 111 resets the other modules of the control IC. When the voltage of the power supply module is equal to or greater than a preset value, the circuit starting module 111 generates the enable signal and the control IC starts to operate and generate the control signal, which controls the operation of the switching transistor.

In some exemplary embodiments, the control IC further comprises a high voltage to low voltage converting module 117 , configured to provide operating power and an enable signal to the low voltage part of the control IC based on the output voltage level of the power supply module; and a reference and bias module 118 , configured to provide a reference voltage and a bias voltage.

FIG. 3 illustrates a block diagram of an exemplary embodiment of the constant voltage and current module 115 shown in FIG. 2 . In FIG. 3 , the constant voltage and current module 115 comprises: a collecting unit 1151 , configured to collect the peak current feedback signal; a mode judging unit 1152 , configured to modulate a judging current according to the error voltage VEA; a mode controlling unit 1153 , configured to modulate a controlling current according to the error voltage VEA; a reference current unit 1154 , configured to generate a preset current; a pulse width modulating unit 1155 , configured to obtain a first comparison voltage VOCP (shown in FIG. 5 ) based on the controlling current that is superimposed with the preset current, and generate a turn-off pulse OFF for the control signal when the first comparison voltage VOCP equals the voltage of the peak current feedback signal VCS (shown in FIG. 5 ); and a frequency modulating unit 1156 , configured to generate a turn-on pulse ON for the control signal based on the judging current, the controlling current and the degaussing time signal Tds.

In FIG. 3 , when the pulse width modulating unit 1155 operates, the control IC enters the pulse width modulation (PWM) mode. When the frequency modulating unit 1156 operates, the control IC enters the pulse frequency modulation (PFM) mode. And the control IC enters the BURST mode (i.e., the hiccup mode or the skip-cycle mode) when both the pulse width modulating unit 1155 and the frequency modulating unit 1156 operate. Under the BURST mode, energy saving can be realized by periodic shielding of the output pulses under certain load conditions.

The output power P of the switch power supply equals U multiplied by I (i.e., P=U*I), where U is the output voltage and I is the output current of the switch power supply. Because the output power P is kept as a constant, when the system load increases, the output current I increases and thus the output voltage U decreases. Consequently, when the system load increases, the feedback voltage, which reflects the output voltage U and is collected by the voltage collecting module 112 shown in FIG. 2 , is far less than the reference voltage. As a result, the error amplifying module 113 shown in FIG. 2 generates a high voltage level. For example, the value of the output error voltage VEA of the error amplifying module 113 equals VDD. When VEA, as an input to the mode judging unit 1152 , is at the high voltage level, the mode judging unit 1152 maintains the judging current and provides the judging current to the frequency modulating unit 1156 . Moreover, the mode controlling unit 1153 provides a maximum control current to the pulse width modulating unit 1155 and stops providing current to the frequency modulating unit 1156 , so that the peak feedback voltage and the peak feedback current can be maintained. As a result, the peak current Ip of the primary winding can also be maintained and Tds/T is kept as a constant. Furthermore, according to a formula

Iout = 0.5 · NP NS · Tds T · Ip , ( 1 )

where NP is the number of turns of the primary winding and NS is the number of turns of the secondary winding, when the turns ratio NP/NS is a constant, the output current Iout of the switch power supply can be kept as a constant. Thus, if the output current Iout is a constant but the degaussing time signal Tds changes, the frequency modulating unit 1156 modulates the operating cycle T of the control IC, so that Tds/T is kept as a constant. In other words, because the operating cycle T is the inverse of the operating frequency fosc, the frequency modulating unit 1156 effectively modulates the operating frequency fosc. Accordingly, when the output current of the switch power supply is maintained, the control IC enters the PFM mode.

When the system load decreases, the feedback voltage, which reflects the output voltage U and is collected by the voltage collecting module 112 shown in FIG. 2 , can gradually approach the reference voltage input to the error amplifying module 113 shown in FIG. 2 . And the error voltage VEA, which is generated by the error amplifying module 113 , decreases gradually from VDD. When VEA is less than V 1 , a preset voltage value, the operating conditions of both the pulse width modulating unit 1155 and the frequency modulating unit 1156 are adjusted according to the value of the error voltage VEA. In other words, the pulse width modulating unit 1155 carries out pulse width modulation and the frequency modulating unit 1156 carries out pulse frequency modulation. As a result, the output voltage of the switch power supply is stabilized by means of system negative feedbacks. When the error voltage VEA decreases to V 2 , another preset voltage value, the control IC reaches its adjustment limit under the PWM mode and the PFM mode. Consequently, if the system load decreases further, the output voltage of the switch power supply increases further and the error voltage VEA decreases further. When VEA is less than a preset voltage V 4 , the mode judging unit 1152 modulates its output judging current and the control IC enters the BURST mode. When the control IC operates under the BURST mode, it can carry out further frequency division based on its minimum operating frequency. If, however, the system load stops decreasing and instead increases, the output voltage of the switch power supply decreases and the error voltage VEA increases. When VEA increases to be greater than a preset voltage V 3 , the control IC no longer operates in the BURST mode. A time delay exists between the voltage V 3 and the voltage V 2 . That is, there is a delay between the time VEA reaches V 2 and the time VEA reaches V 3 , and the values of the voltage V 1 , V 2 , V 3 , and V 4 decrease in the corresponding order.

FIG. 4 is an exemplary diagram illustrating the variation of the control IC's operating frequency (fosc) and peak primary winding current (Ip) in relation to load current (Iout). The shaded area in FIG. 4 indicates that the control IC operates under the BURST mode. The non-shaded area in FIG. 4 indicates that the control IC operates under the PWM mode and the PFM mode. When the control IC operates under the PWM mode and PFM mode (i.e., in the non-shaded area), the control IC's operating mode changes from PFM to PWM, and then to both PFM and PWM, corresponding to the decreasing of load. This type of control can better satisfy the dynamic performance requirements and also reduce the operating frequency under light load conditions. As a result, the control IC's operating efficiency can be improved. When the control IC operates under the BURST mode (i.e., in the shadowed area), the peak current Ip of the primary winding keeps at its minimum value, and the control IC's operating frequency changes to a half of the minimum operating frequency of the PFM mode. Thus, both the system switching loss and the dummy load loss can be reduced. Accordingly, the total power loss can be reduced when the switch power supply operates under the lightly loaded or unloaded conditions.

In some exemplary embodiments, as shown in FIG. 5 and FIG. 6 , the mode controlling unit 1153 includes a first current source connected with the pulse width modulating unit 1155 , being configured to increase a first output current I 1 when the error voltage VEA increases; and a second current source connected with the frequency modulating unit 1156 , being configured to increase a second output current I 2 when the error voltage VEA decreases, stop providing the second output current I 2 when the error voltage VEA equals a first preset voltage, and maintain the second output current I 2 when the error voltage VEA is less than a second preset voltage. When the first preset voltage equals VDD, the second output current I 2 equals zero. And when the error voltage VEA is less than V 4 , the second output current I 2 is kept unchanged.

FIG. 5 illustrates an exemplary circuit diagram corresponding to the PWM mode. In FIG. 5 , a reference current unit, such as the reference current unit 1154 shown in FIG. 3 , is represented by a constant current source, which generates a preset current I 0 . A pulse width modulating unit, such as the pulse width modulating unit 1155 shown in FIG. 3 , comprises a resistor R 0 , a capacitor C 0 and a comparator A 1 . One terminal of the resistor R 0 is connected to an output terminal of the first current source, an output terminal of the reference current unit, a terminal of the capacitor C 0 and a negative terminal of the comparator A 1 . The other terminal of the resister R 0 is connected to the other terminal of the capacitor C 0 and the electrical ground. A positive terminal of the comparator A 1 , which collects the peak current feedback signal VCS, connects to a collecting unit, such as the collecting unit 1151 shown in FIG. 3 . The negative terminal of the comparator A 1 receives a first comparison voltage VOCP, where VOCP=R 0 *(I 0 +I 1 ).

When the switch power supply is fully-loaded or overloaded, the output voltage of the switch power supply is small. Thus, the feedback voltage, which reflects the output voltage and is collected by the control IC, is also small and the error voltage VEA equals VDD. Controlled by the error voltage VEA, the first output current I 1 reaches its maximum value corresponding to the maximum value of the error voltage VEA. Consequently, the voltage VOCP reaches its maximum value as well and the peak current Ip of the primary winding, which is obtained based on the peak current feedback signal VCS, is maintained. When the peak current Ip of the primary winding is maintained, the time during which the first comparator A 1 generates the turn-off pulse OFF is a constant. And because the turn-on duty ratio of the switch transistor Q 1 can be obtained from the time it receives the turn-on pulse ON of the control signal to the time it receives the turn-off pulse OFF of the control signal, the turn-on duty ratio of the switch transistor Q 1 is maintained.

When the load of the switch power supply decreases to a certain degree, the output voltage of the switch power supply increases and the error voltage VEA decreases from VDD. The first output current I 1 also decreases corresponding to the decrease of the error voltage VEA. In turn, the turn-on duty ratio of the switch transistor Q 1 decreases. As a result, the output voltage of the switch power supply decreases and a negative feedback loop is formed. If, however, the load of the switch power supply increases, but to a degree that is less than a full load, the output voltage of the switch power supply decreases and the error voltage VEA increases correspondingly. The first output current I 1 increases corresponding to the increase of the error voltage VEA. In turn, the turn-on duty ratio of the switch transistor Q 1 increases. As a result, the output voltage of the switch power supply increases so that it can be stabilized.

FIG. 6 illustrates an exemplary circuit diagram corresponding to a PFM mode or a BURST mode. In some exemplary embodiments, the mode judging unit, such as the mode judging unit 1152 shown in FIG. 3 , is represented by a third current source. The third current source can reduce a third output current I 3 to less than a preset current value when the error voltage VEA is less than the second preset voltage. The third current source can maintain the value of the third output current I 3 as a constant when the error voltage VEA is greater than or equal to the second preset voltage.

In FIG. 6 , the frequency modulating unit, such as the frequency modulating unit 1156 shown in FIG. 3 , comprises: a first capacitor C 1 ; a second capacitor C 2 ; a comparison A 2 ; a first switch K 1 , of which a first terminal connects to an output terminal of the second current source and a second terminal connects to a first terminal of the first capacitor C 1 and a negative terminal of the comparator A 2 , wherein the first switch K 1 is configured to operate according to the degaussing time signal Tds; and a second switch K 2 , of which a first terminal connects to an output terminal of the third current source, a second terminal connects to the second terminal of the first switch K 1 , and a third terminal connects to a first terminal of the second capacitor C 2 and a positive terminal of the comparator A 2 , wherein the second switch K 2 is configured to connect the first terminal and the second terminal thereof or connect the first terminal with the third terminal thereof according to the degaussing time signal Tds. A detailed description of the operation of the exemplary circuit shown in FIG. 6 will be discussed below in association with FIG. 7 .

FIG. 7 illustrates a timing diagram of an exemplary constant voltage and current module operating under the PFM/BURST mode, corresponding to the circuit shown in FIG. 6 . In some exemplary embodiments, the operation of the control IC under the PFM/BURST mode includes four stages as shown in FIG. 7 . Each of the four stages is discussed below.

During the first stage, the first capacitor C 1 and the second capacitor C 2 are both reset at the beginning of the first cycle T.

During the second stage, the switch transistor Q 1 (not shown in FIG. 6 ) turns on when it receives the turn-on pulse ON of the control signal VCOMP. At this time, the degaussing time signal Tds is low and the third current source charges the second capacitor C 2 with the third output current I 3 . As a result, the voltage across the second capacitor C 2 (i.e., VC 2 ), increases and the output signal VCOMP of the second comparator A 2 changes to a high voltage level.

During the third stage, the turn-on period Ton of the switch transistor Q 1 ends and the switch transistor Q 1 turns off. Subsequently, the degaussing period starts. At this time, the degaussing time signal Tds is high, and both the second output current I 2 and the third output current I 3 charge the first capacitor C 1 . As a result, the voltage across the first capacitor C 1 (i.e., VC 1 ) increases while VC 2 is unchanged or substantially unchanged. When VC 1 is greater than VC 2 , the output of the second comparator A 2 flips to a low voltage level from the high voltage level.

During the fourth stage, the degaussing period ends. At this time, VC 1 is still greater than VC 2 and the second comparator A 2 still outputs a low voltage level. But the degaussing time signal Tds reverts back to low and thus VC 1 is unchanged or substantially unchanged, while the third output current I 3 continues to charge the second capacitor C 2 until VC 2 is greater than VC 1 . When VC 2 is greater than VC 1 , the output of the second comparator A 2 flips to a high voltage level, i.e., the control signal VCOMP becomes high. The second comparator A 2 outputs a turn-on pulse ON, causing the switch transistor Q 1 to turn on. The first capacitor C 1 and the second capacitor C 2 then reset, and the first operating cycle under the PFM/BURST mode ends.

According to the discussion above, the following formulas characterize operation:

Δ ⁢ ⁢ Vc ⁢ ⁢ 1 = ( I ⁢ ⁢ 2 + I ⁢ ⁢ 3 ) · Tds C ⁢ ⁢ 1 ; ( 2 ) Toff + Ton = C ⁢ ⁢ 2 · Δ ⁢ ⁢ Vc ⁢ ⁢ 1 I ⁢ ⁢ 3 = C ⁢ ⁢ 2 ⁢ ( I ⁢ ⁢ 3 + I ⁢ ⁢ 2 ) · Tds I ⁢ ⁢ 3 · C ⁢ ⁢ 1 ; and ( 3 ) Tds T = Tds Tds + Ton + Toff = I ⁢ ⁢ 3 · C ⁢ ⁢ 1 I ⁢ ⁢ 3 · C ⁢ ⁢ 1 + C ⁢ ⁢ 2 ⁢ ( I ⁢ ⁢ 3 + I ⁢ ⁢ 2 ) . ( 4 )

Formula (4) can be obtained by combining formulas (2) and (3).

As discussed above, when the switch power supply is fully-loaded or overloaded, the output voltage of the switch power supply is small. Thus, the feedback voltage, which reflects the output voltage and is collected by the control IC, is also small and the error voltage VEA equals VDD. When VEA equals VDD, the second output current I 2 equals zero. That is, the second output current I 2 changes in an opposite direction as that of the error voltage VEA. Meanwhile, the third output current I 3 is unchanged. Therefore, the charging current of the first capacitor C 1 and the second capacitor C 2 are the same, i.e., they are both the third output current I 3 . According to formula (4) above, when I 2 =0,

Tds T = C ⁢ ⁢ 1 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 . ( 5 )

That is, Tds/T is determined by the ratio of the first capacitor C 1 and sum of the first capacitor C 1 and second capacitor C 2 . And once the capacitance values of the first capacitor C 1 and the second capacitor C 2 are determined, Tds/T is a constant when the switch power supply outputs a constant current.

When the load of the switch power supply decreases to a certain degree, the output voltage of the switch power supply increases and the error voltage VEA decreases from VDD. Correspondingly, the second output current I 2 increases. According to formula (4) above, an increase of the output current I 2 can correspond to an increase of the operating cycle time T, which results in a decrease of the control IC's operating frequency fosc. When the operating frequency decreases, both the output power and the output voltage of the switch power supply decrease. Conversely, when the load of the switch power supply increases, the output voltage increases and the error voltage VEA increases. The second output current I 2 decreases correspondingly. As a result, the control IC's operating frequency fosc increases, and the output voltage of the switch power supply increases. Thus, a negative feedback loop is formed for stabilizing the output voltage.

When error voltage VEA is between V 1 and V 2 , i.e., V 2 <VEA<V 1 , the control IC enters both the PWM mode and the PFM mode. The second output current I 2 varies opposite to the variation of the error voltage VEA. That is, when the error voltage VEA decreases, the second output current I 2 increases. Hence, according to formula (4) above, Tds/T decreases when the error voltage VEA decreases, because the second output current I 2 increases. And if Tds is kept constant, then the operating cycle time T increases. In other words, when the error voltage VEA decreases, the control IC's operating frequency fosc is reduced, realizing the pulse frequency modulation (PFM).

When error voltage VEA is less than the preset voltage V 4 , the control IC enters the BURST mode, during which the second output current I 2 is maintained and the third output current I 3 is changed to a small value and maintained. Thus, according to formula (4), Tds/T decreases further because the operating cycle time T increases. As a result, the operating frequency fosc decreases further until the control IC no longer operates under the BURST mode. When the error voltage VEA is less than V 4 , it indicates that the switch power supply is lightly loaded or unloaded. Accordingly, the decrease of the control IC's operating frequency fosc reduces the switching loss of the switch power supply and thus reduces the standby power consumption.

FIG. 8 illustrates a block diagram of an exemplary switch power supply. As shown in FIG. 8 , a switch power supply comprises: a control integrated circuit IC 1 such as the control IC shown in FIG. 2 ; an input filter and rectification module 11 , configured to filter a first alternating current (AC) voltage for obtaining desired frequencies and convert the first alternating current (AC) voltage to a first direct current (DC) voltage; a primary winding 13 of a transformer, configured to convert the first DC voltage to an electromagnetic signal, wherein the conversion is controlled by the switch transistor Q 1 ; a power supply module 14 , configured to provide a power supply voltage to the control integrated circuit IC 1 ; a primary side feedback module 15 , configured to divide the power supply voltage and provide the divided power supply voltage to the control integrated circuit IC 1 ; a primary collecting module 16 , configured to collect the peak current feedback signal; a secondary winding 17 of the transformer, configured to convert the electromagnetic signal to an electric signal and generate a second AC voltage corresponding to the electric signal; an output rectification module 18 , configured to convert the second AC voltage to a second DC voltage; a voltage regulating module 19 , configured to store the energy provided by the output rectification module and provide output power for stabilizing an output DC voltage of the switch power supply when the switch transistor Q 1 is turned off; and a dummy load module 20 , configured to consume energy generated by the secondary winding when the switch power supply carries no load.

In FIG. 8 , the control IC 1 can include an error amplifying module, such as the error amplifying module 113 shown in FIG. 2 . As discussed above in association with FIG. 2 , the error amplifying module compares a feedback voltage and a reference voltage and generates an error voltage, which is for determining the load condition of the switch power supply. Based on the load condition, the degaussing time signal and the peak current feedback signal, the frequency and duty ratio of the control signal can be adjusted to stabilize the output voltage and output current of the switch power supply. Moreover, the operating frequency of the control IC can be reduced when the system is under a lightly loaded or unloaded condition. As a result, the switching loss of the power supply system is reduced so that the standby power consumption can be reduced.

As shown in FIG. 8 , in some exemplary embodiments, the switching power supply system further comprises a first voltage absorbing module 21 coupled to the input filter and rectification module 11 and the primary winding 13 of the transformer, wherein the first voltage absorbing module 21 is configured to absorb a first peak voltage caused by leakage inductance of the primary winding to protect the switch transistor Q 1 .

In some exemplary embodiments, the switch power supply further comprises a second voltage absorbing module 22 coupled to the secondary winding 17 of the transformer and the voltage regulating module 19 , wherein the second voltage absorbing module 22 is configured to absorb a second peak voltage generated during the reverse recovery stage of the output rectification module 18 .

FIG. 9 illustrates a circuit diagram of an exemplary switch power supply corresponding to the block diagram shown in FIG. 8 . In FIG. 9 , the primary side of the switch power supply includes a primary winding Np of a transformer, a switch transistor Q 1 configured to control the primary winding Np, and a control integrated circuit IC 1 configured to control the operation of the switch transistor Q 1 . The switch power supply further comprises a fuse FR 1 configured to disconnect the AC voltage input for protecting the system when a circuit fault occurs.

In FIG. 9 , diodes D 1 -D 4 , configured to convert the input alternating current (AC) voltage to a direct current (DC) voltage, form a full wave rectifier. Capacitors C 01 , C 02 , and inductance L 1 form a filter, which is configured to filter out interfering signals in the input AC voltage and reduce voltage ripples. The diodes D 1 -D 4 , the capacitors C 01 , C 02 , and the inductance L 1 form an exemplary circuit corresponding to the input filter and rectification module 11 shown in FIG. 8 .

In FIG. 9 , an exemplary circuit corresponding to the power supply module 14 shown in FIG. 8 can include resistors R 3 and R 4 , a capacitor C 4 , an auxiliary winding Nd and a diode D 6 . The resistors R 3 , R 4 , and the capacitor C 4 form a startup circuit for starting the control circuit IC 1 . The capacitor C 4 is charged by current flowing through the resistors R 3 and R 4 . When the power supply voltage provided to the control circuit IC 1 , i.e., the voltage across the capacitor C 4 , reaches a preset startup value, the switch power supply starts its normal operation. Subsequently, the primary winding Np starts to store energy until the primary side current reaches a certain value and the switch transistor Q 1 is turned off. The primary side current is determined by the control circuit IC 1 's voltage sampling of the resistor R 9 . After the system starts its normal operation, the system's power supply is provided through the auxiliary winding Nd and the diode D 6 .

In some exemplary embodiments, the output voltage of the auxiliary winding Nd is divided by the resistors R 6 and R 7 . The divided voltage is provided to the control circuit IC 1 as a voltage feedback signal. The control circuit IC 1 also samples the voltage across the resistor R 9 to obtain the peak current feedback signal. The voltage sampling of the resistor R 9 allows the control circuit IC 1 to determine the load condition of the switch power supply and adjust the operation of the switch transistor Q 1 accordingly.

At the output side, when the switch transistor Q 1 is turned off, the energy of the primary winding Np is coupled to the secondary winding Ns. The output AC voltage of the secondary winding Ns is rectified by the diode D 7 and becomes a DC voltage. The diode D 7 is an exemplary circuit corresponding to the output rectification module shown in FIG. 8 . The output DC voltage generated by the diode D 7 is then stored in the capacitor C 7 , which provides the output voltage when the switch transistor Q 1 is turned off. Thus, the system output voltage can be stabilized. In some exemplary embodiments, the switch power supply can also include a resistor R 12 , corresponding to the dummy load module 20 as shown in FIG. 8 . The resistor R 12 can be configured to consume energy generated by the secondary winding Ns, thus stabilizing the output voltage.

In the preceding specification, the subject matter has been described with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made without departing from the broader spirit and scope of the claimed subject matter as set forth in the claims that follow. The specification and drawings are accordingly to be regarded as illustrative rather than restrictive. Other embodiments may be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein.