MEMS-based frequency synthesizers with enhanced temperature compensation

This application is related to U.S. application Ser. No. 13/538,719, filed Jun. 29, 2012, entitled “MEMS-Based Frequency Synthesizers Having Variable Bandwidth Temperature Compensation”, the disclosure of which is hereby incorporated by reference.

The present invention relates to integrated circuit frequency synthesizers and, more particularly, to frequency synthesizers that utilize microelectromechanical resonators to generate periodic reference signals and methods of operating same.

MEMs-based frequency synthesizers frequently utilize techniques to provide temperature compensation, which can counteract temperature-induced variations in resonant frequency of MEMs resonators. As will be understood by those skilled in the art, MEMs resonators may be used as substitutes for piezoelectric crystal resonators and may be more highly integrated with electrical circuitry (e.g., transimpedance amplifiers) using conventional semiconductor fabrication techniques. Examples of conventional MEMs-based frequency synthesizers with temperature compensation are disclosed in U.S. Pat. Nos. 7,449,968 and 7,755,441 to Cioffi et al., entitled “Frequency and Temperature Compensation Synthesis for a MEMs Resonator.” Among other things, FIG. 3 of the '968 and '441 patents to Cioffi et al. discloses the use of a temperature sensor to provide an indication of the operating temperature of a MEMs resonator, which is provided to an analog-to-digital (ADC) converter. A conventional ADC converter may utilize an analog delta-sigma (ΔΣ) modulator to produce an oversampled output stream of 1-bit digital samples, which can be provided to a digital decimation filter. A digital decimation filter can be used to remove out-of-band quantization noise and unwanted out-of-band signals in the analog input of the modulator. Additional examples of conventional MEMs-based frequency synthesizers with temperature compensation are disclosed in U.S. Pat. Nos. 7,446,619, 7,532,081, 7,443,258 and 7,545,228.

FIGS. 1A-1B illustrate conventional MEMs-based frequency synthesizers 100 that utilize temperature compensation when generating periodic output signals from phase-locked loop (PLL) integrated circuits, which are responsive to periodic input signals derived from MEMs resonators. As shown by FIG. 1A , a MEMs-based frequency synthesizer 100 may include a microelectromechanical resonator circuit 102 containing a trans-impedance amplifier (TIA), which produces a periodic input signal (F IN ). This periodic input signal F IN is provided to a phase-locked loop (PLL) integrated circuit 104 , which operates as a frequency synthesizer to generate a periodic output signal (F our ). As will be understood by those skilled in the art, the frequency of the periodic output signal F OUT is typically much higher than the frequency of the periodic input signal F IN , by virtue of the inclusion of a voltage-controlled oscillator (VCO) (not shown) within the forward signal path of the PLL integrated circuit 104 . A fractional-N feedback divider 110 is also provided to generate a feedback reference signal (relative to F IN ). This feedback divider 110 is controlled by the magnitude of a feedback divider number (N), which is generated by a summation device 114 . As illustrated, this summation device 114 receives, as operands, a programmable divider number (N 1 ) stored within a register 112 and a divider number adjustment (N 2 ) generated by an analog-to-digital converter (ADC) 108 , which performs digital filtering and scaling. This ADC 108 is responsive to a clock signal CLK and an analog temperature sensor output signal T S , which is generated by a temperature sensor 106 that is operably coupled to the MEMs resonator 102 . Unfortunately, as illustrated by FIG. 1B , the MEMs-based frequency synthesizer 100 of FIG. 1A may be susceptible to a delayed locking phenomenon caused by the faster locking rate of the phase-locked loop integrated circuit 104 (e.g., <10 ms) relative to the ADC converter 108 (e.g., >100 ms). This delayed settling of the ADC converter 108 in response to a reset or start-up event may result in a relatively large adjustment in the divider number (N 2 ), which may cause the PLL integrated circuit 104 to undergo a disruptive unlock/relock transition and modify the frequency of the periodic output signal (F OUT ). Thus, notwithstanding the advantages of providing temperature compensation in MEMs-based frequency synthesizers, there continues to be a need to provide enhanced temperature compensation that does not adversely affect PLL locking characteristics.

A frequency synthesizer according to embodiments of the invention can include a frequency generator, which is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is also provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent frequency adjusting control signal in response to the temperature measurement signal. This control circuit includes a cascaded arrangement of an oversampled data converter and a multi-stage digital filter, which is configured to generate a plurality of codes from respective ones of the digital filter stages, and a selection circuit, which is configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals, respectively, to generate the temperature-dependent frequency adjusting control signal. The oversampled data converter may be a 3 rd or higher order delta-sigma (ΔΣ) modulator. The multi-stage digital filter may include a sinc filter, which is configured to generate the first of the plurality of codes, and a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters. In particular, the second of the plurality of codes may be generated by one of the plurality of halfband finite impulse response (FIR) filters. In some of the embodiments of the invention, the frequency generator may be configured as a locked-loop integrated circuit and the selection circuit may be configured to use the first of the plurality of codes when the locked-loop integrated circuit is unlocked and the second of the plurality of codes when the locked-loop integrated circuit is locked.

According to further embodiments of the invention, a frequency synthesizer may be provided with a phase-locked loop (PLL) frequency generator. This PLL frequency generator can be configured to generate a periodic output signal in response to a periodic input signal, which can be generated by a microelectromechanical-based frequency generator (e.g., MEMs resonator with trans-impedance amplifier (TIA)). The PLL frequency generator may include a feedback divider, which is responsive to a feedback divider code. A code generation circuit is provided, which is configured to generate the feedback divider code. This code generation circuit may include an analog-to-digital (ADC) converter, which is configured as a cascaded arrangement of a delta-sigma (ΔΣ) modulator, and a multi-stage digital filter, which is configured to generate a corresponding plurality of divider codes from the multiple stages thereof. A selection circuit is also provided, which is configured to use a first of the plurality divider codes to generate the feedback divider code when the PLL frequency generator is unlocked and then use a second of the plurality of divider codes to generate the feedback divider code once the PLL frequency generator has become locked.

According to some of these embodiments of the invention, the delta-sigma modulator is a 3 rd or higher order modulator. The multi-stage digital filter may also include a sinc filter, which is configured to generate the first of the plurality of divider codes, and a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters. According to these embodiments of the invention, the second of the plurality of divider codes is generated by one of the plurality of halfband finite impulse response (FIR) filters.

A temperature sensor may also be provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the microelectromechanical-based frequency generator. The ADC converter can be directly responsive to the temperature measurement signal and the temperature measurement signal may be generated in response to detecting a temperature of the MEMs resonator.

FIG. 1A is a block diagram of a microelectromechanical-based frequency synthesizer according to the prior art.

FIG. 1B is a graph of output frequency versus time for the synthesizer of FIG. 1A , which shows how output frequency can change in response to repeated PLL locking events.

FIG. 2A is a block diagram of a microelectromechanical-based frequency synthesizer according to an embodiment of the present invention.

FIG. 2B is a graph of output frequency versus time for the synthesizer of FIG. 2A , which shows how output frequency can be maintained more nearly uniform using a multi-stage digital filter.

FIG. 2C is a block diagram of an embodiment of the ADC and multi-stage digital filter of FIG. 2A .

The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer (and variants thereof), it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer (and variants thereof), there are no intervening elements or layers present. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to FIGS. 2A-2C , frequency synthesizers according to embodiments of the invention will now be described. As shown by FIG. 2A , a frequency synthesizer 200 can include a frequency generator 204 , which is configured to generate a periodic output signal (F OUT ) in response to a periodic input signal (F IN ) and a temperature-dependent code N. This periodic input signal (F IN ) is illustrated as being generated by a MEMs resonator 202 , which can include a transimpedance amplifier (TIA) for processing a resonance signal generated by the MEMs resonator 202 . A temperature sensor 206 is also provided, which is configured to generate a temperature measurement signal (T S ) in response to detecting a temperature of at least a portion of the frequency synthesizer 200 . A control circuit is provided, which is configured to generate the temperature-dependent code N in response to the temperature measurement signal (T S ). This control circuit includes a cascaded arrangement of an oversampled data converter and a multi-stage digital filter, which is configured to generate a plurality of codes from respective ones of the digital filter stages. The control circuit may also include a selection circuit, which is configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals, respectively, to generate the temperature-dependent code N. In particular, as shown by FIG. 2A , the control circuit may include an analog-to-digital (ADC) converter with multi-stage digital filtering and scaling 208 , a selection circuit 216 , which is shown as a 2-input multiplexer responsive to a selection signal (SELECT), a programmable register 212 containing a base divider number N 1 and a summation circuit 214 , which adds the base divider number N 1 to the temperature-dependent number N 2 generated by the 2-input multiplexer. As shown by FIG. 2C , the analog-to-digital (ADC) converter with multi-stage digital filtering and scaling 208 can be configured as a cascaded arrangement of an oversampled data converter 208 a and a multi-stage digital filter ( 208 b , 208 c ), which is configured to generate a plurality of codes (DATA 1 , DATA 2 ) from respective ones of the digital filter stages. According to preferred aspects of the embodiment of FIG. 2A , the selection circuit 216 may select first and second codes (DATA 1 , DATA 2 ) in sequence during first and second consecutive time intervals, respectively, to generate the temperature-dependent code N during start-up of the frequency synthesizer 200 and thereafter during normal operation when fluctuations in operating temperature are present.

FIG. 2A further illustrates that the frequency generator 204 may be provided as a phase-locked loop (PLL) frequency generator. As shown, the PLL frequency generator may include a feedback divider 210 , which is responsive to a temperature-dependent code “N”. A code generation circuit is provided as an embodiment of a control circuit, which is configured to generate the feedback divider code N. This code generation circuit includes an analog-to-digital (ADC) converter, which is configured as a cascaded arrangement of a delta-sigma (AZ) modulator 208 a , and a multi-stage digital filter 208 b , 208 c , which is configured to generate a corresponding plurality of divider codes (DATA 1 , DATA 2 ) from the multiple stages thereof. A selection circuit is also provided, which is configured to use a first of the plurality divider codes (e.g., DATA 1 ) to generate the feedback divider code N when the PLL frequency generator 204 is unlocked (e.g., at start-up and reset) and then use a second of the plurality of divider codes (e.g., DATA 2 ) to generate the feedback divider code N once the PLL frequency generator 204 has become locked. As further illustrated by the graph of FIG. 2B , the “partial stage” selection of code DATA 1 represents an “ADC” output that advantageously settles early before the PLL circuit 204 is locked, whereas the “full stage” selection of code DATA 2 represents a more heavily filtered and higher fidelity signal that does not cause unlocking of the PLL circuit 204 .

According to some of these embodiments, the ADC converter with multi-stage digital filtering and scaling 208 may be configured as shown by the cascaded arrangement of FIG. 2C , with a 2nd or higher order modulator 208 a (e.g., delta-sigma (ΔΣ) modulator) and a multi-stage digital filter. This multi-stage digital filter is shown as including a sinc filter 208 b and a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters 208 c.

In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.