Control circuit for connector

1. Technical Field

The present disclosure relates to a circuit for controlling a connector.

2. Description of Related Art

To embed programs in complex programmable logic devices (CPLD) on motherboards, operators connect an integrated circuit (IC) burner to one connector of the motherboards. To test the motherboards, the operators connect a debugging card to yet another connector on the motherboard. Two connectors must be used because the testing is done using Low Pin Count protocol. However, IC burners transmit data according to Joint Test Action Group protocol, which is inconvenient, time consuming, and uses precious space.

Many aspects of the embodiments can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawing, like reference numerals designate corresponding parts throughout the drawing.

The FIGURE is a circuit diagram of an exemplary embodiment of a control circuit.

The disclosure, including the accompanying drawings, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to the FIGURE, a control circuit 100 controls a connector 20 on a motherboard to transmit data either according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol. An exemplary embodiment of the circuit 100 includes a jumper 55 , a base 50 , transistors Q 1 and Q 2 , and switching chips 30 and 40 . In the embodiment, the connector 20 includes pins 1 - 10 . The pin 6 is connected to a standby power P 3 V 3 _STBY on the motherboard. The pin 10 is grounded.

The base 50 includes terminals 11 - 13 . The terminal 11 is connected to the standby power P 3 V 3 _STBY through a resistor R 1 . The terminal 12 is connected to the standby power P 3 V 3 _STBY through a resistor R 2 . The terminal 13 is grounded.

A base of the transistor Q 1 is connected to the terminal 12 through a resistor R 4 . A collector of the transistor Q 1 is connected to the standby power P 3 V 3 _STBY through a resistor R 5 . An emitter of the transistor Q 1 is grounded. A base of the transistor Q 2 is connected to the collector of the transistor Q 1 . A collector of the transistor Q 2 is connected to the standby power P 3 V 3 _STBY through a resistor R 6 . An emitter of the transistor Q 2 is grounded.

In the embodiment, the switching chip 40 includes a first group of data pins 1 A 1 - 1 A 4 , a second group of data pins 2 A 1 - 2 A 4 , a third group of data pins 1 Y 1 - 1 Y 4 , a fourth group of data pins 2 Y 1 - 2 Y 4 , enable pins 1 OE and 2 OE, a ground pin GND, and a power pin VCC. The data pins 1 A 1 - 1 A 4 are respectively connected to data pins LPC_LAD 0 , LPC_LAD 1 , LPC_LAD 2 , and LPC_LAD 3 of a Platform Controller Hub (PCH) 80 on the motherboard. The data pins 2 A 1 - 2 A 3 are respectively connected to a control pin LPC_LFRAME, a reset pin LPC_RST, and a clock pin LPC_CLK of the PCH 80 . The data pin 2 A 4 is grounded. The data pins 1 Y 1 - 1 Y 4 are respectively connected to the pins 1 - 4 of the connector 20 . The data pins 2 Y 1 - 2 Y 3 are respectively connected to the pins 7 - 9 of the connector 20 . The data pin 2 Y 4 is grounded. The power VCC is connected to the standby power P 3 V 3 _STBY. The ground pin GND is grounded. The enable pins 1 OE and 2 OE are connected to the collector of the transistor Q 1 . In the embodiment, when the enable pins 1 OE and 2 OE both receive low level signals, the data pins 1 A 1 - 1 A 4 are respectively connected to the data pins 1 Y 1 - 1 Y 4 , and the data pins 2 A 1 - 2 A 3 are respectively connected to the data pins 2 Y 1 - 2 Y 3 . When the enable pin 1 OE and 2 OE both receive high level signals, the data pins 1 A 1 - 1 A 4 are disconnected from the data pins 1 Y 1 - 1 Y 4 , and the data pins 2 A 1 - 2 A 3 are disconnected from the data pins 2 Y 1 - 2 Y 3 .

In the embodiment, the switching chip 30 includes a first group of data pins 1 A- 4 A, a second group of data pins 1 Y- 4 Y, an enable pin OE, a ground pin GND, and a power pin VCC. The data pins 1 A- 4 A are respectively connected to data pins JTAG_PLD_TCK, JTAG_PLD_TDO, JTAG_PLD_TMS, and JTAG_PLD_TDI of a complex programmable logic device (CPLD) 70 on the motherboard. The data pins 1 Y- 4 Y are respectively connected to the pins 1 - 3 and 5 of the connector 20 . The enable pin OE is connected to the collector of the transistor Q 2 . The power pin VCC is connected to the standby power P 3 V 3 _STBY. The ground pin GND is grounded. In the embodiment, when the enable pin OE receives a low level signal, the data pins 1 A- 4 A are respectively connected to the data pins 1 Y- 4 Y. When the enable pin OE receives a high level signal, the data pins 1 A 1 - 4 A are disconnected from the data pins 1 Y- 4 Y.

In use, when operators need to burn programs into the CPLD 70 through the connector 20 , the terminals 12 and 13 of the base 50 are connected through the jumper 55 . The base of the transistor Q 1 is grounded. The transistor Q 1 is turned off. The enable pins 1 OE and 2 OE of the switching chip 40 and the base of the transistor Q 2 receive high level signals. The data pins 1 A 1 - 1 A 4 are disconnected from the data pins 1 Y 1 - 1 Y 4 , and the data pins 2 A 1 - 2 A 3 are disconnected from the data pins 2 Y 1 - 2 Y 3 of the switching chip 40 . As a result, the connector 20 is not electronically connected to the PCH 80 . Furthermore, the transistor Q 2 is turned on. The enable pin OE of the switching chip 30 receives a low level signal. The data pins 1 A- 4 A are respectively connected to the data pins 1 Y- 4 Y of the switching chip 30 . As a result, the connector 20 is electronically connected to the CPLD 70 and transmits using the JTAG protocol. The operators can burn programs into the CPLD 70 through the connector 20 .

When the operators needs to receive error codes through the connector 20 using a debugging card, the terminals 12 and 13 of the base 50 are disconnected from each other. At this time, the base of the transistor Q 1 receives a high level signal. The transistor Q 1 is turned on. The enable pins 1 OE and 2 OE of the switching chip 40 receive low level signals. The base of the transistor Q 2 receives a low level signal. The transistor Q 2 is turned off. The enable pin OE of the switching chip 30 receives a high level signal. The data pins 1 A- 4 A are disconnected from the data pins 1 Y- 4 Y of the switching chip 30 . As a result, the connector 20 is not electronically connected to the CPLD 70 . Furthermore, because the enable pins 1 OE and 2 OE of the switching chip 40 receive low level signals, the data pins 1 A 1 - 1 A 4 are respectively connected to the data pins 1 Y 1 - 1 Y 4 , and the data pins 2 A 1 - 2 A 3 are respectively connected to the data pins 2 Y 1 - 2 Y 3 of the switching chip 40 . As a result, the connector 20 is electronically connected to the PCH 80 , and transmits data using the LPC protocol. The operators can receive error codes through the connector 20 .

As described above, the base 50 and the jumper 55 can be used to ground the base of the transistor Q 1 or not ground the base of the transistor Q 1 . In other words, the base 50 and the jumper 55 function as a switch. In other embodiments, the base 50 and the jumper 55 can be replaced by other switches, such as a button switch. In addition, the transistors Q 1 and Q 2 function as electronic switches. In other embodiments, the transistors Q 1 and Q 2 can be replaced by other electronic switches, such as metallic oxide semiconductor field effect transistors (MOSFETs).

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in the light of everything above. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.