Current control circuit and associated method

This application claims the benefit of CN application No. 201110166613.9, filed on Jun. 21, 2011, and incorporated herein by reference.

The present invention generally relates to electric circuit, and more particularly but not exclusively relates to a current control circuit and associated method.

In electric circuit, precise current, especially precise average current, is commonly required to be provided to load. The term “load” hereby includes but not limited to electrical load, battery, and light-emitting diode (LED), etc. Among these loads, the precision control of LED current, especially LED average current, is particularly important. LED current control circuit is applied as an example to introduce the related technology in the following text.

It is well-known that the luminance of LED depends on the average current flowing through the LED. The average current of LED may be set by a current control circuit. FIG. 1 illustrates a LED current control circuit 100 , comprising: an input voltage terminal V IN , a switch terminal SW, and a reference ground terminal GND; a fly-wheel circuit 101 comprising an inductor L, a load of LED string and a rectifier coupled in series, wherein the LED string comprises a plurality of LEDs D 1 -DN, the LED string is further coupled to the input voltage terminal V IN through a sampling resistor R SENSE , and rectifier Rectifier is coupled between the input voltage terminal V IN and the switch terminal SW; a current sense circuit 102 comprising a first resistor R 1 , a first error amplifier EA 1 and a first transistor T 1 , wherein current sense circuit 102 senses the current flowing through the LED string, and generates a first current signal I FIRST accordingly; a first reference signal REF; a control circuit 103 comprising a second resistor R 2 , a third resistor R 3 , a second switch M 2 , a first comparator C 1 and a driver D 1 , responsive to the first current signal I FIRST and the first reference signal REF, operable to generate a control signal V CON ; and a switch M 1 , coupled between the switch terminal SW and the reference ground terminal GND, turned ON and OFF according to the control signal.

As shown in FIG. 2 , when the first switch M 1 is turned on (the voltage V SW on the SW terminal is at low level), a loop comprising the input voltage terminal V IN , the inductor L, the load, the switch M 1 and the reference ground terminal GND is conducted. The current flowing through the LED string (inductor current I L ) gradually increases. By the effect of the current sense circuit 102 , I SENSE also gradually increases, and the voltage level on a node B rises up. At this moment, the second switch M 2 is turned ON, and the voltage drop on the third resistor R 3 and the second switch M 2 may be ignored. When the voltage level on node B reaches V REF (the voltage level of REF signal), that is, I FIRST reaches V REF /R 2 , the first comparator C 1 is reversed and generates a low level output signal. The first switch M 1 and the second switch M 2 are turned OFF (the voltage V SW on the SW terminal is at high level), and the LED string, inductor L, rectifier Rectifier comprises a current loop. The current on the LED load decreases gradually. By the effect of current sense circuit 102 , I FIRST also gradually decreases, and the voltage level on node B falls down. When the voltage level on node B falls to V REF , that is, the current I FIRST decreases to V REF /(R 2 +R 3 ), the comparator P 2 is reversed to generate a high level output signal. I FIRST oscillates between a hysteresis voltage [V REF /(R 2 +R 3 ), V REF /R 2 ], and correspondingly the inductor current I L oscillates between the hysteresis voltage [V REF /(R 2 +R 3 ), V REF /R 2 ].

Supposing the duty cycle D of the first switch M 1 is 50%, when I FIRST reaches the high level peak of the hysteresis voltage V REF /R 2 , it takes some time for the system to control the switch M 1 ON and OFF. Seen in FIG. 2 , the T D1 and T D2 are respectively the propagation delay time of the first comparator C 1 and the delay time of the driver circuit. T D1 represents the period from the moment when I FIRST reaching V REF /(R 2 +R 3 ) to the moment when the switch M 1 is turned ON, while T D2 represents the period from the moment when I FIRST reaching V REF /R 2 to the moment when the switch M 1 is turned OFF. ΔI TH1 and ΔI TH2 are respectively the output current error caused by delays T D1 and T D2 . When the duty cycle D is 50%, if T D1 =T D2 , then ΔI TH1 =ΔI TH2 . As a result, the average current flowing through inductor L is still precise.

The variation of input voltage or the number of serially coupled LEDs may lead to the change of duty cycle D. As shown in FIG. 3 , supposing the duty cycle D is 10%, it may approximately consider that the up-time of the inductor current is 1/9 of the down time of the inductor current. Thus the current rising rate is 9 times more than the current falling rate. Once T D1 =T D2 , then ΔI TH1 =9×ΔI TH2 . Thus, when the duty cycle D is smaller than 50%, the average inductor current I L may drift to I TH1 and generate an error, so that the average inductor current is higher than the desired value. On the contrary, when the duty cycle D is larger than 50%, the average inductor current I L may drift to I TH2 and also generate an error, so that the average inductor current I L is smaller than the desired value.

Besides the above description, the reasons of generating an error further include but not limited to: the delay, delay difference under different load/inductor current, or non-linearity of current sense circuit 102 ; the delay, non-linearity or delay difference between rising-edge and falling-edge of control circuit 103 ; the delay, non-linearity or difference between rising-edge and falling edge of the driver circuit; the varying of the above delays, delay difference or non-linearity caused by the change of duty cycle.

One embodiment of the present invention discloses a current control circuit system to provide a precise load current, especially a precise average load current. The current control circuit system comprises: a fly-wheel circuit comprising an inductor, a rectifier and a load, wherein the inductor and the load are coupled in series; a current sense circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the fly-wheel circuit and wherein the output terminal is configured to provide a first current signal indicating a load current flowing through the load; a compensating circuit having an output terminal configured to provide a compensating signal; a control circuit, having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the current sense circuit and the output terminal of the compensating circuit, and the output terminal of the control circuit is configured to provide a control signal according to the first current signal and the compensating signal; and a first switch comprising a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the fly-wheel circuit, the second terminal is coupled to a reference ground and control terminal is coupled to the output of the control circuit, and wherein the first switch is configured to be turned ON and OFF according to the control signal.

By introducing the compensating circuit and the compensating signal into the current control circuit, the drift error of the average load current may be prohibited.

Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are not depicted to scale and only for illustration purpose.

FIG. 1 illustrates a prior art LED current control circuit system 100 .

FIG. 2 illustrates a prior art operation waveform diagram of the LED current control circuit system 100 when the duty-cycle is 50%.

FIG. 3 illustrates a prior art operation waveform diagram of the LED current control circuit system 100 when the duty-cycle is 90%.

FIG. 4 illustrates a schematic block diagram of a current control circuit system 400 according to an embodiment of the present invention.

FIG. 5 illustrates an operation process flow diagram of the current control circuit system 400 according to an embodiment of the present invention.

FIG. 6 illustrates a specific circuitry diagram of a current control circuit system 600 according to an embodiment of the present invention.

FIG. 7 illustrates an operation waveform diagram of the current control circuit system 600 according to an embodiment of the present invention

FIG. 8 illustrates a specific circuitry diagram of a current control circuit system 800 according to another embodiment of the present invention.

FIG. 9 illustrates a specific circuitry diagram of a current control circuit system 900 according to yet another embodiment of the present invention.

The use of the same reference label in different drawings indicates the same or like components.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 4 illustrates a schematic block diagram of a current control circuit system 400 according to an embodiment of the present invention. A current control circuit system 600 shown in FIG. 6 , a circuit system 800 shown in FIG. 8 , and a circuit system 900 shown in FIG. 9 , schematically introduce some specific structural embodiments of circuit system 400 . As shown in FIG. 4 , current control circuit system 400 may comprise: an input voltage terminal V IN , a switch terminal SW and a reference ground terminal GND; a fly-wheel circuit 101 , comprising an inductor L, a load (D 1 , D 2 , . . . Dn) and a rectifier Rectifier, wherein fly-wheel circuit 101 is coupled between the input voltage terminal V IN and the switch terminal SW; current sense circuit 102 , detecting the current flowing through the load and the inductor, and generating a first current signal I FIRST ; a first, reference signal REF; a compensating circuit 401 , generating a compensating signal 402 ; a control circuit 403 , generating a control signal V CON according to the first current signal I FIRST , compensating signal 402 , and maybe further according to first reference signal REF in certain embodiments; and a switch M 1 , coupled between the switch terminal SW and the reference ground terminal GND, turned ON and OFF according to the control signal V CON . One with ordinary skill in relevant art may choose to detect the load current or the inductor current according to different specific applications for generating the first current signal. In one embodiment, load current may be detected. In another embodiment, inductor current may be detected. In yet another embodiment, the current is detected from both the load and the inductor.

In the shown embodiment, the load (D 1 , D 2 , Dn) are a LED string. In other embodiments, the load may comprise one LED, or a plurality of LED strings. The type of LED may comprise but not limited to white LED, blue LED, red LED, yellow LED, and etc. In other embodiment, the load may further comprise but not limited to battery, electric load, and etc.

In one embodiment, the rectifier Rectifier may comprise Schottky diode. In other embodiments, P-type or N-type metal-oxide semiconductor field effect transistor (MOSFET) may be applied in the rectifier.

In one embodiment, the load and the inductor L are coupled in series, and then together coupled between the input voltage terminal V IN and the switch terminal SW. The rectifier Rectifier is coupled between the input voltage terminal V IN and the switch terminal SW. In one embodiment, the inductor L is adjacent to switch terminal SW, while in another embodiment, the load is adjacent to switch terminal SW. In other embodiments, the inductor L is coupled among the LED strings. The dash line in FIG. 4 emphasizes a coupling relationship, which represents that the rectifier Rectifier, the load D 1 -DN and the inductor L may be coupled directly, or indirectly coupled through other device, wire, and etc. Unless particularly or exclusively mentioned, the solid line also represents a coupling relationship but not direct connection relationship.

In one embodiment, the current control circuit system 600 shown in FIG. 6 further comprises a sampling resistor R SENSE . The sampling resistor R SENSE is coupled to the load D 1 -DN or inductor L. The sampling resistor R SENSE may be adjacent to the input voltage terminal V IN , or adjacent to the switch terminal SW. The sampling resistor R SENSE may be coupled among the LED strings, or coupled between the LED load and the inductor L. The current sense circuit 102 detects the current flowing through the load by the sampling resistor R SENSE . In one embodiment, the sampling resistor R SENSE comprises a first terminal and a second terminal. The current sense circuit 102 comprise as shown in FIG. 6 : a first resistor R 1 , comprising a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the sampling resistor R SENSE ; a first error amplifier EA 1 , wherein a first input terminal is coupled to the second terminal of the first resistor R 1 , and wherein a second input terminal is coupled to a second terminal of the sampling resistor R SENSE ; a first transistor T 1 , wherein a gate is coupled to an output terminal of the first error amplifier EA 1 , and wherein a first input terminal is coupled to the second terminal of the first resistor, and further wherein a second input terminal is coupled to the control circuit 103 .

In one embodiment, the control circuit 103 has plurality of input terminals and an output terminal. In one embodiment, the control circuit 103 comprises: a hysteresis generator 606 , generating a hysteresis voltage on a hysteresis voltage generating node B; a first comparator C 1 , having a first input terminal, a second input terminal and an output terminal, and wherein the output terminal generates the control signal V CON . In certain embodiments, wherein the second terminal is coupled to the first reference signal REF. In some embodiments, the control circuit may further comprise a driver D 1 , coupled to an output terminal of the first comparator C 1 , converting the control signal V CON to a driving signal to drive the switch. In one embodiment, the hysteresis generator 606 comprises a second resistor R 2 ; a third resistor R 3 , coupled to the second resistor R 2 ; a second switch M 2 , coupled to the third resistor R 3 in parallel, controlled by the control signal V CON .

According to an embodiment of the present invention, the control signal is a PWM (pulse width modulation) signal and the compensating signal is responsive to the duty cycle D of the control signal. The compensating signal may indicate the value of the duty cycle. In one embodiment, the compensating signal arises with the increase of the duty cycle. In another embodiment, the compensating signal decreases with the increase of the duty cycle. In yet another embodiment, a linearity relationship is established between the compensating signal and the duty cycle D.

In one embodiment, the compensating signal may be a current signal. The compensating signal is coupled into the first current signal I FIRST . The compensating signal may be a positive signal or a negative signal, and may be a sinking current or a sourcing current. The coupling method may comprise, without limitation, directly or indirectly adding, subtracting, multiplying, dividing, integrating, differentiating, or the above operations with amplifying or level shifting.

According to one embodiment of the present invention, the current compensating circuit 601 shown in FIG. 6 comprises: a first low-pass filter 603 , having an input terminal and an output terminal, wherein the input terminal is coupled to the hysteresis voltage generating node B; a first amplifier 604 , having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to hysteresis voltage generating node B, and wherein the second input terminal is coupled to the first reference voltage REF, and further wherein the output terminal generates the compensating signal 602 . In one embodiment, the first amplifier may be a transconductance amplifier.

According to another embodiment, the current compensating circuit 801 shown in FIG. 8 may alternatively comprise: a second reference voltage V CC /2; a low-pass filter 803 ; a first amplifier 804 , having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output of the control circuit 103 through the low-pass filter 803 , and wherein a second input terminal is coupled to the second reference voltage V CC /2, wherein the second reference voltage V CC /2 equals half of the high level voltage of the control signal V CON , and further wherein the output terminal generates the compensating signal. In one embodiment, the first amplifier is a transconductance amplifier.

In yet another embodiment, the second input terminal of the first comparator C 1 is coupled to the compensating signal. A compensating circuit 901 shown in FIG. 9 comprises: a low-pass filter 903 ; a first amplifier 904 , having a first input terminal, a second input terminal and an output terminal, wherein a first input terminal is coupled to the control circuit 103 through the third low-pass filter 903 , and wherein a second input terminal is coupled to the first reference signal REF. In the illustrated embodiment, the first amplifier is a transconductance amplifier. The compensating circuit 901 further comprises a fourth resistor R COM , coupled between the first reference signal REF and the output terminal of the first amplifier 904 ; and a first capacitor C COM , coupled between the first input terminal and the output terminal of the first amplifier 904 .

In some other embodiments, the compensating signal is coupled with the first reference signal. The coupling method may comprise, without limitation, directly or indirectly adding, subtracting multiplying, dividing, integrating, differentiating, or the above operations with amplifying or level shifting.

FIG. 5 illustrates a process flow chart 500 of a current control method according to an embodiment of the present invention. Process flow chart 500 comprising: step 501 , providing energy to a load by an inductor, a rectifier and a switch; step 502 , generating a first current signal I FIRST to represent the load current or the inductor current; step 503 , generating a compensating signal 510 by a compensating circuit; step 504 , providing a first reference signal REF; step 505 , generating a control signal V CON according to the first current signal I FIRST and the compensating signal 510 . In certain embodiment, generating the control signal V CON may be also according the first reference signal REF. The process flow further comprises a step 506 , applying the control signal V CON to control the switch ON and OFF. It should be noted that steps 501 - 506 are the description sequence in the text hereby, and do not represent the operation sequence of the embodiment of the present invention.

In one embodiment, the load mentioned in process flow chart 500 may be LED. The load may comprise one or more LEDs, or one or more strings of LED. The type of LED may comprise but not limited to white LED, blue LED, red LED, yellow LED, and etc. In another embodiment, the load may further comprise but not limited to battery, electric load, and etc.

In one embodiment, the rectifier mentioned in process flow chart 500 may comprise a Schottky diode. In other embodiments, P-type or N-type metal-oxide semiconductor field effect transistor (MOSFET) may be applied into the rectifier.

In one embodiment, the control method further comprises providing an input voltage terminal V IN and a switch terminal SW. The load and the inductor L are coupled in series, and then together coupled between the input voltage terminal V IN and the switch terminal SW. The rectifier Rectifier is coupled between the input voltage terminal V IN and the switch terminal SW. In one embodiment, the inductor L is adjacent to switch terminal SW while in another embodiment, the load is adjacent to switch terminal SW. In other embodiments, the inductor L is coupled in certain positions among the LED strings. The rectifier, the load and the inductor may be coupled directly, or indirectly coupled through other device, wire, and etc.

In one embodiment, the current control method further comprises applying a sampling resistor R SENSE ( FIG. 6 ) coupled to the load or inductor in series. The sampling resistor R SENSE may be adjacent to the input voltage terminal V IN , or adjacent to the switch terminal SW. The sampling resistor R SENSE may be coupled among the loads, or coupled between the load and the inductor. The current sense circuit 102 detects the current flowing through the load by the sampling resistor R SENSE . In one embodiment, the sampling resistor R SENSE comprises a first terminal and a second terminal; The current sense circuit 102 comprises: a first resistor R 1 , comprising a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the sampling resistor R SENSE ; a first error amplifier EA 1 , wherein a first input terminal is coupled to the second terminal of the first resistor R 1 , and wherein a second input terminal is coupled to a second terminal of the sampling resistor R SENSE ; a first transistor T 1 , wherein a gate is coupled to an output terminal of the first error amplifier EA 1 , and wherein a first input terminal is coupled to the second terminal of the first resistor, and further wherein a second input terminal is coupled to the control circuit 103 .

According to one embodiment of the present invention, generating the control signal comprises: generating hysteresis voltage by a hysteresis generator; comparing hysteresis voltage with the first reference signal REF and generating the control signal V CON accordingly. In certain embodiments, the control signal V CON may further be converted to a driving signal. In one embodiment, the hysteresis generator comprises a second resistor R 2 ; a third resistor R 3 , coupled to the second resistor R 2 ; a second switch M 2 , coupled to the third resistor R 3 in parallel, and controlled by the control signal V CON .

According to one embodiment, the control signal may be a PWM signal and thus generating the compensating signal 510 may be based on the duty cycle of the control signal V CON . The compensating signal 510 is responsive to the duty cycle signal. The compensating signal may reflect the value of the duty cycle. In other embodiment, the compensating signal 510 increases as the duty cycle increases. In another embodiment, the compensating signal 510 increases as the duty cycle decreases. In yet another embodiment, a linear relationship is established between the compensating signal 510 and the duty cycle.

In one embodiment, the compensating signal may be a current signal. The method further comprises coupling the compensating signal into the first current signal I FIRST . The current control signal may be a positive signal or a negative signal, and may be a sinking current or a sourcing current. The coupling method may comprise, without limitation, directly or indirectly adding, subtracting multiplying, dividing, integrating, differentiating, or the above operations with amplifying or level shifting.

In one embodiment, generating the compensating signal comprises: filtering the first current signal I FIRST ; sending the filtered first current signal and the first reference signal REF to a first amplifier; and generating the compensating signal accordingly by the first amplifier.

According to another embodiment, generating the compensating signal may alternatively comprises: filtering the control signal V CON ; sending the filtered control signal and a second reference signal V CC /2 to a first amplifier, wherein the second reference signal V CC /2 equals half of the high voltage level of the control signal V CON ; and generating the compensating signal accordingly by the first amplifier.

In another one embodiment, generating the control signal V CON may alternatively comprises: generating a hysteresis voltage through a hysteresis generator according to the first current signal I FIRST ; and comparing the hysteresis voltage with the compensating signal and generating the control signal accordingly.

In one embodiment, generating the compensating signal comprises: filtering the first current signal I FIRST ; sending the filtered first current signal and the first reference signal REF to a first amplifier to make the first amplifier sink or source current; and generating the compensating signal accordingly by the first amplifier. In one embodiment, the first amplifier may be a transconductance amplifier.

In yet another embodiment, the compensating signal is coupled with the first reference signal. The coupling method may comprise, without limitation, directly or indirectly adding, subtracting multiplying, dividing, integrating, differentiating, or the above operations with amplifying or level shifting.

FIG. 6 illustrates a specific schematic circuit of a circuit system 600 according to an embodiment of the present invention. Circuit system 600 comprises: an input voltage terminal V IN , a switch terminal SW and a reference ground terminal GND. In the illustrated embodiment, the input voltage terminal V IN is coupled to a power supply and the terminal GND is connected to the reference ground. However, in other embodiments, the terminal GND may be coupled to a negative power supply. Or each of the terminals V IN , SW and GND may apply one or more ports, pads, or pins.

A fly-wheel circuit 101 comprises an inductor L, a load and a rectifier Rectifier. In the illustrated embodiment, the load comprises a LED string D 1 -D N (n is an integrate number larger than 1). In other embodiment, the load may comprise a plurality of LED strings with equivalent or nonequivalent numbers of LEDs for each LED string. AS shown in FIG. 6 , the rectifier comprises a Schottky diode. However, in other embodiments, the rectifier comprises a synchronous switch. The synchronous switch may comprise N-type MOSFET (NMOS), P-type MOSFET(PMOS) or insulated gate bipolar transistor (IGBT). Correspondingly, a complementary or synchronous signal of the control signal V CON is required for the system to control the synchronous switch. Seen in FIG. 6 , the load D 1 -DN and the inductor L are coupled in series, and then are together coupled between the input voltage terminal VIN and the switch terminal SW. The inductor L is adjacent to the switch terminal SW. Since the currents on each of the devices in a series connection circuit loop are approximately the same (ignore the affecting factors such as leakage current), in other embodiments, the load may be placed after the inductor L and adjacent to the switch terminal SW. In another embodiment, the inductor may be placed at certain positions among the LEDs in a LED string. Other suitable devices may also be coupled between the switch terminal SW and an output terminal, for an instance, coupling a PMOS with a low on-state resistance between the input voltage terminal V IN and a node A, or before the LED strings. When the system is idle, the PMOS is turned OFF, so that the whole system is off-insulated without leakage current. While the system is operating, the PMOS is turned on. Because of the low on-state resistance of the PMOS, the power loss is limited and does not affect the normal operation of the system. The rectifier is coupled between the input voltage terminal V IN and the switch terminal SW. In other embodiments, the rectifier may be coupled between the input voltage terminal V IN and the switch terminal SW through other switches, sampling resistors or hall-effect devices. It should be noted that the connection relationship shown in FIG. 6 is illustrative. In other embodiments, the rectifier, the inductor and the load may be coupled between the switch terminal SW and the reference ground terminal GND, and the switch may be coupled between the input voltage terminal V IN and the switch terminal SW to form a buck converter structure. In yet other embodiments, the inductor, the load, the rectifier and the switch may form a boost, a buck-boost, a fly-back or other suitable structure, which are included in the scope of the present invention.

Current sense circuit 102 senses the current flowing through the load and is configured to generate a first current signal I FIRST . The circuit system 600 further comprises a sampling resistor R SENSE , coupled between node A and the load. The resistance scope of R SENSE may be from 0.01 ohmic to several ohmic. It should understand that this resistance value range is for illustration without limitation. Similarly, since the current in a series connected circuit loop is substantially the same, the sampling resistor R SENSE may be coupled among the LEDs in LED string, or between the LED string and the inductor, or after the inductor. In other embodiment, the sampling resistor R SENSE may be omitted, and the current on the load or inductor is directly detected. In another embodiment, the current sense circuit 102 detects the voltage difference between the input voltage terminal V IN and the switch terminal SW, or between node A and the terminal SW. Thus the sensed current may generate a sensed current signal is responsive to the load current or the inductor current and representing the change of the load current. Once the generated signal has a logic relationship with the load current or inductor current, it should be considered as a current sampling signal. Shown in FIG. 6 , the current sense circuit comprises: the sampling resistor R SENSE , having a first terminal and a second terminal, wherein the first terminal is coupled to node A, and wherein the second terminal is coupled to the load; a first resistor R 1 , having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the sampling resistor R SENSE ; a first error amplifier EA 1 , wherein an first input terminal is coupled to the second terminal of the first resistor, and wherein the second input terminal is coupled to the second terminal of the sampling resistor R SENSE ; a first transistor T 1 , wherein a gate terminal is coupled to an output terminal of the first error amplifier EA 1 , and wherein a source terminal is coupled to the second terminal of the first resistor R 1 , and further wherein a drain terminal is coupled to the control circuit 103 .

Due to the negative feedback effect of the amplifier, the voltage level on the second terminal of the first resistor and the second terminal of the sampling resistor are maintained the same. Therefore the voltage drops on the two resistors are equal,

I FIRST ×R 1= I RSENSE ×R SENSE   (1)

I FIRST =I RSENSE ×R SENSE /R 1  (2)

Wherein, I FIRST is the current flowing through the first resistor R 1 , and I RSENSE is the current flowing through the sampling resistor R SENSE . In the illustrated embodiment shown in FIG. 6 , I RSENSE equals the inductor current I L and the load current. Generally, R 1 may be integrated in an integrated circuit (IC) chip, and R SENSE is an external device. By choosing different values of R SENSE , the load current is chosen. As the amplifier is not an ideal amplifier, the voltage level on the second terminal of the first resistor R 1 and the second terminal of the sampling resistor R SENSE may not be absolutely the same. Consequently an error voltage Δ may be generated. The error voltage Δ may be actively set according to the requirement, so as to make

I FIRST =I RSENSE ×R SENSE /R 1×Δ/ R 1  (3)

Wherein, Δ/R 1 is a direct current (DC) component, which represents that the first current I FIRST has an initial current value.

For better explaining the present invention, it is assumed in the following analysis that

I FIRST =K×I SENSE   (4)

Wherein, K may be a constant number or a function. For example, in the illustrated embodiment, K=R SENSE /R 1 .

A compensating circuit 601 generates a compensating signal 602 . In one embodiment, the compensating circuit 601 comprises: a low-pass filter 603 ; a first amplifier 604 , having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to a hysteresis voltage generating node B of control circuit 103 through the low-pass filter 603 , and wherein the second input terminal is coupled to a first reference voltage REF, and further wherein the output terminal generates the compensating signal 602 . In the illustrated embodiment, the compensating signal 602 is a current signal. However in other embodiments, the compensating signal 602 may be a voltage signal. The compensating signal 602 is coupled to the first current signal IFIRST. The term “couple” hereby may indicate the two signals may be combined through one or more of following method: adding, subtracting, multiplying, dividing, integrating, differentiating, or amplifying, abstracting, algebraic manipulating one or two of the signals before the above operation. The current control signal may be a positive signal or a negative signal, and may be a sinking current or a sourcing current. In one embodiment, a transconductance amplifier may be applied as the first amplifier.

Circuit system 600 comprises a first reference signal REF. In one embodiment, REF may be a reference current or voltage with low thermal drift. In another embodiment, REF may be a current or a voltage proportional to absolute temperature (PTAT). In yet another embodiment, REF may be a current or a voltage inverse proportional to absolute temperature (IPTAT). For better understanding, it is assumed that REF is a voltage signal in the following analysis.

Control circuit 103 generates the control signal V CON according to the first current signal I FIRST , the compensating signal 602 and the first signal REF. In one embodiment, control circuit 103 comprises a hysteresis generator 606 which generates a hysteresis voltage, wherein the hysteresis voltage has a high level peak voltage V B1 and a low level peak voltage V B2 . The hysteresis generator 606 comprises: a second resistor R 2 , coupled between two hysteresis generating nodes B and C; a third resistor R 3 , coupled between node C and the reference ground terminal GND; and a second switch M 2 , coupled to the third resistor R 3 in parallel and controlled by the control signal V CON . In one embodiment, the second switch M 2 may be an NMOS. Since the on-state resistance of the NMOS is much lower than the third resistor R 3 , it may be considered that the voltage level on node C is at ground level.

A first comparator C 1 has a first input terminal coupled to the hysteresis generator 606 . In one embodiment, the first input terminal is coupled to node B, configured to change the voltage level of the control signal V CON . A second input terminal of the first comparator C 1 is coupled to the first reference signal REF. An output terminal of the first comparator C 1 generates the control signal V CON . A driver D 1 may be further coupled to an output terminal of the first comparator C 1 , configured to convert the control signal V CON to a driving signal.

Once the control circuit 103 is operating normally, when the control signal V CON is at high level, the current on the load increases gradually, and the voltage level of node B also increases gradually. At this moment, since the second switch M 2 is turned on, the voltage level of node C is at ground level. When the voltage level of node B reaches V REF (the voltage level of the first reference signal REF), the comparator C 1 generates a low level signal to turn M 1 and M 2 off. The compensating current I COM and the first current signal I FIRST are coupled together and then flows through the second resistor R 2 . When the comparator is inversed, supposing that the value of the inductor current I SENSE is I TH1 , then

( I COM K×I TH1 )× R 2= V REF   (5)

According to formula (5),

I TH1 =( V REF /R 2− I COM )/ K   (6)

As shown in FIG. 7 , once the second switch M 2 is suddenly turned off, because the current flows through the third resistor R 3 , the voltage level of node C steps up, and the voltage level of node B increases to the high level peak voltage V B1 ,

V B1 =( R 3+ R 2)× V REF /R 2  (7)

The variance ΔV B1 of the voltage level of node B is

ΔV B1 =V B −V REF =R 3× V REF /R 2  (8)

Once the voltage level of node B steps up, the control signal V CON is maintained at low level. As the first switch M 1 is turned off, the current flows along the loop of the load, the inductor L, and the rectifier Rectifier. The inductor current I SENSE continuously decreases, and the first current signal I FIRST also continuously decreases. Thus the voltage level of node B falls down. When the voltage level of node B falls to the V REF , the comparator C 1 is inversed and generates a high level signal. The switches M 1 and M 2 are turned on again. At this moment, the compensating current I COM and the first current signal I FIRST are coupling together and then flow through the second resistor R 2 and the third resistor R 3 . Supposing when the comparator C 1 is inversed, the value of inductor current I SENSE is I TH2 , then,

( I COM +K×I TH2 )×( R 3+ R 2)= V REF   (9)

According to formula (9),

I TH2 =( V REF /( R 3+ R 2)− I COM )/ K   (10)

Once the second switch M 2 suddenly is turned on, because the current flows through M 2 , the voltage level of node B steps down to the low level peak voltage V B2 , where

V B2 =R 2× V REF /( R 3+ R 2)  (11)

The variance ΔV B2 of the voltage level of node B is

Δ V B2 =V REF −V B2 =R 3× V REF /( R 3+ R 2)  (12)

The average voltage value /V B of node B is

/ V B =V REF ×[1+Δ V B1 ×(1− D )/2−Δ V B2 ×D/ 2]  (13)

Wherein, D is the duty cycle. The function of the third resistor R 3 is to provide a hysteresis voltage, and in one embodiment, R 2 >>R 3 and thus ΔV B1 ≈ΔV B2 . Therefore, when the duty cycle D is lower than 50%, the average voltage value /V B of node B is lower than V REF . In one embodiment, if the influence of R 3 is ignored, and ΔV B1 >ΔV B2 is strictly complied, then

Δ V B1 ×(1− D EXACT )− V B2 ×D EXACT =0  (14)

that is,

D EXACT =ΔV B1 /(Δ V B1 +ΔV B2 )=( R 3+ R 2)/( R 3+2× R 2)  (15)

At this moment, the compensating signal I COM generated by the compensating circuit 601 is zero. When the duty cycle D is lower than D EXACT , the average voltage value /V B of node B is larger than voltage V REF . When the duty cycle D is larger than D EXACT , the average voltage value /V B of node B is smaller than voltage V REF .

In certain embodiments, a low-pass filter 603 is applied to output the average voltage value of node B to a node D. In one embodiment, the sourcing current from the amplifier 604 to the control circuit 103 is defined as positive current, and the sinking current which the amplifier 604 sinks from node B is defined as negative current. In the illustrated embodiment, the first amplifier 604 is a transconductance amplifier. A positive input terminal of the transconductance amplifier 604 is coupled to the first reference signal REF, and a negative input terminal is coupled to node D. Thus the generated current control signal I COM

I COM =G M ×(/ V B −V REF )  (16)

Wherein, G M is the transconductance of the transconductance amplifier, which represents the capability of transmitting the differential voltage of the two input terminals to current signal.

According to above analysis, it may be concluded that, when the duty-cycle is lower than 50%, the average voltage /V B of node B may be larger than reference voltage V REF . As I COM is a positive signal, the current flows into the control circuit through node B. When the duty cycle is larger than 50%, the average voltage /V B of node B is smaller than V REF . As a result I COM is a negative signal and the amplifier sinks current from node B.

According to formula (6) and (10), the average load or inductor current /I SENSE is:

/ I SENSE =( I TH1 +I TH2 )/2=(REF/( R 3+ R 2)+REF/ R 2−2× I COM )/ K/ 2  (17)

When the duty cycle is lower than 50%, I COM is a positive signal, and /I SENSE decreases. When the duty cycle is larger than 50%, I COM is a negative signal and /I SENSE increase. As a result, the drift error of the average inductor current /I L described above is prohibited.

A first switch M 1 is coupled between the switch terminal SW and the reference ground terminal GND, turned ON and OFF according to the control signal V CON . In one embodiment, NMOS or IGBT may be applied as the first switch M 1 . In the illustrated embodiment, the control terminals of the switches M 1 and M 2 are together coupled to the output of the driver D 1 . In other embodiments, the control terminals of the two switches may be coupled to different terminals. For example, the control terminal of the switch M 2 may be coupled to the control signal directly without the driver.

FIG. 8 illustrates a circuit system 800 according to another embodiment of the present invention. Seen in FIG. 8 , compared with circuit system 600 , an alternative compensating circuit 801 replaces compensating circuit 601 , configured to generate a compensating signal 802 . In one embodiment, compensating circuit 801 comprises a low-pass filter 803 and a first amplifier 804 comprising a first input terminal, a second input terminal and an output terminal. Wherein the first input terminal is coupled to the output terminal of the first capacitor C 1 through the low-pass filter 803 , and wherein the second input terminal is coupled to a second reference voltage V CC /2, wherein V CC is the internal power supply voltage which equals the high level signal of comparator or inverter output, and the output terminal provides the compensating signal I COM . In the illustrated embodiment, the first amplifier 804 is a transconductance amplifier.

The operation process flow of circuit system is described in the following text. When the output of the comparator C 1 passes through the low-pass filter 803 , if the duty cycle is smaller than 50%, the voltage on the negative input terminal of the comparator C 1 is smaller than V CC /2. The transconductance amplifier 804 sources current to node B, that is, I COM is a positive current signal. According to formula (17), the average load or inductor current /I SENSE decreases. When the duty cycle is larger than 50%, I COM is a negative current signal, and /I SENSE increases. As a result, the drift error of the average current /I L described above is prohibited.

FIG. 9 illustrates a circuit system 900 according to yet another embodiment of the present invention. Seen in FIG. 9 , compared with circuit system 600 , an alternative compensating circuit 901 replaces compensating circuit 601 , configured to generate a compensating signal 902 . V 902 represent the voltage level of compensating signal 902 . In one embodiment, compensating circuit 901 comprises a low-pass filter 903 and a first amplifier 904 . The first amplifier 904 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first capacitor C 1 through the low-pass filter 903 , and wherein the second input terminal is coupled to the first reference voltage REF; a fourth resistor R COM , coupled between the first reference signal REF and an output terminal of the first amplifier 904 ; a first capacitor C COM , coupled between the first input terminal and the output terminal of the first amplifier 904 . The output terminal of amplifier 904 provides a compensating signal. In the illustrated embodiment, first amplifier 904 is a transconductance amplifier.

The operation process flow of circuit system 900 is described in the following text. Similar to the circuit system 600 , according to formula (13), when the duty cycle is smaller than 50%, the average voltage /V B of node B is larger than the reference voltage V REF , that is, the voltage V E of node E is larger than V REF . The transconductance amplifier 904 sinks current, and the voltage level V 902 of compensating signal 902 decreases. While the duty cycle is larger than 50%, the average voltage /V B of node B is smaller than the reference voltage V REF , and the voltage level V 902 increases.

According to formula (6) and (10), if I COM is set to zero, and if V 902 replaces V REF , then the high level peak voltage I TH3 and low level peak voltage I TH4 is

I TH3 =V 902 /R 2 /K   (18)

I TH4 =V 902 /( R 3+ R 2)/ K   (19)

Therefore, the average load or inductor current /I L 3 is

/ I L3 =( I TH1 +I TH2 )/2=[ V 902 /( R 3+ R 2)+ V 902 /R 2]/ K/ 2

When the duty cycle is smaller than 50%, V 902 decreases so that I L3 decreases. When the duty cycle is larger than 50%, V 902 increases so that I L3 increases. As a result, the drift error of the average current /I L described above is prohibited.

The present invention introduces a compensating circuit into circuit system, configured to provide a precise load current. The compensating circuit is not limited by the above embodiments. In other embodiments, other suitable circuit structure may also be applied as compensating circuit.

Similarly, the above embodiments are primary illustrative practiced for the issue of duty cycle. However, other embodiments may be practiced for the issue of propagation delay of circuit. For an instance, a current sense circuit may have a large propagation delay at low current, and a small propagation delay at high current. The compensating circuit may detect a signal which indicates the current and compensate the control circuit loop. These applications also are included in the scope of the present invention.

The above description and discussion about specific embodiments of the present invention is for purposes of illustration. However, one with ordinary skill in the relevant art should know that the invention is not limited by the specific examples disclosed herein. Variations and modifications can be made on the apparatus, methods and technical design described above. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.