Transistor device and manufacturing method thereof

1. Technical Field

The disclosure relates in general to a semiconductor device and a manufacturing method thereof, and more particularly to a transistor device and a manufacturing method thereof.

2. Description of the Related Art

With the development of semiconductor technology, varied semiconductor elements are invented. Those semiconductor elements are widely used in electric devices.

Transistor device is a solid state transistor element, used for being a voltage amplifier, an audio amplifier, a radio amplifier, a regulated power element or a switch. The transistor device has advantages of small volume, high efficiency, long life and high speed, so that the transistor device is widely used in electric devices. In recently year, a high voltage and high power transistor device has been invented.

The disclosure is directed to a transistor device and a manufacturing method thereof. A shallow trench isolation has a floating diffusion island, so that the breakdown voltage can be increased and the turn-on-resistance (Ron) can be reduced.

According to a first embodiment of the present disclosure, a transistor device is provided. The transistor comprises a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well.

According to a second embodiment of the present disclosure, a manufacturing method of a transistor device is provided. The manufacturing method of the transistor device comprises the following steps. A substrate is provided. A first well is formed in the substrate. A second well is formed in the substrate. A shallow trench isolation (STI) having at least a floating diffusion island is formed in the second well. A source is formed in the first well. A drain is formed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. A gate is formed above the first well and the second well. The gate partially overlaps the first well and the second well.

The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiments. The following description is made with reference to the accompanying drawings.

FIG. 1 shows a top view of a transistor device of one embodiment;

FIG. 2 shows a cross-sectional view of the transistor device of FIG. 1 along a cutting line 2 - 2 ; and

FIGS. 3A to 3E show a flowchart of a manufacturing method of the transistor device according to one embodiment;

FIG. 4 shows a cross-sectional view of another preferred embodiment of transistor device.

Several embodiments are disclosed below for elaborating the invention. The following embodiments are for the purpose of elaboration only, not for limiting the scope of protection of the invention. Besides, secondary elements are omitted in the following embodiments to highlight the technical features of the invention.

Referring to FIGS. 1 to 2 , FIG. 1 shows a top view of a transistor device 100 of one embodiment, and FIG. 2 shows a cross-sectional view of the transistor device 100 of FIG. 1 along a cutting line 2 - 2 . The transistor device 100 includes a substrate 110 , a first well 141 , a second well 142 , a shallow trench isolation (STI) 150 , a source 170 S, a drain 170 D and a gate 180 G.

The substrate 110 can be a P type silicon substrate or a N type silicon substrate, for example. The first well 141 and the second well 142 can be a P type well doped boron (B) or a N type well doped phosphorous (P), arsenic (As) or antimony (Sb), for example. In the present embodiment, the substrate 110 is a P type silicon substrate, and the first well 141 and the second well 142 are a P type well and a N type well respectively. The first well 141 and the second well 142 are disposed in the substrate 110 . Referring to FIG. 2 , the first well 141 and the second well 142 can be separated. In another embodiment, the first well 141 and the second well 142 can be connected.

Some STI 150 are disposed in the second well 142 and are surrounded by the second well 142 . The STI 150 has at least one floating diffusion island 150 a . Referring to FIG. 1 , the STI 150 has several floating diffusion islands 150 a . The floating diffusion islands 150 a are located along a straight line and the floating diffusion islands 150 a are not connected with each other.

The source 170 S is disposed in the first well 141 , and the drain 170 D is disposed in the second well 142 . The source 170 S and the drain 170 D can be N type heavily doping regions or P type heavily doping regions, for example. The gate 180 G is disposed above the first well 141 and the second well 142 and partially overlaps the first well 141 and the second well 142 . The material of the gate 180 G can be polysilicon, for example. The source 170 S, the drain 170 N and the gate 180 G form a laterally diffused metal oxide semiconductor (LDMOS).

Regarding the floating diffusion islands 150 a , the floating diffusion islands 150 a are disposed in the STI 150 and are not disposed below the STI 150 . A channel between the drain 170 D and the source 170 S would not be lengthened, so that the turn-on-resistance (Ron) can be keep at a low level.

Moreover, each of the floating diffusion islands 150 a is located between the drain 170 D and the source 170 S, such than the break voltage can be increased and the Ron can be reduced effectively.

Referring to FIG. 1 , regarding to the STI 150 and each floating diffusion island 150 a , the width W 1 of the STI 150 is about three times the width W 2 of each floating diffusion island 150 a . Each floating diffusion island 150 a is substantially located at the center of the STI 150 . That is to say, the ratio of the width W 3 , the width W 2 and the width W 4 is about 1:1:1.

Further, regarding to FIG. 1 , the number of the floating diffusion islands 150 a can be larger than or equal to two, and form several island structures. In one embodiment, the number of the floating diffusion island 150 a can be one, and form a single elongate structure. If the floating diffusion islands 150 a are island structures, then the structural strength of the STI 150 can be kept. If the floating diffusion island 150 a is a single elongate structure, the function of the floating diffusion island 150 a can be brought fully.

Referring to FIG. 1 , in the present embodiment, the floating diffusion islands 150 a are island structures. The distance D 1 between two adjacent floating diffusion islands 150 a is larger than or equal to 0.3 micrometer (um) to keep the structural strength of the STI 150 . However, according to different process generations or different design rules, the distance D 1 can be changed and is not limited to 0.3 um.

Moreover, referring to FIG. 2 , regarding the depth L 1 of the floating diffusion islands 150 a , if the depth L 1 of the floating diffusion islands 150 a is larger, then the function of the floating diffusion islands 150 a can be brought more. However, the depth L 1 of the floating diffusion islands 150 a must be less than the thickness L 2 of the STI 150 to avoid to change the channel between the drain 170 D and the source 170 S.

Referring to FIG. 2 , regarding to the relationship between the gate 180 G and the floating diffusion islands 150 a , the gate 180 G and the floating diffusion islands 150 a can be separated without any overlapping, or partially overlapped. If the gate 180 G and the floating diffusion islands 150 a are partially overlapped, the breakdown voltage and the Ron will be effected accordingly.

Please referring to FIG. 2 , regarding to the concentration and the electric type of the floating diffusion islands 150 a , the transistor device 100 further includes a deep well 130 and a buried layer 120 . The deep well 130 and the buried layer 120 can be N type or P type, for example. In the present embodiment, the deep well 130 and the buried layer 120 are N type. The deep well 130 is disposed above the substrate 110 . The second well 142 and the first well 141 are disposed in the deep well 130 . The electric type of the floating diffusion islands 150 a and that of the drain 170 D can be different or the same. It is proper that the electric type of the floating diffusion islands 150 a is the same with the drain 170 D. The concentration of the floating diffusion islands 150 a and the deep well 130 have the same order of magnitude.

Please referring to FIGS. 3A to 3E , FIGS. 3A to 3E show a flowchart of the manufacturing method of the transistor device according to the embodiment. Firstly, referring to FIG. 3A , the substrate 110 is provided. Next, the buried layer 120 and the deep well 130 are formed in the substrate 110 . Afterwards, the first well 141 is formed in the deep well 130 . Then, the second well 142 is formed in the deep well 130 . In one embodiment, after providing the substrate 110 , the buried layer 120 is formed at the top of the substrate 110 . Then an epitaxy layer is formed above the buried layer 120 for disposing the deep well 130 , the first well 141 and the second well 142 .

Afterwards, referring to FIG. 3B , the STI 150 is formed in the second well 142 and gaps 150 b between the STI 150 are defined simultaneously.

Then, referring to FIG. 3C , the floating diffusion islands 150 a are formed in the gaps 150 b by using a mask (not shown) to define an implanting area. In this step, the depth L 1 of the floating diffusion island 150 a is controlled to be less than the thickness L 2 of the STI 150 by controlling the process time and the energy.

Afterwards, referring to FIG. 3D , the source 170 S and a heavily doping region 170 are formed in the first well 141 and the drain 170 D is formed in the second well 142 by using a mask (not shown) to define an implanting area.

Afterwards, referring to FIG. 3E , the gate 180 G is formed above the first well 141 and the second well 142 . After those steps are performed, the transistor device 100 is manufactured.

In the present embodiment, it is no needed to increase the manufacturing cost of the manufacturing method of the transistor device 100 . The floating diffusion islands 150 a can be disposed in the STI 150 during the manufacturing method, such that the breakdown voltage can be increased and the Ron can be decreased.

While the disclosure has been described by way of example and in terms of the exemplary embodiments, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.