Reference current source circuit and system

1. Field of Invention

The present invention relates to a reference current source circuit and its system, and more particularly to a reference current source circuit without externally attached resistors and its system.

2. Description of Related Arts

Referring to FIG. 1 , a conventional reference current source circuit is illustrated. The conventional reference depends on a resistor R 31 and a reference current value thereof equals a reference voltage Vref of a reference voltage terminal divided by the resistance of the resistor R 31 , so the reference current value is related to an absolute value of the resistor. In semiconductor arts, an absolute value of a resistor can have a positive or negative deviation of 10%. Thus, in order to generate a highly precise reference current source, it is required to externally attach a resistor or to rectify the resistance value through a calibration mechanism of a back-end test, whereas both add up a cost of a chip.

Based on above analysis, the conventional reference current source needs an externally attached resistor to generate the highly precise reference current source and thus increases the cost of the chip.

Based on above content, it is necessary to provide a reference current source circuit omitting any externally attached resistor and its system.

A reference current source circuit comprises a reference voltage generating module, a voltage buffer connected to the reference voltage generating module, an equivalent resistor connected to the voltage buffer, a filter capacitor connected to the voltage buffer, a current mirror module connected to the voltage buffer and a reference current outputting terminal connected to the current mirror module. The voltage buffer comprises an operational amplifier and a first field-effect transistor (FET) connected to the operational amplifier. The current mirror module comprises a second FET and a third FET connected to the second FET. The equivalent resistor comprises an oscillator, a fourth FET connected to the oscillator, a fifth FET connected to the oscillator and a capacitor connected to the fourth FET and the fifth FET. The oscillator generates a clock signal whose frequency is related to a discharging and charging capacitor in the oscillator to control charging and discharging of the capacitor in the equivalent resistance. The reference current outputting terminal outputs a reference current related to a capacitance ratio of the capacitor to the charging and discharging capacitor.

A reference current source system comprises a reference voltage generating module for generating a reference voltage, a voltage buffer connected to the reference generating module, an equivalent resistor connected to the voltage buffer, a filter capacitor connected to the voltage buffer, a current mirror module connected to the voltage buffer and a reference current outputting terminal connected to the current mirror module. The reference current outputting terminal outputs a reference current only related to the capacitance ratio.

Compared with conventional arts, the reference current source circuit and system of the present invention output the reference current only related to the capacitance ratio, generate the reference current without any externally attached resistance, has a simple structure and also reduce a chip cost.

These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

FIG. 1 is a circuit diagram of a conventional reference current source circuit.

FIG. 2 is a block diagram of a reference current source system according to a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a reference current source circuit according to the preferred embodiment of the present invention.

FIG. 4 is a circuit diagram of an oscillator in the reference current source circuit according to the preferred embodiment of the present invention.

Referring to FIGS. 2 and 3 of the drawings, a reference current source circuit and its system according to a preferred embodiment of the present invention are illustrated, comprising a reference voltage generating module VREF, a voltage buffer connected to the reference voltage generating module VREF, an equivalent resistor connected to the voltage buffer, a filter capacitor C 1 connected to the voltage buffer, a current mirror module connected to the voltage buffer and a reference current outputting terminal lout connected to the current mirror module, wherein the voltage buffer comprises an operational amplifier OP and a first FET M 1 connected to the operational amplifier OP; the current mirror module comprises a second FET M 2 and a third FET M 3 connected to the second FET M 2 ; the equivalent resistor comprises an oscillator OSC, a fourth FET M 4 connected to the oscillator OSC, a fifth FET M 5 connected to the oscillator OSC and a capacitor C 2 connected to the fourth FET M 4 and the fifth FET M 5 .

The reference voltage generating module VREF is for generating a reference voltage Vref. The voltage buffer is for equalizing a source electrode voltage of the first FET M 1 with the reference voltage Vref. The filter capacitor C 1 is for eliminating high-frequency components in the reference current. The oscillator OSC is for generating a clock signal Fosc to control charging and discharging of the capacitor C 2 . The current mirror module is for outputting the reference current through the reference current outputting terminal lout.

According to the preferred embodiment of the present invention, specific connections of the reference current source circuit are following. The reference voltage generating module VREF and a non-inverting inputting terminal of the operational amplifier OP are connected; a reversed inputting terminal of the operational amplifier, a source electrode of the first FET M 1 , a source electrode of the fourth FET M 4 and a first terminal of the filter capacitor C 1 are all connected with each other; and an outputting terminal of operational amplifier OP and a gate electrode of the first FET M 1 are connected with each other. A drain electrode of the first FET M 1 is connected to a gate electrode and a drain electrode of the second FET M 2 and a gate electrode of the third FET M 3 ; a drain electrode of the third FET M 3 and the reference current outputting terminal Iout are connected with each other; and a source electrode of the second FET M 2 and a source electrode of the third FET M 3 are both connected to a power source terminal AVD. A gate electrode of the fourth FET M 4 and a gate electrode of the fifth FET M 5 are both connected to the oscillator OSC; a drain electrode of the fourth FET M 4 is connected to a drain electrode of the fifth FET M 5 and a first terminal of the capacitor C 2 ; and a source electrode of the fifth FET M 5 , a second terminal of the capacitor C 2 and a second terminal of the filter capacitor C 1 are all connected to a grounding terminal AVS.

Referring to FIG. 4 , according to the preferred embodiment of the present invention, a circuit of the oscillator OSC is illustrated, comprising a sixth FET M 6 , a seventh FET M 7 , an eighth FET M 8 , a ninth FET M 9 , a tenth FET M 10 , an eleventh FET M 11 , a twelfth FET M 12 , a thirteenth FET M 13 , a fourteenth FET M 14 , a fifteenth FET M 15 , a sixteenth FET M 16 , a seventeenth FET M 17 , a nineteenth FET M 19 , a twentieth FET M 20 , a twenty-first FET M 21 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a charging and discharging capacitor C 3 in an internal part of the oscillator OSC, a first comparer COM 1 , a second comparer COM 2 and a RS flip-flop.

Specific connections of the circuit of the oscillator OSC are following. A gate electrode and a drain electrode of the sixth FET M 6 , a gate electrode of the seventh FET M 7 , a gate electrode of the eighth FET M 8 and a drain electrode of the thirteenth FET M 13 are connected with each other. A drain electrode of the seventh FET M 7 , a gate electrode and a drain electrode of the fourteenth FET M 14 and a gate electrode of the thirteenth FET M 13 are connected with each other. A drain electrode of the eighth FET M 8 is connected to a first terminal of the second resistor R 2 and a non-inverting inputting terminal INP of the first comparer COM 1 . A gate electrode and a drain electrode of the ninth FET M 9 , a gate electrode of the tenth FET M 10 , a gate electrode of the eleventh FET M 11 , a gate electrode of the twelfth FET M 12 and a drain electrode of the sixteenth FET M 16 are connected with each other. A drain electrode of the tenth FET M 10 , a gate electrode and a drain electrode of the seventeenth FET M 17 and a gate electrode of the sixteenth FET M 16 are connected with each other. A drain electrode of the eleventh FET M 11 , a gate electrode and a drain electrode of the twentieth FET M 20 and a gate electrode of the twenty-first FET M 21 are connected with each other. A drain electrode of the twelfth FET M 12 and a source electrode of the eighteenth FET M 18 are connected with each other. A source electrode of the thirteenth FET M 13 and a first terminal of the first resistor R 1 are connected with each other. A gate electrode and a drain electrode of the fifteenth FET M 15 , a second terminal of the second resistor R 2 and a reversed inputting terminal INN of the second comparer COM 2 are connected with each other. A source electrode of the sixteenth FET M 16 and a first terminal of the third resistor R 3 are connected with each other. A gate electrode of the eighteenth FET M 18 and a gate electrode of the nineteenth FET M 19 are both connected to a first outputting terminal Q of the RS flip-flop; and a drain electrode of the eighteenth FET M 18 , a drain electrode of the nineteenth FET M 19 and a first terminal of the charging and discharging capacitor C 3 are all connected to a reversed inputting terminal INN of the first comparer COM 1 and a non-inverting inputting terminal INP of the second comparer COM 2 . A source electrode of the nineteenth FET M 19 and a drain electrode of the twenty-first FET M 21 are connected with each other. An outputting terminal of the first comparer COM 1 and a first inputting terminal S of the RS flip-flop are connected with each other; and an outputting terminal of the second comparer COM 2 and a second inputting terminal R of the RS flip-flop are connected with each other. A second outputting terminal QN of the RS flip-flop outputs a clock signal Fosc and sends the clock signal Fosc to a gate electrode of the fourth FET M 4 and a gate electrode of the fifth FET M 5 . A source electrode of the sixth FET M 6 , a source electrode of the seventh FET M 7 , a source electrode of the eighth FET M 8 , a source electrode of the ninth FET M 9 , a source electrode of the tenth FET M 10 , a source electrode of the eleventh FET M 11 and a source electrode of the twelfth FET M 12 are all connected to the power source terminal AVD; and a second terminal of the first resistor R 1 , a source electrode of the fourteenth FET M 14 , a source electrode of the fifteenth FET M 15 , a second terminal of the third resistor R 3 , a source electrode of the seventeenth FET M 17 , a source electrode of the twentieth FET M 20 , a source electrode of the twenty-first FET M 21 and a second terminal of the charging and discharging capacitor C 3 are all connected to the grounding terminal AVS.

According to the preferred embodiment of the present invention, working principles of the reference current source circuit are following.

The thirteenth FET M 13 and the fourteenth FET M 14 work in saturation regions and a width-length ratio thereof is K 1 .

The sixth FET M 6 and the seventh FET M 7 form a first current mirror; based on circuit working states and an omission of body effects of FETs, a current flowing through the first resistor R 1 is

wherein μ n is negative temperature coefficient; C ox is gate oxide capacitance;

( W L ) n

is a width-length ratio of the thirteenth FET M 13 .

Thus a voltage difference between the two terminals of the third resistor R 3 is

Δ V=I 1 *R 2,

and the sixteenth FET M 16 and the seventeenth FET M 17 work in sub-threshold regions and a width-length thereof is K 2 .

The ninth FET M 9 and the tenth FET M 10 form a second current mirror; based on the circuit working states and the omission of body effects of FETs, a charging and discharging current flowing through the charging and discharging capacitor C 3 is

wherein is a constant related to arts and V T is a positive temperature coefficient.

Thus a clock frequency of the clock signal Fosc outputted by the oscillator OSC is

wherein ΔT is a half of a clock cycle; V T can be completely compensated by designs; and the first resistor R 1 , the second resistor R 2 and the third resistor R 3 are matched resistances. And thus the clock frequency of the clock signal Fosc outputted by the oscillator OSC is only inversely proportional to the charging and discharging capacitor C 3 and irrelevant to the resistances.

Based on above analysis, the oscillator OSC generates the clock signal Fosc to control charging and discharging of the capacitor C 2 and the frequency F of the clock signal Fosc is only related to the charging and discharging capacitor C 3 , i.e.,

wherein K is a constant.

When the clock signal Fosc is at a low level, the voltage buffer comprising the operational amplifier OP and the first FET M 1 charges the capacitor C 2 through the fourth FET M 4 ; when the clock signal Fosc is at a high level, the capacitor C 2 discharges through the fifth FET M 5 , and thus a resistance value Ron of the equivalent resistor is

A reference current I outputted by the reference current outputting terminal lout is

Thus the reference current I outputted by the reference current outputting terminal lout is only related to a capacitance ratio of the capacitor C 2 to the charging and discharging capacitor C 3 and irrelevant to the resistances, i.e., needs no externally attached resistance.

Based on above analysis, the reference current source circuit and system of the present invention generate a clock signal only related to capacitors through the oscillator to control the charging and the discharging of the capacitors, in such a manner that equivalent impedance only related to a capacitance ratio is formed to generate a reference current.

The reference current source circuit and system of the present invention output the reference current only related to the capacitance ratio. A precision of the capacitance ratio in a semiconductor art is far higher than a precision of an absolute value of the capacitors and the resistances. Thus the reference circuit source circuit and system of the present invention need no externally attached resistor to generate the reference current, have simple structures and reduce costs of chips.

One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.