Pixel structure and display system utilizing the same

This application claims priority of Taiwan Patent Application No. 100118415, filed on May 26, 2011, the entirety of which is incorporated by reference herein.

1. Field of the Invention

The invention relates to a pixel structure, and more particularly to a pixel structure of a display system.

2. Description of the Related Art

Because cathode ray tubes (CRTs) are inexpensive and provide high definition, they are utilized extensively in televisions and computers. With technological development, new flat-panel displays have continually been developed in recent years. The flat-panel displays are widely used as they possess the favorable advantages of having a thin profile and light weight.

Generally, each flat-panel display comprises a display panel comprising various pixels. Each pixel comprises a driving transistor and a luminous element. The driving transistor generates a driving current according to an image signal. The luminous element displays correspond to brightness according to the driving current.

However, the driving transistors in the different pixels may comprise different threshold voltages because the driving transistors are affected by the manufacturing thereof. When some pixels receive the same image signal, the corresponding driving transistors may generate different driving currents such that corresponding luminous elements display different brightness.

In accordance with an embodiment, a pixel structure comprises a first switching transistor, a setting unit, a capacitor, a driving transistor, a second switching transistor and a luminous element. The first switching transistor transmits a data signal to a first node according to a scan signal. The setting unit controls the voltage level of the first node and the voltage level of a second node according to the scan signal and a discharging signal. The capacitor is coupled between the first and the second nodes. The driving transistor comprises a first threshold voltage and a gate coupled to the second node. The second switching transistor comprises a gate receiving an emitting signal. The luminous element is coupled to the driving transistor and the second switching transistor in series between a first operation voltage and a second operation voltage. During a first period, the setting unit controls the voltage level of the first node to equal to a first reference voltage and controls the voltage level of the second node to equal to a second reference voltage, and the first reference voltage exceeds the second reference voltage. During a second period, the first switching transistor transmits the first data signal to the first node, and the setting unit controls the voltage level of the second node to equal to a difference between the first operation voltage and the first threshold voltage. During a third period, the setting unit controls the voltage level of the first node to equal to the first reference voltage and floats the second node.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an exemplary embodiment of a display system;

FIGS. 2A , 3 and 4 are schematic diagrams of other exemplary embodiments of a pixel structure; and

FIG. 2B is a timing diagram of an exemplary embodiment of the invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is a schematic diagram of an exemplary embodiment of a display system. The display system 100 comprises a driving module 110 and pixels P 11 ˜P mn . The driving module 110 provides signals to the pixels P 11 ˜P mn . In this embodiment, the driving module 110 comprises a scan driver 111 , a data driver 113 and a control driver 115 .

The scan driver 111 provides scan signals S 1 ˜S n to the pixels P 11 ˜P mn . The data driver 113 provides data signals D 1 ˜D m to the pixels P 11 ˜P mn . The pixels P 11 ˜P mn receive the data signals D 1 ˜D m according to the scan signals S 1 ˜S n and display corresponding brightness according to the data signals D 1 ˜D m . The control driver 115 provides a discharging signal S DIS , an emitting signal S EM , reference voltages S REF1 , S REF2 , and operation voltages PVDD and PVEE to the pixels P 11 ˜P mn such that driving transistors of the pixels P 11 ˜P mn generate driving currents and each driving current is not affected by the threshold voltage of the corresponding driving transistor.

FIG. 2A is a schematic diagram of an exemplary embodiment of a pixel structure. Since the circuits of the pixels P 11 ˜P mn are the same, the pixel P 11 is given as an example. As shown in FIG. 2A , the pixel P 11 comprises switching transistors T SW1 , T SW2 , a setting unit 20 , a capacitor Cst, a driving transistor T DR and a luminous element 24 .

The switching transistor T SW1 transmits the data signal D 1 to a node A according to the scan signal S 1 . The invention does not limit the type of the switching transistor T SW1 . In this embodiment, the switching transistor T SW1 is an N-type transistor. The N-type transistor comprises a gate receiving the scan signal S 1 , a drain receiving the data signal D 1 and a source coupled to the node A.

The capacitor Cst is coupled between the nodes A and B. The driving transistor T DR comprises a threshold voltage (Vt (DR) ). The invention does not limit the type of the driving transistor T DR . In this embodiment, the driving transistor T DR is a P-type transistor. The P-type transistor comprises a gate coupled to the node B, a source receiving the operation voltage PVDD and a drain coupled to the setting unit 20 and the switching transistor T SW2 .

The switching transistor T SW2 transmits a driving current I DP generated by the driving transistor T DR to the luminous element 24 according to the emitting signal S EM . The invention does not limit the type of the switching transistor T SW2 . In this embodiment, the switching transistor T SW2 is an N-type transistor. The N-type transistor comprises a gate receiving the emitting signal S EM , a drain coupled to the driving transistor T DR and a source coupled to the luminous element 24 .

The luminous element 24 is coupled to the driving transistor T DR and the switching transistor T SW2 in series between the operation voltages PVDD and PVEE. The invention does not limit the kind of the luminous element 24 . Any element, which is lighted according to a driving current, can serve as the luminous element 24 . In one embodiment, the luminous element 24 is an organic light emitted diode (OLED).

The setting unit 20 and the switching transistor T SW1 controls the voltage levels of the nodes A and B according to the scan signal S 1 and the discharging signal S DIS . The invention does not limit the circuit of the setting unit 20 . Any circuit, which can achieve the setting functions of the setting unit 20 , can serve as the setting unit 20 .

During a first period, the setting unit 20 controls the voltage level of the node A to equal to the reference voltage S REF1 and controls the voltage level of the node B to equal to the reference voltage S REF2 . The reference voltage S REF1 is different from the reference voltage S REF2 . In this embodiment, the reference voltage S REF1 exceeds the reference voltage S REF2 . In another embodiment, the reference voltage S REF1 is a positive value and the reference voltage S REF2 is a negative value. In other embodiments, a difference between the reference voltages S REF1 and S REF2 exceeds the threshold voltage of the driving transistor T DR .

During a second period, the switching transistor T SW1 transmits the data signal D 1 to the node A. During this period, the setting unit 20 controls the voltage level of the node B to equal to a difference between the operation voltage PVDD and the threshold voltage Vt (DR) of the driving transistor T DR .

Since the voltage level of the node A is different from the voltage level of the node B during the first period, when the voltage level of the node A is equal to the data signal D 1 during the second period, the voltage level of the node B is equal to the difference between the operation voltage PVDD and the threshold voltage Vt (DR) of the driving transistor T DR during the second period.

During a third period, the setting unit 20 controls the nodes A and B such that the voltage level of the node A is equal to the reference voltage S REF1 and the node B is in a floating state. At this period, the voltage level V B of the node B is equal to PVDD-Vt (DR) −(D 1 -S REF1 ).

During the third period, the driving transistor T DR generates the driving current I DP according to the following equation (1):

I DP =K P *( Vsg −Vt (DR) ) 2   Equation (1).

wherein K P is a parameter of the driving transistor T DR and is a pre-determined value, Vsg is a difference between the source of the driving transistor T DR and the gate of the driving transistor T DR , and Vt (DR) is the threshold voltage of the driving transistor T DR .

If we substitute the difference between the source and the gate of the driving transistor T DR with equation (1), the substituted result is expressed by the following equation (2):

I DP =K P *{PVDD−[PVDD −Vt (DR) −( D 1 −S REF1 )]−Vt (DR) } 2   Equation (2).

If we simplify equation (2):

I DP =K P *( D 1 −S REF1 ) 2   Equation (3).

According to the equation (3), the driving current I DP is not affected by the threshold voltage Vt (DR) of the driving transistor T DR . Thus, if the driving transistors of some pixels comprise the different threshold voltages and the some pixels receive the same data signals, the driving transistors of the some pixels generate the same driving currents.

The invention does not limit the circuit structure of the setting unit 20 . Any circuit, which can achieve the above functions, can serve as the setting unit 20 . In this embodiment, the setting unit 20 comprises setting transistors T 21 ˜T 23 .

The setting transistor T 21 transmits the reference voltage S REF1 to the node A according to the scan signal S 1 . The setting transistor T 22 controls the driving transistor T DR such that the gate of the driving transistor T DR is connected to the drain of the driving transistor T DR . Thus, the driving transistor T DR forms a diode connection. The setting transistor T 23 transmits the reference voltage S REF2 to the node B according to the discharging signal S DIS .

The invention does not limit the type of the setting transistors T 21 ˜T 23 . In this embodiment, the setting transistor T 21 is a P-type transistor and the setting transistors T 22 and T 23 are N-type transistors, however, the invention is not limited thereto. In other embodiments, the setting transistors T 21 ˜T 23 are P-type transistors or are N-type transistors or a portion of the setting transistors T 21 ˜T 23 are N-type transistors or P-type transistors. The method for transformation between P-type and N-type transistors is well known to those skilled in the field, thus, description thereof is omitted for brevity. FIG. 2A is given as an example to describe the connection of the setting transistors T 21 ˜T 23 .

As shown in FIG. 2A , the setting transistor T 21 comprises a gate receiving the scan signal S 1 , a source receiving the reference voltage S REF1 and a drain coupled to the node A. The setting transistor T 22 comprises a gate receiving the scan signal S 1 , a drain coupled to the node B and a source coupled to the drain of the driving transistor T DR . The setting transistor T 23 comprises a gate receiving the discharging signal S DIS , a drain receiving the reference voltage S REF2 and a source coupled to the node B.

FIG. 2B is a timing diagram of an exemplary embodiment of the invention. During the first period St 1 , the scan signal S 1 is at a low level to turn on the setting transistor T 21 . Thus, the voltage level of the node A is equal to the reference voltage S REF1 . At this period, the discharging signal S DIS is at a high level such that the setting transistor T 23 is turned on. Thus, the voltage level of the node B is equal to the reference voltage S REF2 .

During the second period St 2 , the scan signal S 1 is at the high level to turn on the switching transistor T SW1 and the setting transistor T 22 . Thus, the voltage level of the node A is equal to the data signal D 1 , and the gate of the driving transistor T DR is connected to the drain of the driving transistor T DR . Since the driving transistor T DR forms a diode connection, the voltage level of the node B is the difference between the operation voltage PVDD and the threshold voltage Vt (DR) of the driving transistor T DR .

During the third period St 3 , the scan signal S 1 is at the low level to again turn on the setting transistor T 21 . Thus, the voltage level of the node A is equal to the reference voltage S REF1 . Since the scan signal is at the low level, the setting transistors T 22 and T 23 are turned off. In this embodiment, the voltage level of the node B is equal to PVDD−Vt (DR) −(D 1 −S REF1 ). When the emitting signal S EM is at the high level, the switching transistor T SW2 is turned on to transmit the driving current I DP to the luminous element 24 . The driving current I DP is expressed by the equation (3).

During the first period St 1 , the voltage level of the node B is less than the voltage level of the node A. Thus, when the voltage level of the node A is equal to the data signal D 1 (during the second period St 2 ), the driving transistor T DR and the setting transistor T 22 normally operates due to the coupling effect of the capacitor Cst. In other words, the voltage level of the node B is equal to PVDD−Vt (DR) . Thus, the driving transistor T DR forms a diode connection. In addition, the gray level of the data signal D 1 can equal to the operation voltage PVDD. Since the maximum gray level of the data signal is not limited in PVDD−Vt (DR) , the range of the gray level is increased. In other words, when the operation voltage PVDD is reduced, the power consumption can be reduced and the range of the gray level is not affected.

FIG. 3 is a schematic diagram of another exemplary embodiment of the pixel structure. FIG. 3 is similar to FIG. 2A with the exception that the setting transistor T 33 is a P-type transistor. Since the connection between the setting transistors T 31 and T 32 is the same as the connection between the setting transistors T 21 and T 22 , description is omitted for brevity.

In this embodiment, the setting transistor T 33 is a diode connection. The setting transistor T 33 comprises a gate receiving the discharging signal S ms , a drain coupled to the node B and a source receiving the discharging signal S DIS . When the discharging signal S DIS is at the low level, the voltage level of the node B is equal to the sum of the operation voltage PVEE and the threshold voltage of the setting transistor T 33 . In one embodiment, the discharging signal S DIS is equal to the operation voltage PVEE.

FIG. 4 is a schematic diagram of another exemplary embodiment of the pixel structure. FIG. 4 is similar to FIG. 2A with the exception that the setting transistor T 43 is an N-type transistor. Since the connection between the setting transistors T 41 and T 42 is the same as the connection between the setting transistors T 21 and T 22 , description is omitted for brevity.

In this embodiment, the setting transistor T 43 is a diode connection. The setting transistor T 43 comprises a gate coupled to the node B, a drain receiving the discharging signal S DIS and a source coupled to the node B. When the discharging signal S DIS and the voltage level of the node B are sufficient to turn on the setting transistor T 43 , the voltage level of the node B is equal to the sum of the operation voltage PVEE and the threshold voltage of the setting transistor T 43 . In one embodiment, the discharging signal S DIS is equal to the operation voltage PVEE.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.