Bootstrap gate driver

This application claims the priority benefit of China application serial no. 201120158231.7, filed on May 18, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

1. Field of the Invention

The invention generally relates to a power conversion field, in particular, to a bootstrap gate driver applied in a synchronous rectification circuit/application.

2. Description of Related Art

There are two types of rectification strategies in the power conversion field, one type is diode rectification, and the other type is synchronous rectification. Diode rectification is performed based on the conduction of diodes. Synchronous rectification is performed by usually using a gate driving signal to control the operation (i.e. turned on or off) synchronous rectifiers (SRs). Synchronous rectifiers are usually implemented by MOSFETs. For low-voltage and large-current power conversion application, the forward bias (Vf) of diodes cannot be further reduced due to the characteristic of diodes, so the power loss is higher; and on the other hand, the on-resistor (Rds-on) of each synchronous rectifier is smaller, so the power loss is lower compared with diode rectification. Therefore, the conversion efficiency of the power conversion can be increased due to the power loss of synchronous rectifiers is lower.

There are conduction loss, driving loss, switching loss and body diode loss in the operating region of synchronous rectifiers. When the load is in the heavy-loading state, the load current becomes larger and makes the conduction loss become the main part of loss. When the load is in the light-loading state, the load current is small, such that the switching loss and driving loss both caused by turning on/off synchronous rectifiers become the main part of loss.

Compared with diode rectification, the saved power of synchronous rectification is lower, and the power loss related to synchronous rectification is even higher than that of diode rectification. In this case, a switching of synchronous rectification needs to be stopped/inactivated, and the body diode of the corresponding synchronous rectifier is used to perform diode rectification. Moreover, the body diode can cut off the negative reactive current loop when the load is in the light-loading state, such that inductive loss and driving loss will be significantly reduced, and the light-loading efficiency will be obviously increased.

However, the current synchronous rectification may be implemented by a couple of synchronous rectifiers to be respectively served as a high-side N-type transistor functioned as a rectifier and a low-side N-type transistor functioned as a switch. And, as shown in FIG. 1 , a traditional bootstrap gate driver 101 is used to drive the high-side N-type transistor Q H and the low-side N-type transistor Q L in response to an inputted pulse width modulation (PWM) signal PWM_I. Since the high-side N-type transistor Q H and the low-side N-type transistor Q L are alternately switched by the bootstrap gate driver 101 in response the inputted PWM signal PWM_I, so the high-side N-type transistor Q H can not be disabled when the load is in the light-loading state by directly turning off the inputted PWM signal PWM_I due to both high-side N-type transistor Q H and the low-side N-type transistor Q L are commonly used the inputted PWM signal PWM_I (if the inputted PWM signal PWM_I is turned off, the operation of the low-side N-type transistor Q L is affected). In other words, a switching of the synchronous rectification is still activated when the load is in the light-loading state, such that the light-loading efficiency will not be effectively increased in case that the traditional bootstrap gate driver 101 is applied in the synchronous rectification application.

Accordingly, the invention is directed to a bootstrap gate driver in order to solve the problem mentioned in the above “Related Art”.

An exemplary embodiment of the invention provides a bootstrap gate driver including a load indication unit, a bootstrap gate-drive unit and a drive-control unit. The load indication unit is configured to generate a load indication signal in response to a state of a load. The bootstrap gate-drive unit is configured to drive a switch-transistor circuit in response to an inputted pulse-width-modulation (PWM) signal, wherein the switch-transistor circuit has a high-side driving path and a low-side driving path. The drive-control unit is coupled to the load indication unit and the bootstrap gate-drive unit, and configured to enable or disable the high-side driving path in response to the load indication signal.

In one exemplary embodiment of the invention, the load indication unit includes a sample circuit and a determination circuit. The sample circuit is configured to detect the state of the load by a means of voltage/current sensing, so as to provide a detection signal. The determination circuit is coupled to the sample circuit, and configured to compare the detection signal with a reference signal, so as to generate the load indication signal.

In one exemplary embodiment of the invention, the switch-transistor circuit includes a high-side transistor corresponding to the high-side driving path and a low-side transistor corresponding to the low-side driving path. The bootstrap gate-drive unit includes a high-side driving circuit, a low-side driving circuit, a bootstrap diode, a bootstrap capacitor and a signal processing unit. The high-side driving circuit is coupled to the high-side transistor, and configured to drive the high-side transistor in response to a first control signal related to the inputted PWM signal. The low-side driving circuit is coupled to the low-side transistor, and configured to drive the low-side transistor in response to a second control signal related to the inputted PWM signal, wherein the first and the second control signals are complementary. An anode of the bootstrap diode is coupled to an output of the drive-control unit. A first terminal of the bootstrap capacitor is coupled to a cathode of the bootstrap diode, and a second terminal of the bootstrap capacitor is coupled between the high-side transistor and the low-side transistor. The signal processing unit is coupled to the high-side driving circuit and the low-side driving circuit, and configured to receive and process the inputted PWM signal, so as to generate the first control signal and the second control signal.

In one exemplary embodiment of the invention, the high-side driving circuit includes a first transistor and a second transistor. A control electrode of the first transistor is configured to receive the first control signal, a first electrode of the first transistor is coupled to the cathode of the bootstrap diode and the first terminal of the bootstrap capacitor, and a second electrode the first transistor is coupled to a gate of the high-side transistor. A control electrode of the second transistor is configured to receive the first control signal, a first electrode of the second transistor is coupled to the second electrode of the first transistor and the gate of the high-side transistor, and a second electrode of the second transistor is coupled to the second terminal of the bootstrap capacitor, a source of the high-side transistor and a drain of the low-side transistor.

In one exemplary embodiment of the invention, the low-side driving circuit includes a third transistor and a fourth transistor. A control electrode of the third transistor is configured to receive the second control signal, a first electrode of the third transistor is coupled to a system power, and a second electrode of the third transistor is coupled to a gate of the low-side transistor. A control electrode of the fourth transistor is configured to receive the second control signal, a first electrode of the fourth transistor is coupled to the second electrode of the third transistor and the gate of the low-side transistor, and a second electrode of the fourth transistor is coupled to a source of the low-side transistor.

In one exemplary embodiment of the invention, the first to the fourth transistors are bipolar junction transistors (BJTs). In this case, the first and the third transistors are NPN-type BJTs, and the second and the fourth transistors are PNP-type BJTs.

In one exemplary embodiment of the invention, the high-side transistor and the low-side transistor are N-type power transistors.

In one exemplary embodiment of the invention, the drive-control unit includes a fifth transistor and a sixth transistor. A control electrode of the fifth transistor is configured to receive the load indication signal, and a first electrode of the fifth transistor is coupled to a ground potential. A control electrode of the sixth transistor is coupled to a second electrode of the fifth transistor, a first electrode of the sixth transistor is coupled to the system power, and a second electrode of the sixth transistor is coupled to the anode of the bootstrap diode, wherein the second electrode of the sixth transistor is served as the output of the drive-control unit.

In one exemplary embodiment of the invention, the drive-control unit further includes a current-limiting resistor coupled between the second electrode of the fifth transistor and the control electrode of the sixth transistor.

In one exemplary embodiment of the invention, the fifth transistor is an N-type transistor, and the sixth transistor is a PNP-type BJT.

In one exemplary embodiment of the invention, when the load is in a light-loading state, the load indication signal is in a low level, such that the fifth and the sixth transistors are turned off, so as to disable the high-side driving path; and when the load is not in the light-loading state, the load indication signal is in a high level, such that the fifth and the sixth transistors are turned on, so as to enable the high-side driving path.

In one exemplary embodiment of the invention, the signal processing unit may include a first series-connected level-shift module and logic module and a second series-connected level-shift module and logic module. The first series-connected level-shift module and logic module is configured to receive and process the inputted PWM signal, so as to generate the first control signal. The second series-connected level-shift module and logic module is configured to receive and process the inputted PWM signal, so as to generate the second control signal.

In one exemplary embodiment of the invention, the provided bootstrap gate driver is at least suitable for a voltage converter such as a boost converter.

From the above, in the invention, the provided bootstrap gate driver applied in the synchronous rectification application is capable of inactivating a switching of the high-side transistor and low-side transistor (i.e. synchronous rectification) when the load is in the light-loading state, such that the light-loading efficiency can be effectively/substantially increased. And, the operation of the low-side driving path is not affected by enabling or disabling the high-side driving path.

In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary implementations accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a diagram of a traditional bootstrap gate driver for driving a high-side N-type transistor and a low-side N-type transistor in response to an inputted PWM signal.

FIG. 2 is a diagram of a bootstrap gate driver according to an exemplary embodiment of the invention.

FIG. 3A is an implementation diagram of a load indication unit in the bootstrap gate driver of FIG. 2 .

FIG. 3B is an implementation diagram of a bootstrap gate-drive unit and a drive-control unit both in the bootstrap gate driver of FIG. 2 .

FIG. 4 is a part of operation diagram of the bootstrap gate driver of FIG. 2 .

FIG. 5 is an application diagram of the bootstrap gate driver of FIG. 2 .

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Based on the demands of high efficiency, reliability and safety of the switching power supply, the invention provides a bootstrap gate driver 20 as shown in FIG. 2 . To be specific, FIG. 2 is a diagram of the bootstrap gate driver 20 according to an exemplary embodiment of the invention. Referring to FIG. 2 , the bootstrap gate driver 20 includes a load indication unit 201 , a bootstrap gate-drive unit 203 and a drive-control unit 205 . The load indication unit 201 is configured to generate a load indication signal C 32 in response to a state of a load 40 (for example, an electronic device, but not limited thereto), where a level of the load indication signal C 32 represents the state of the load 40 , for example, heavy-loading state, light-loading state, or middle-loading state, but not limited thereto.

To be specific, FIG. 3A is an implementation diagram of the load indication unit 201 in the bootstrap gate driver 20 of FIG. 2 . Referring to FIGS. 2 and 3A , the load indication unit 201 includes a sample circuit 301 and a determination circuit 303 . The sample circuit 301 is configured to detect the state of the load 40 by a means of voltage/current sensing, so as to provide a detection signal DS. The determination circuit 303 is coupled to the sample circuit 301 , and configured to compare the detection signal DS with a built-in reference signal RS, so as to generate the load indication signal C 32 .

Referring back to FIG. 2 , the bootstrap gate-drive unit 203 is configured to drive a switch-transistor circuit 30 in response to an inputted pulse-width-modulation (PWM) signal PWM_I, wherein the switch-transistor circuit 30 has a high-side driving path (loop) and a low-side driving path (loop). Moreover, the drive-control unit 205 is coupled to the load indication unit 201 and the bootstrap gate-drive unit 203 , and configured to enable or disable the high-side driving path of the switch-transistor circuit 30 in response to the load indication signal C 32 .

To be specific, FIG. 3B is an implementation diagram of the bootstrap gate-drive unit 203 and the drive-control unit 205 both in the bootstrap gate driver 20 of FIG. 2 . Referring to FIGS. 2 and 3B , in this exemplary embodiment, the switch-transistor circuit 30 may include a high-side transistor Q H corresponding to the high-side driving path and a low-side transistor Q L corresponding to the low-side driving path. The high-side transistor Q H and the low-side transistor Q L are connected in series between terminals P 1 and P 2 , and may be implemented by N-type power transistors, but not limited thereto.

The bootstrap gate-drive unit 203 may include a high-side driving circuit 305 , a low-side driving circuit 307 , a bootstrap diode D, a bootstrap capacitor C and a signal processing unit 309 . The high-side driving circuit 305 is coupled to the high-side transistor Q H , and configured to drive the high-side transistor Q H in response to a first control signal V PWM related to the inputted PWM signal PWM_I. The low-side driving circuit 307 is coupled to the low-side transistor Q L , and configured to drive the low-side transistor Q L in response to a second control signal V PWM ′ related to the inputted PWM signal PWM_I. In this exemplary embodiment, the first and the second control signals V PWM and V PWM ′ are complementary.

An anode of the bootstrap diode D is coupled to an output of the drive-control unit 205 . A first terminal of the bootstrap capacitor C is coupled to a cathode of the bootstrap diode D, and a second terminal of the bootstrap capacitor C is coupled between the high-side transistor Q H and the low-side transistor Q L . The signal processing unit 309 is coupled to the high-side driving circuit 305 and the low-side driving circuit 307 , and configured to receive and process the inputted PWM signal PWM_I, so as to generate the first control signal V PWM and the second control signal V PWM ′.

In this exemplary embodiment, each of the high-side driving circuit 305 and the low-side driving circuit 307 may be a totem pole driving circuit, but not limited thereto. In this case, the high-side driving circuit 305 may include transistors Q 1 and Q 2 , and the low-side driving circuit 307 may include transistors Q 3 and Q 4 . The transistors Q 1 to Q 4 may be implemented by bipolar junction transistors (BJTs), but not limited thereto, such that the transistors Q 1 and Q 3 are NPN-type BJTs, and the transistors Q 2 and Q 4 are PNP-type BJTs.

A control electrode (i.e. base) of the transistor Q 1 is configured to receive the first control signal V PWM , a first electrode (i.e. collector) of the transistor Q 1 is coupled to the cathode of the bootstrap diode D and the first terminal of the bootstrap capacitor C, and a second electrode (i.e. emitter) of the transistor Q 1 is coupled to a gate of the high-side transistor Q H . A control electrode (i.e. base) of the transistor Q 2 is configured to receive the first control signal V PWM , a first electrode (i.e. emitter) of the transistor Q 2 is coupled to the second electrode (i.e. emitter) of the transistor Q 1 and the gate of the high-side transistor Q H , and a second electrode (i.e. collector) of the transistor Q 2 is coupled to the second terminal of the bootstrap capacitor C, a source of the high-side transistor Q H and a drain of the low-side transistor Q L .

A control electrode (i.e. base) of the transistor Q 3 is configured to receive the second control signal V PWM ′, a first electrode (i.e. collector) of the transistor Q 3 is coupled to a system power VCC, and a second electrode (i.e. emitter) of the transistor Q 3 is coupled to a gate of the low-side transistor Q L . A control electrode (i.e. base) of the transistor Q 4 is configured to receive the second control signal V PWM ′, a first electrode (i.e. emitter) of the transistor Q 4 is coupled to the second electrode (i.e. emitter) of the transistor Q 3 and the gate of the low-side transistor Q L , and a second electrode (i.e. collector) of the transistor Q 4 is coupled to a source of the low-side transistor Q L .

In addition, the signal processing unit 309 may include a first series-connected level-shift module 311 and logic module 313 , and a second series-connected level-shift module 315 and logic module 317 . The first series-connected level-shift module 311 and logic module 313 is configured to receive and process the inputted PWM signal PWM_I, so as to generate the first control signal V PWM . The second series-connected level-shift module 315 and logic module 317 is configured to receive and process the inputted PWM signal PWM_I, so as to generate the second control signal V PWM ′. Each of the level-shift modules 311 and 315 is configured to regulate/adjust the level of the input voltage, and each of the logic modules 313 and 317 is configured to perform the logic conversion on the input digital signal.

It should be noted that, the level-shift modules 311 , 315 and the logic modules 313 , 317 are optional. Whether the level-shift modules 311 , 315 and the logic modules 313 , 317 are used or not is determined by the real design or application requirement.

On the other hand, the drive-control unit 205 may include transistors Q 5 , Q 6 and a current-limiting resistor RL. In this exemplary embodiment, the transistor Q 5 is implemented by an N-type transistor, and the transistor Q 6 is implemented by a PNP-type BJT, but not limited thereto. In this case, a control electrode (i.e. gate) of the transistor Q 5 is configured to receive the load indication signal C 32 from the load indication unit 201 , and a first electrode (i.e. source) of the transistor Q 5 is coupled to a ground potential GND.

A control electrode (i.e. base) of the transistor Q 6 is coupled to a second electrode (i.e. drain) of the transistor Q 5 through the current-limiting resistor RL. In other words, the current-limiting resistor RL is coupled between the second electrode (i.e. drain) of the transistor Q 5 and the control electrode (i.e. base) of the transistor Q 6 . A first electrode (i.e. emitter) of the transistor Q 6 is coupled to the system power VCC, and a second electrode (i.e. collector) of the transistor Q 6 is coupled to the anode of the bootstrap diode D. In this exemplary embodiment, the second electrode (i.e. collector) of the transistor Q 6 may be served/seen as the output of the drive-control unit 205 , and the control electrode (i.e. gate) of the transistor Q 5 may be served/seen as an input of the drive-control unit 205 .

Herein, it should be noted that, in this exemplary embodiment, when the load 40 is in the light-loading state, the load indication signal C 32 is in a low level, such that the transistors Q 5 , Q 6 are simultaneously turned off, so as to disable the high-side driving path of the switch-transistor circuit 30 . Moreover, when the load 40 is not in the light-loading state (for example, in the heavy-loading state, or the middle-loading state, but not limited thereto), the load indication signal C 32 is in a high level, such that the transistors Q 5 , Q 6 are simultaneously turned on, so as to enable the high-side driving path of the switch-transistor circuit 30 .

Herein, the switching of the high-side transistor Q H and the low-side transistor Q L is explained as below in case that the load 40 is not in the light-loading state, for example, the heavy-loading state, or the middle-loading state, but not limited thereto.

When the load 40 is not in the light-loading state, the load indication unit 201 would generate the load indication signal C 32 with high level, so the transistors Q 5 , Q 6 are simultaneously turned on. In this case, the system power VCC can be provided to the anode of the bootstrap diode D and the low-side driving circuit 307 , so the charging path of the bootstrap capacitor C can be established. Since the system power VCC can be provided to the anode of the bootstrap diode D and the low-side driving circuit 307 , so the high-side driving path and the low-side driving path of the switch-transistor circuit 30 can be enabled in response to the enabling of the high-side driving circuit 305 and the low-side driving circuit 307 .

In case that the system power VCC can be provided to the anode of the bootstrap diode D and the low-side driving circuit 307 , when the second control signal V PWM ′ is in the high level, the transistor Q 3 is turned on, so the gate of the low-side transistor Q L is coupled to the system power VCC. In this case, the low-side transistor Q L would be turned on, and the bootstrap capacitor C is charged by the power system VCC. Moreover, when the second control signal V PWM ′ is in the low level, the transistor Q 4 is turned on, so the gate and the source of the low-side transistor Q L are coupled with each other. In this case, the low-side transistor Q L would be turned off.

In case that the system power VCC can be provided to the anode of the bootstrap diode D and the low-side driving circuit 307 , when the first control signal V PWM is in the high level, the transistor Q 1 is turned on, so the bootstrap capacitor C is coupled across the gate and the source of the high-side transistor Q H . In this case, the high-side transistor Q H may be turned on in response to the voltage on the bootstrap capacitor C (here, assuming the voltage on the bootstrap capacitor C is greater than the threshold voltage of the high-side transistor Q H ). However, if the voltage on the bootstrap capacitor C is controlled to less than the threshold voltage of the high-side transistor Q H , so the high-side transistor Q H may be turned off. In other words, when the first control signal V PWM is in the high level, whether the high-side transistor Q H is turned on or not is determined by the voltage on the bootstrap capacitor C.

Moreover, when the first control signal V PWM is in the low level, the transistor Q 2 is turned on, so the gate and the source of the high-side transistor Q H are coupled with each other. In this case, the high-side transistor Q H would be turned off.

On the other hand, the switching of the high-side transistor Q H and the low-side transistor Q L is explained as below in case that the load 40 is in the light-loading state.

When the load 40 is in the light-loading state, the load indication unit 201 would generate the load indication signal C 32 with low level, so the transistors Q 5 , Q 6 are simultaneously turned off. In this case, the system power VCC can not be provided to the anode of the bootstrap diode D, and it only can be provided to the low-side driving circuit 307 , so the charging path of the bootstrap capacitor C can not be established. Since the system power VCC can not be provided to the anode of the bootstrap diode D, so the high-side driving path of the switch-transistor circuit 30 is disabled in response to the disabling of the high-side driving circuit 305 , and the low-side driving path of the switch-transistor circuit 30 can be still enabled in response to the enabling of the low-side driving circuit 307 .

In case that the system power VCC only can be provided to the low-side driving circuit 307 , when the second control signal V PWM ′ is in the high level, the transistor Q 3 is turned on, so the gate of the low-side transistor Q L is coupled to the system power VCC. In this case, the low-side transistor Q L would be turned on, but the bootstrap capacitor C can not be charged by the power system VCC at this time due to the charging path of the bootstrap capacitor C can not be established. Moreover, when the second control signal V PWM ′ is in the low level, the transistor Q 4 is turned on, so the gate and the source of the low-side transistor Q L are coupled with each other. In this case, the low-side transistor Q L would be turned off. Obviously, the operation of the low-side driving path of the switch-transistor circuit 30 is not affected by enabling or disabling the high-side driving path of the switch-transistor circuit 30 .

In case that the system power VCC only can be provided to the low-side driving circuit 307 , since the charging path of the bootstrap capacitor C can not be established, so the high-side transistor Q H is continuously turned off when the load 40 is in the light-loading state. Obviously, when the load 40 is in the light-loading state, the bootstrap gate driver 20 can disable the high-side driving path of the switch-transistor circuit 30 , so as to effectively/substantially increase the light-loading efficiency.

FIG. 4 is a part of operation diagram of the bootstrap gate driver 20 of FIG. 2 . Referring to FIGS. 2-4 , the load indication signal C 32 , the first control signal V PWM and the voltage Vg on the bootstrap capacitor C are only shown on FIG. 4 . Assuming that the load 40 is not in the light-loading state before the timing T 1 on the time axis t, the load indication signal C 32 is in the high level, so the charging path of the bootstrap capacitor C can be established. In this case, the high-side driving path of the switch-transistor circuit 30 is enabled, such that the high-side transistor Q H is turned on in response to the high voltage Vg when the first control signal V PWM is in the high level; moreover, the high-side transistor Q H is turned off in response to the low voltage Vg when the first control signal V PWM is in the low level.

On the other hand, assuming that the load 40 is in the light-loading state after the timing T 1 on the time axis t, the load indication signal C 32 is in the low level, so the charging path of the bootstrap capacitor C can not be established. In this case, the high-side driving path of the switch-transistor circuit 30 is disabled, such that the high-side transistor Q H is continuously turned off in response to the low voltage Vg regardless of that the first control signal V PWM is in either the high level or the low level.

FIG. 5 is an application diagram of the bootstrap gate driver 20 of FIG. 2 . Referring to FIGS. 2-5 , in this exemplary embodiment, assuming that the bootstrap gate driver 20 is at least suitable for a voltage converter, for example, a boost converter as shown in FIG. 5 , but not limited thereto. In other words, the circuit configuration shown in FIG. 5 is a boost conversion topology. To be specific, terminals T 001 , T 002 are input of the boost converter, and terminals T 003 , T 004 are output of the boost converter for supplying an output voltage Vout to the load 40 .

As shown in FIG. 5 , the high-side transistor Q H functions as a synchronous rectifier (SR) through the body diode of the high-side transistor Q H , and the low-side transistor Q L functions as a main switch in the boost converter. A chip CP 1 (for example, the integrated chip of LT 6106 , but not limited thereto) and resistors R 1 , RD may function as the sample circuit 301 ; and resistors R 2 -R 5 and a comparator CM may function as the determination circuit 303 . A chip CP 2 (for example, the integrated chip of LM 27222 , but not limited thereto) may function as the high-side driving circuit 305 , the low-side driving circuit 307 and the signal processing unit 309 .

In this case, the chip CP 1 can obtain the load current supplied to the load 40 through the resistor RD, so as to detect the state of the load 40 and thus generating the detection signal DS with the voltage level V DS to the determination circuit 303 . The determination circuit 303 would compare the detection signal DS with the voltage level V DS to the reference signal RS with the voltage level V RS , so as to generate the load indication signal C 32 . The reference signal RS is corresponding to a light-loading reference point. If the detection signal DS with the voltage level V DS is higher than the reference signal RS with the voltage level V RS , the output load indication signal C 32 is in the high level, it represents that the load 40 is not in the light-loading state. If the detection signal DS with the voltage level V DS is lower than the reference signal RS with the voltage level V RS , the output load indication signal C 32 is in the low level, it represents that the load 40 is in the light-loading state.

In case that the load 40 is not in the light-loading state, the transistors Q 5 , Q 6 are simultaneously turned on in response to the load indication signal C 32 with high level, so the high-side transistor Q H and the low-side transistor Q L can be alternately switched under the control of the chip CP 2 because the charging path of the bootstrap capacitor C can be established. On the other hand, in case that the load 40 is in the light-loading state, the transistors Q 5 , Q 6 are simultaneously turned off in response to the load indication signal C 32 with low level, so the high-side transistor Q H can not be switched under the control of the chip CP 2 because the charging path of the bootstrap capacitor C can not be established, but meanwhile, the low-side transistor Q L can still be switched under the control of the chip CP 2 .

It should be noted that since the body diode is a one-direction conducting element, so the loop of reactive cycling current is blocked when the load 40 is in the light-loading state. As a result, the boost converter will operate in a discontinuous conduction mode (DCM), so not only no negative inductive current will appear, but also inductive loss and driving loss of synchronous rectifier will be significantly reduced. Consequentially, the light-loading efficiency will be obviously increased.

Besides, even the bootstrap gate driver 20 applied in the boost converter is taken as an example in the above exemplary embodiments, but the application occasion of the bootstrap gate driver 20 is not limited thereto. To be specific, the bootstrap gate driver 20 may be applied in another voltage converter other than the boost converter, for example, a buck converter with SRs, a flyback converter with SRs, a forward converter with SRs, a boost-buck converter with SRs, but not limited thereto. In other words, the application occasion of the bootstrap gate driver 20 can be determined by the real design or application requirement.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.