Serial data transmission system and method

1. Field of Invention

The present invention relates to a data transmission system and method, and more particularly to a serial data transmission system having an amplitude detection unit and its method.

2. Description of Related Arts

In a serial data transmission system, when performing a high-speed data transmission, a transmitting terminal of an electronic device needs to detect whether a receiving terminal of an opposite side is properly connected with the transmitting terminal of the electronic device. And the high-speed data transmission is not capable of being started until the transmitting terminal of the electronic device detects that the receiving terminal of the opposite side is properly connected with the transmitting terminal of the electronic device.

Thus, it is required that the transmitting terminal of the electronic device has a detection circuit which is capable of detecting whether the receiving terminal is properly connected. In a serial data transmission system, due to great changes of a peripheral circuit, especially due to the existing of an AC coupling device in a plate pathway, a parasitic circuit in the plate, and factors such as an uncertain resistance designing in the receiving terminal, when a detection circuit is designed, the system is required to have a high anti jamming capability, accurate judgment range, and power consumption thereof is required to be as less as possible, so as to meet the demand of low power consumption in the development of future.

In view of the descriptions mentioned above, it is necessary to provide a serial data transmission system having a simple structure, a strong anti-interference ability, a low power consumption, and comprising an amplitude detection unit thereof, and its method.

A serial data transmission system, comprises a transmitting terminal for transmitting data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit, and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other.

A serial data transmission method, for transmitting differential data received by a transmitting terminal to a receiving terminal, comprises the following steps of:

receiving a pair of differential data by the transmitting terminal;

switching on an amplitude detection unit in the transmitting terminal;

according to the received differential data, outputting a pair of differential signals to an amplitude detection circuit in the amplitude detection unit by a transmitting terminal diver unit in the transmitting terminal;

detecting an amplitude variation of the received differential data, and outputting a detecting voltage, which is proportional to a voltage that the received differential data are deviating from the common-mode voltage, to a non-inverting input terminal of a comparator in the amplitude detection unit, by the amplitude detection circuit;

inputting a reference voltage to an inverting input terminal of the comparator by a reference voltage terminal;

outputting an indication signal which indicates whether the transmitting terminal and the receiving terminal is properly connected, by an outputting terminal of the comparator; and

transmitting the received differential data to the receiving terminal by the transmitting terminal, if the transmitting terminal and the receiving terminal are properly connected with each other.

Compared with conventional arts, the serial data transmission system and method of the present invention detect the amplitude variation generated by the transmitting terminal during data transmitting, generate a detecting voltage, which is proportional to the amplitude variation generated during data transmitting, and compare the detecting voltage with the reference voltage to detect whether the transmitting terminal and the receiving terminal are properly connected with each other, via the amplitude detection unit. The serial data transmission system and method of the present invention have a simple structure, a strong anti-interference ability and low power consumption.

These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

FIG. 1 is a system frame diagram of a serial data transmission system according to a preferred embodiment of the present invention.

FIG. 2 is a system block diagram of an amplitude detection unit of the serial data transmission system according to the preferred embodiment of the present invention.

FIG. 3 is a specific circuit diagram of the serial data transmission system according to the preferred embodiment of the present invention.

FIG. 4 is a flow chart of a serial data transmission method according to a preferred embodiment of the present invention.

Referring to FIG. 1 and FIG. 3 of the drawings, a serial data transmission system according to a preferred embodiment of the present invention, comprises a transmitting terminal, a receiving terminal, a first connecting capacitor C 1 connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor C 2 connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the receiving terminal comprises a first resistor R 1 and a second resistor R 2 which are connected in parallel.

The transmitting terminal driver unit outputs a pair of differential signals tx_on and tx_op, according to a data signal received. The amplitude detection unit detects an amplitude variation of the signals tx_on and tx_op which are output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. Both the first connecting capacitor C 1 and the second connecting capacitor C 2 are AC coupling capacitors for isolating DC signals and allowing only AC signals to pass through. The first resistor R 1 and the second resistor R 2 are load impedances of the receiving terminal. Both the resistor R 1 and the resistor R 2 are connected with ground.

Referring to FIG. 2 of the drawings, which is a system block diagram of the amplitude detection unit of the serial data transmission system according to the preferred embodiment of the present invention, and further referring to FIG. 3 of the drawings, the amplitude detection unit comprises an amplitude detection circuit, a reference voltage generation circuit, a reference voltage terminal Vref connected with the reference voltage generation terminal, and a comparator COMP respectively connected with the amplitude detection circuit and the reference voltage terminal Vref, the amplitude detection circuit is for detecting an amplitude variation of differential signals output by the transmitting terminal driver circuit, and outputting a voltage which is proportional to the amplitude variation of the differential signals to the comparator COMP, the reference voltage generation circuit is for generating a required reference voltage to the reference voltage terminal Vref, the comparator COMP is for comparing the voltage output by the amplitude detection circuit with a voltage at the reference terminal in size, and outputs the indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other.

Referring to FIG. 3 , which is a specific circuit diagram of the serial data transmission system according to the preferred embodiment of the present invention, the transmitting terminal driver unit comprises a first current source I 1 , a first field effect transistor (FET) M 1 connected with the first current source I 1 , a second FET M 2 connected with the first current source I 1 , a third resistor R 3 connected with the first FET M 1 , and a fourth resistor R 4 connected with the second FET M 2 ; the amplitude detection circuit comprises a fourth current source I 4 , a fifth current source I 5 , a third FET M 3 , a fourth FET M 4 , an eighth FET M 8 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , a third capacitor C 3 , and a fourth capacitor C 4 ; and the reference voltage generation circuit comprises a second current source I 2 , a third current source I 3 , a fifth FET M 5 , a sixth FET M 6 , a seventh FET M 7 , an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , a fourteenth resistor R 14 , a fifteenth resistor R 15 , a sixteenth resistor R 16 , a fifth capacitor C 5 , and a sixth capacitor C 6 .

According to the preferred embodiment of the present invention, specific circuit connections of the serial data transmission system are as follows. A first terminal of the first current source I 1 , a first terminal of the second current source I 2 , a first terminal of the third current source I 3 , a first terminal of the fourth current source I 4 , a first terminal of the fifth current source I 5 , a first terminal of the seventh resistor R 7 , a first terminal of the eighth resistor R 8 , a first terminal of the eleventh resistor R 11 , and a first terminal of the twelfth resistor R 12 are all connected with a source terminal VDD. Both a source electrode of the first FET M 1 and a source electrode of the second FET M 2 are connected with a second terminal of the first current source I 1 , both a gate electrode of the first FET M 1 and a gate electrode of the second FET M 2 receive a pair of input differential data DATA_P and DATA_N, a drain electrode of the first FET M 1 is respectively connected with a first terminal of the third resistor R 3 , a first terminal of the first connecting capacitor C 1 , a gate electrode of the third FET M 3 , and a first terminal of the ninth resistor R 9 , a drain electrode of the second FET M 2 is respectively connected with a first terminal of the fourth resistor R 4 , a first terminal of the second connecting capacitor C 2 , a gate electrode of the fourth FET M 4 , and a first terminal of the tenth resistor R 10 , both a drain electrode of the first FET M 1 and a drain electrode of the second FET M 2 output the pair of differential signals Tx_on and Tx_op to the gate of the third FET M 3 and the gate of the fourth FET M 4 . A second terminal of the first connecting capacitor C 1 is connected with a first terminal of the second resistor R 2 , a second terminal of the second connecting capacitor C 2 is connected with a first terminal of the first resistor R 1 . A drain electrode of the third FET M 3 is connected with a second terminal of the eighth resistor R 8 , a drain electrode of the fourth FET M 4 is connected with a second terminal of the seventh resistor R 7 , a source electrode of the third FET M 3 , a source electrode of the fourth FET M 4 , a drain electrode of the eighth FET M 8 , a first terminal of the fifth resistor R 5 , a first terminal of the sixth resistor R 6 , a first terminal of the third capacitor C 3 , and a first terminal of the fourth capacitor C 4 are all connected with a voltage detection terminal Vdct. A second terminal of the fifth resistor R 5 is connected with a second terminal of the fourth current source I 4 , a second terminal of the sixth resistor R 6 is connected with a second terminal of the fifth current source I 5 . Both a second terminal of the ninth resistor R 9 and a second terminal of the tenth resistor R 10 are connected with a gate electrode of the fifth FET M 5 and a gate electrode of the sixth FET M 6 , and a common-mode signal Tx_com is output to the gate electrode of the fifth FET M 5 and the gate electrode of the sixth FET M 6 . A drain electrode of the fifth FET M 5 is connected with a second terminal of the eleventh resistor R 11 , a drain electrode of the sixth FET M 6 is connected with a second terminal of the twelfth resistor R 12 . A source electrode of the fifth FET M 5 , a source electrode of the sixth FET M 6 , a drain electrode of the seventh FET M 7 , a first terminal of the fifteenth resistor R 15 , a first terminal of the sixteenth resistor R 16 , a first terminal of the fifth capacitor C 5 , and a first terminal of the sixth capacitor C 6 are all connected with each other. A gate electrode of the seventh FET M 7 is connected with a gate electrode of the eighth FET M 8 , both the gate electrode of the seventh FET M 7 and the gate electrode of the eighth FET M 8 are connected with a voltage terminal Vb. A first terminal of the thirteenth resistor R 13 is connected with a second terminal of the second current source I 2 , a first terminal of the fourteenth resistor R 14 is connected with a second terminal of the third circuit current I 3 , both a second terminal of the thirteenth resistor R 13 and a second terminal of the fifteenth resistor R 15 are connected with the reference voltage terminal Vref, and a second terminal of the fourteenth resistor R 14 is connected with a second terminal of the sixteenth resistor R 16 . A second terminal of the first resistor R 1 , a second terminal of the second resistor R 2 , a second terminal of the third resistor R 3 , a second terminal of the fourth resistor R 4 , a second terminal of the third capacitor C 3 , a second terminal of the fourth capacitor C 4 , a second terminal of the fifth capacitor C 5 , a second terminal of the sixth capacitor C 6 , a source electrode of the seventh FET M 7 , and a soured electrode of the eighth FET M 8 are all connected with a ground terminal GND. A non-inverting input terminal of the comparator COMP is connected with the voltage detection terminal Vdct, an inverting input terminal of the comparator is connected with the reference voltage terminal Vref, an output terminal OUT of the comparator outputs an indicating signal that indicates whether the transmitting terminal and the receiving terminal are properly connected with each other. A voltage terminal of the comparator COMP is connected with the source terminal VDD, a second terminal of the comparator COMP is connected with the ground terminal GND.

Working principles of the serial data transmission system according to a preferred embodiment of the present invention are as follows.

Referring to FIG. 3 of the drawings, the differential data DATA_P and DATA_N are serial data which are required to be transmitted by the transmitting terminal. When switching on the amplitude detection unit, the differential data DATA_P and DATA_N are data to be detected with a certain frequency, and the frequency thereof is capable of being regulated according to a designing requirement.

If the amplitudes output by the differential signals Tx_on and Tx_op are respectively as following:

V Tx — on =V Tx — com +ΔV, V Tx — op =V Tx — com −ΔV;

the common-mode voltage thereof is V Tx — com ,

V Tx ⁢ ⁢ _ ⁢ ⁢ com = 1 2 ⁢ I ⁢ ⁢ 1 × R ⁢ ⁢ 4 ,

wherein ΔV is a voltage that the differential data Tx_on and Tx_op are deviating from the common-mode voltage, i.e., an amplitude of the signal output by the transmitting terminal.

At this moment, sum of currents that flows through the third FET M 3 and the fourth FET M 4 is as following:

I M3 +I M4 =K ( V tx — op −V dct −V th ) 2 +K ( V Tx — on −V dct −V th ) 2 =K ( V b −V th ) 2 −I 4 −I 5 ,

from the equation mentioned above, a formula that indicates a variation of a voltage value Vdct at the voltage detection terminal Vdct with ΔV is obtained:

i.e., the voltage value Vdct at the voltage detection terminal Vdct is proportional to the voltage value ΔV that the differential data Tx_on and Tx_op are deviating from the common-mode voltage,

wherein K is a proportional coefficient,

K = 1 2 ⁢ μ ⁢ ⁢ c ox ⁢ W L ,

μ is a mobility of a process of an FET, Cox is a gate oxide thickness of the process of the FET,

W L

is a width to length ratio of the third FET M 3 and the fourth FET M 4 , Vth is a threshold voltage of the FET.

It can be seen from the formula mentioned above that the voltage value Vdct at the voltage detection terminal Vdct increases with an increasing of the voltage value ΔV that the differential data Tx_on and Tx_op are deviating from the common-mode voltage.

Assuming that when the transmitting terminal detects that the transmitting terminal and the receiving terminal are properly connected with each other, the voltage value that the differential signals Tx_on and Tx_op are deviating from the common-mode voltage is ΔV 1 , the voltage value detected at the voltage terminal Vdct is Vdct 1 ; and that when the transmitting terminal detects that the transmitting terminal and the receiving terminal are not properly connected with each other, the voltage value that the differential signals Tx_on and Tx_op are deviating from the common-mode voltage is ΔV 2 , the voltage value detected at the voltage terminal Vdct is Vdct 2 ,

when the transmitting terminal detects that the transmitting terminal and the receiving terminal are properly connected with each other,

when the transmitting terminal detects that the transmitting terminal and the receiving terminal are not properly connected with each other,

Δ ⁢ ⁢ V ⁢ ⁢ 2 = 1 2 ⁢ I ⁢ ⁢ 1 × R ⁢ ⁢ 4 ; Δ V 1 <ΔV 2, so Vdct 1 <Vdct 2.

In order to distinguish the two cases mentioned above, a reference voltage value Vref generated by the reference voltage generation circuit is set between ΔV 1 and ΔV 2 .

when the transmitting terminal detects that the transmitting terminal and the receiving terminal are properly connected with each other, Vdct<Vref, i.e., an output at the output terminal of the comparator is at low level;

when the transmitting terminal detects that the transmitting terminal and the receiving terminal are not properly connected with each other, Vdct>Vref, i.e., the output at the output terminal of the comparator is at high level.

It can be seen from the descriptions mentioned above that whether the transmitting terminal and the receiving terminal are properly connected with each other is capable of being detected, by a level of signal output by the transmitting terminal of the comparator.

Referring to FIG. 4 of the drawings, a serial data transmission system according to a preferred embodiment of the present invention comprises:

step 1 of, receiving a pair of differential data DATA_P and DATA_N by the transmitting terminal, wherein the pair of differential data DATA_P and DATA_N are serial data that requires the transmitting terminal to transmit;

step 2 of, switching on an amplitude detection unit in the transmitting terminal, wherein at this moment, the differential data DATA_P and DATA_N are data to be detected with a certain frequency, and the frequency thereof is capable of being regulated according to a designing requirement;

step 3 of, according to the differential data DATA_P and DATA_N received, outputting a pair of differential signals Tx_on and Tx_op to an amplitude detection circuit in the amplitude detection unit by a transmitting terminal diver unit in the transmitting terminal;

step 4 of, detecting an amplitude variation of the differential data Tx_on and Tx_op received, and outputting a detecting voltage Vdct, which is proportional to a voltage ΔV that the differential data Tx_on and Tx_op received are deviating from the common-mode voltage, to a non-inverting input terminal of a comparator in the amplitude detection unit, by the amplitude detection circuit;

step 5 of, generating a reference voltage to the reference voltage terminal Vref by a reference voltage generation circuit, wherein the reference voltage terminal Vref inputs the reference voltage to an inverting input terminal of the comparator;

step 6 of, outputting an indication signal which indicates whether the transmitting terminal and the receiving terminal are properly connected with each other by an outputting terminal of the comparator; and judging whether the transmitting terminal and the receiving terminal are properly connected with each other; and

step 7 of, transmitting the differential data DATA_P and DATA_N received to the receiving terminal by the transmitting terminal, if the transmitting terminal and the receiving terminal are properly connected with each other; stopping working if the transmitting terminal and the receiving terminal are not properly connected with each other.

In the serial data transmission system and method of the present invention, the amplitude detection unit detects the amplitude variation generated by the transmitting terminal during data transmitting, i.e., a voltage value that the differential data Tx_on and Tx_op are deviating from the common-mode voltage; generates a detecting voltage, which is proportional to the amplitude variation generated during data transmitting; and compares the detecting voltage with the reference voltage to detect whether the transmitting terminal and the receiving terminal are properly connected with each other. The serial data transmission system and method of the present invention have a simple structure, a strong anti-interference ability and a low power consumption.

One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.