Synchronous rectifier driver circuit rectifier

This application claims priority under 35 U.S.C. §119 to Chinese patent application 201110198561.3, filed Jun. 2, 2011, the disclosure of which is incorporated herein by reference in its entirety.

This application is directed, in general, to power conversion and, more specifically, to synchronous rectifiers and methods of operating and forming synchronous rectifiers.

Some synchronous, or active, rectifiers provide improved efficiency over diode-bridge rectifiers in part by reducing resistive losses by replacing the diodes with transistors, e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs). The MOSFETs may have a very low on-resistance, e.g. 10 mΩ, compared to a constant junction-voltage drop across the diodes, e.g. about 0.7-1.2 volts.

As the driving loss of the conventional self-driving circuit is very large in wide input voltage range design, continuing research has been undertaken to improve the efficiency of the synchronous rectifier driver circuit. While the efficiency of synchronous rectifiers is significantly greater than diode-bridge rectifiers, power loss of the self-driving clamp MOSFETs imposes a lower limit on the efficiency of conventional self-driving designs. New solutions are needed to further reduce losses in synchronous rectifier driving circuits while doing so with low cost.

One aspect provides a synchronous rectifier that includes primary and secondary rectifier circuits. The primary rectifier circuit is configured to produce first and second half-rectified signals from respective first and second primary voltage outputs of a first transformer winding. The secondary rectifier circuit is configured to rectify a voltage output of a second transformer winding in response to first and second transistor gate inputs. A first buffer driver is configured to receive the first half-rectified signal and to provide a first buffered control signal to the first transistor gate input. A second buffer driver is configured to receive the second half-rectified signal and to provide a second buffered control signal to the first transistor gate input.

Another aspect provides a method of forming a synchronous rectifier. The method includes the step of configuring a primary rectifier circuit to produce first and second half-rectified signals from first and second primary voltage outputs of a first transformer winding. In another step a secondary rectifier circuit is configured to rectify a voltage output of a second transformer winding in response to first and second transistor gate inputs. In another step a first buffer driver is configured to receive the first half-rectified signal and to provide a first buffered control signal to the first transistor gate input. In another step a second buffer driver is configured to receive the second half-rectified signal and to provide a second buffered control signal to the first transistor gate input.

Another aspect provides a method of operating a synchronous rectifier. The method includes the step of producing first and second half-rectified signals from respective first and second primary voltage outputs of a first transformer winding. In another step the first and second half-rectified signals are buffered with respective first and second buffer drivers to produce respective first and second control signals. In another step an output of the first control signal is coupled to ground when under control of the second rectifier control signal. In another step an output of the second buffer driver is coupled to ground under control of the first rectifier control signal.

Yet another aspect provides a synchronous rectifier. The rectifier includes MOSFETs S 1 and S 2 . The MOSFET S 1 has a drain connected to a first terminal of a first transformer winding. The MOSFET S 2 has a drain connected to a second terminal of the first transformer winding. An input of a first buffer driver is connected to a source of the MOSFET S 1 . An input of a second buffer driver is connected to a source of the MOSFET S 2 . A MOSFET S 3 has a gate connected to the input of the second buffer driver, a source connected to ground and a drain configured to receive an output voltage from the first buffer driver. A MOSFET S 4 has a gate connected to the input of the first buffer driver, a source connected to ground and a drain configured to receive an output voltage from the second buffer driver. A MOSFET Q 1 has a drain connected to a first terminal of a second transformer winding, a source connected to ground and a gate configured to receive the output voltage from the first buffer driver. A MOSFET Q 2 has a drain connected to a second terminal of the second transformer winding, a source connected to ground and a gate configured to receive the output voltage from the second buffer driver.

Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates aspects of a prior art synchronous rectifier;

FIG. 2 illustrates a synchronous rectifier according to one embodiment in accordance with the disclosure;

FIGS. 3 and 4 illustrate aspects of signal timing of signals in various embodiments, e.g. the synchronous rectifier of FIG. 2 ;

FIG. 5 illustrates internal functionality of an integrated driver circuit that may be used in some embodiments to provide buffer drivers used in the synchronous rectifier of FIG. 2 ;

FIG. 6 illustrates a synchronous rectifier according to one embodiment in which some MOSFETS in the embodiment of FIG. 2 are replaced with diodes; and

FIG. 7 presents a method of forming a synchronous rectifier according to various embodiments of the disclosure, e.g. the synchronous rectifiers 200 and 600 .

Embodiments presented herein describe a new synchronous rectifier (SR) drive circuit for power converters. In applications involving a wide range of input voltages, a conventional SR self-driving circuit is typically not suitable, as there may be large resistive losses and thermal issues involving linear clipping MOSFETs used in the synchronous FET drive. Some conventional synchronous rectifier drive solutions use a digital isolator to transfer a control signal from a primary control integrated circuit (IC) to a secondary driver IC, with an RC delay circuit to adjust the delay time between primary and secondary sides. Although this solution may achieve high efficiency in some cases, the circuit includes many components, and is thus typically complex and/or costly. Embodiments of the present disclosure provide an improved SR driver strategy that provides low driver-related loss and may be less costly to manufacture than conventional synchronous rectifier drive solutions.

FIG. 1 illustrates a prior art SR circuit 100 that is representative of some conventional SR circuits. The circuit 100 includes a primary rectifier circuit 101 and a secondary rectifier circuit 102 . The primary rectifier circuit 101 includes MOSFETs S 1 110 and S 2 120 , and clipping MOSFETs 140 , 150 . The secondary rectifier circuit 102 includes MOSFETs Q 1 160 and Q 2 170 . In some cases the components of the primary rectifier circuit 101 are integrated in a control IC, and the components of the secondary rectifier circuit 102 are integrated in a driver IC.

The MOSFETs S 1 110 and S 2 120 are biased with a gate voltage Vg and are thus always “on”, e.g. provide a relatively low resistance path between the source and the drain of the device. The drains of each of S 1 110 and S 2 120 are connected to terminals 130 - 1 and 130 - 2 of a primary winding T 1 B 130 of a transformer T 1 . The winding T 1 B 130 produces a time-varying (AC) voltage across the terminals 130 - 1 , 130 - 2 . The voltage at the terminal 130 - 1 is designated Vs 1 , and the voltage at the terminal 130 - 2 is designated Vs 2 . The voltage at the S 1 110 source is designated V in1 , and the voltage at the S 2 120 source is designated V in2 .

The source of S 1 110 is connected to the gate of the MOSFET 140 . The source of S 2 120 is connected to the gate of the MOSFET 150 . When Vs 1 >0, the MOSFET 140 clips V in2 to about ground. When Vs 2 >0 the MOSFET 150 clips V in1 to about ground. Thus, each of V in1 and V in2 is a half-rectified portion of the AC voltage produced at the respective terminals 130 - 1 , 130 - 2 .

The drains of a MOSFET Q 1 160 and a MOSFET Q 2 170 are respectively connected to a terminal 180 - 2 and a terminal 180 - 1 of a secondary winding T 1 A 180 of the transformer T 1 . When V in1 is positive, Q 1 160 is on and Q 2 170 is off. The terminal 180 - 2 is grounded, setting a ground reference for the voltage at the terminal 180 - 1 . The voltage at the terminal 180 - 1 therefore follows the positive phase of the AC output of the winding T 1 A 180 . When V in2 is positive, Q 2 170 is on, thereby grounding the terminal 180 - 1 . Thus the voltage at the terminal 180 - 2 is half-rectified. An LC filter formed by an inductor L 1 190 and a capacitor C 1 195 is charged by the periodic positive cycles of the voltage at the terminal 180 - 1 , thereby providing a substantially DC voltage V 0 across the terminals of C 1 195 .

To improve performance in wide input voltage range design applications, some conventional SR circuits include a driver between the primary rectifier circuit 101 and the secondary rectifier circuit 102 . Such drivers may, e.g. reduce transient current flow through S 1 110 and S 2 120 . However, delays in the drivers may result in Q 1 160 and Q 2 170 being briefly simultaneously turned on. In such cases, a low resistance path between the terminals 180 - 1 and 180 - 2 of the winding T 1 A 180 causes a high current transient with resulting resistive loss and joule heating of Q 1 160 and Q 2 170 and the winding T 1 A. This power loss decreases the efficiency of the SR circuit 100 and may lead to lower reliability and/or the need to dissipate the heat for the SR circuit 100 .

Some conventional attempts to reduce these resistive losses have used a digital isolator and an RC delay circuit to adjust the delay time between primary and secondary sides of the transformer T 1 . Conventional implementations of this approach typically require more components that result in added circuit complexity and cost, and may be less reliable due to additional potential sources of failure.

FIG. 2 illustrates in one embodiment of the disclosure a synchronous rectifier 200 that provides improved conversion efficiency with significantly lower complexity and cost than some conventional implementations as described above. The synchronous rectifier 200 includes the primary rectifier circuit 101 and the secondary rectifier circuit 102 previously described. Embodiments of the disclosure explicitly include variations of the primary rectifier circuit 101 and the secondary rectifier circuit 102 that may differ in form while providing substantially the same functionality as the illustrated rectifier circuits 101 and 102 .

Interposed between the rectifier circuits 101 , 102 is an isolation circuit 201 . The isolation circuit 201 includes buffer drivers 210 a and 210 b , resistors R 1 220 and R 2 230 , and MOSFETs S 3 240 and S 4 250 . As used in this discussion and in the claims, a buffer driver is a circuit that amplifies a drive current capability of an electrical signal input to the buffer driver. The gain of the buffer driver is not limited to any particular value. For example, a buffer driver may receive a 100 μA current at its input and drive a load with about 1 A or more. A buffer driver may be, e.g. a conventional driver.

The isolation circuit 201 receives input signals V in1 and V in2 , and provides buffered control signals V o1 and V o2 respectively to gates of Q 1 160 and Q 2 170 . The buffer drivers 210 a , 210 b may be powered by inductively coupling a winding L 1 B to the inductor L 1 . An AC voltage produced by the winding L 1 B may be rectified by a diode D 1 and a capacitor C 2 .

The isolation circuit 201 serves several functions in the synchronous rectifier 200 . First, the buffer drivers 210 a , 210 b isolate the MOSFETs S 1 110 and S 2 120 from the MOSFETs Q 1 160 and Q 2 170 . This aspect may reduce current through S 1 110 and S 2 120 that is caused by capacitive switching at the gates of Q 1 160 and Q 2 170 . Second, the buffer drivers may provide relatively uniform switching current to Q 1 160 and Q 2 170 over a wider range of voltage provided by the winding T 1 B 130 . A third related function provided by the buffer drivers 210 a , 210 b is the reduction of switching time, e.g. rise and fall times of the gate voltages of Q 1 160 and Q 2 170 that may provide greater precision of timing the on and off states of Q 1 160 and Q 2 170 .

In spite of these beneficial effects, the buffer driver 210 a may impose a small delay between V in1 and the gate of Q 1 160 . Similarly the buffer driver 210 b may impose a small delay between V in2 and the gate of Q 2 170 . If not mitigated, these delays can lead to simultaneous conduction through Q 1 and Q 2 , with resulting power loss and reduced lifetime of Q 1 and Q 2 .

For example, FIG. 3A illustrates voltage traces of V in1 and V in2 for the synchronous rectifier 200 without the presence of S 3 240 and S 4 250 . A current trace I T1A is representative of current through the winding T 1 A 180 , Q 1 160 and Q 2 170 . V in1 and V in2 are half-rectified signals. At times t 1 , t 2 , t 3 and t 4 Q 1 160 and Q 2 170 may be briefly simultaneously in an “on” state. Thus, I T1A includes periodic current spikes 310 at the zero-crossings of V in1 and V in2 .

FIG. 4 illustrates voltage traces of V in1 , V in2 , V o1 and V o2 for the synchronous rectifier 200 including the transistors S 3 240 and S 4 250 . S 3 240 and S 4 250 receive feed-forward communication of the V in1 and V in2 signals to substantially prevent the occurrence of the current spikes 310 . V o1 lags Vin 1 by Δt, and V o2 lags V in2 by Δt, wherein Δt is the delay imposed by the buffer drivers 210 a and 210 b . First considering V o1 , immediately prior to T 1 this signal follows the form of V in1 . The buffer driver 210 a may have unity or non-unity gain. The transistor S 3 240 is off because V in2 is clipped to ground by the MOSFET 140 . At time t 1 , V in1 falls below the turn-on voltage of S 4 250 , thereby turning S 4 250 off, and V in2 begins to increase. The rise of V in2 turns on S 3 240 , clipping V o1 to ground. V in2 is buffered by the buffer driver 210 b , which again may have unity or non-unity gain. V o2 follows V in2 with a time lag. At T 2 V in1 again increases, turning on S 4 250 . V o2 is clipped to ground by S 4 250 . V o1 follows V in1 with the time lag Δt. Subsequent periods of V in1 , V in2 , V o1 and V o2 continue to follow the described pattern.

By examination of V o1 and V o2 it is apparent that these signals are not simultaneously active, e.g. greater than zero volts. Thus Q 1 and Q 2 will not be simultaneously in an “on” state and the current spikes 310 ( FIG. 3 ) are substantially eliminated.

Turning to FIG. 5 , a driver circuit 500 that includes first and second buffer driver circuits 510 and 520 . The driver circuit 500 includes terminals 1 - 6 . The buffer driver circuit 510 has an input at terminal 1 and an output at terminal 4 . The buffer driver circuit 520 has an input at terminal 3 and an output at terminal 6 . Each buffer driver circuit 510 , 520 provides the functionality of one of the buffer drivers 210 a , 210 b . In various embodiments the buffer driver circuit 500 is a commercially available integrated circuit with at least two independent buffer driver circuits. The circuit 510 may operate as the buffer driver 210 a , while the circuit 520 may operate as the buffer driver 210 b . Power and ground may respectively be applied to terminals 5 and 2 .

In some embodiments the buffer driver circuits 510 , 520 are high performance buffer drivers. Herein and in the claims a high performance buffer driver is characterized by the following attributes:

1) capable of driving peak loads of at least about 1 ampere,

2) has a rise time response to a step-function input no greater than about 150 ns while driving a load of about 2 nF, and

3) has a fall time response to a step function input no greater than about 150 ns while driving a load of about 2 nF.

In some embodiments the peak load drive capacity is at least about 4 amperes, the rise time response time is about 20 ns or less for a load of about 1.8 nF, and the fall time is less than about 15 ns for a load of about 1.8 nF.

In one embodiment, the driver circuit 500 is provided by a commercially available integrated circuit that includes two or more drivers, e.g. such as the buffer drivers circuits 510 , 520 . In one non-limiting example, part number UCC27324 manufactured by Texas Instruments, Dallas, Tex., USA may be used. Those skilled in the pertinent art will appreciate that the buffer driver circuits 510 , 520 may be equivalently formed using discrete components. Furthermore, embodiments of the circuit 500 that provide functionally similar operation to the UCC27324 are included in the scope of the disclosure.

FIG. 6 illustrates a synchronous rectifier 600 in another embodiment of the invention. The synchronous rectifier 600 replaces the MOSFETs 140 and 150 of the synchronous rectifier 200 with a network of resistors R 3 , R 4 and diodes D 2 , D 3 . The synchronous rectifier 600 may operate as described with respect to the synchronous rectifier 200 , with the exception of aspects now described. The anode of the diode D 2 is connected to ground and the cathode is connected to V in1 . The resistor R 3 is connected in parallel with D 2 . The anode of the diode D 3 is connected to ground and its cathode is connected to V in2 . A resistor R 4 is connected in parallel with D 3 . The diode D 2 operates to clip V in1 to a value no less than about ground less junction voltage drop of D 2 . The diode D 3 operates to clip V in2 to a value no less than about ground less the diode drop of D 3 .

The synchronous rectifier 600 also includes in some embodiments a diode D 4 with its anode connected to V in2 and its cathode connected to the transformer terminal 180 - 2 . When V in1 is positive, Q 1 is turned on, grounding the transformer terminal 180 - 2 . The voltage at the terminal 180 - 2 is then referenced to ground, and the terminal 180 - 2 provides an output voltage determined by the transformer characteristics. When V in2 is positive, the terminal 180 - 2 is referenced to V in2 less the D 4 diode drop). An effect of D 4 is to ensure that Vin 2 is about grounded when Vo 1 turns on Q 1 .

Turning to FIG. 7 , a method 700 is presented, e.g. of forming a synchronous rectifier, such as the synchronous rectifiers 200 and 600 . The method 700 is described without limitation in terms of features described herein, e.g. in FIGS. 2 , 4 , 5 and 6 . Embodiments of the disclosure include variations on the method 700 , such as performing the steps in an order other than the illustrated order.

In a step 710 , a primary control circuit is configured to receive first and second primary voltage outputs of a first transformer winding. First and second half-rectified signals are produced from the first and second primary voltage outputs. In a step 720 first and second buffer drivers are configured to produce first and second control signals from the first and second half-rectified signals. In a step 730 a secondary rectifier circuit is configured to rectify a voltage output of a second transformer winding in response to the first and second half-rectified signals. In a step 740 a first clipping transistor is configured to ground the first control signal in response to the second half-rectified signal. In a step 750 a second clipping transistor is configured to ground the second control signal in response the first half-rectified signal.

In a step 760 the first half-rectified signal is coupled to ground via a first resistor and a first diode arranged in parallel with the first resistor. The second half-rectified signal is coupled to ground via a second resistor and a second diode arranged in parallel with the second resistor. In a step 770 a third diode is coupled between the second half-rectified signal and the first terminal.

Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.