Linear multi-mode power amplifier for dynamic supply operation

The present invention relates, in general, to power amplifiers. More specifically, the present invention relates to Radio Frequency (RF) power amplifiers used in the field of cellular communication.

A key component in any wireless communication system is an RF power amplifier circuit that is enabled by a wide variety of semiconductor technologies. These RF power amplifier circuits generally operate in a variety of modes and hence the term ‘Multi-mode RF power amplifiers’. The multi-mode RF power amplifier circuits used in 3G/4G mobile handsets utilize switch path architecture. According to the architecture, switches placed in various paths, turn on or off to respectively activate or deactivate a particular path. A conventional multi-mode RF power amplifier circuit is designed to operate under two power modes, a high power mode and a low power mode. The conventional multi-mode RF power amplifier circuit includes a high power path and a low power path that are placed parallel to each other. In the high power mode, the high power path is active and the low power path is inactive. Whereas, in the low power mode, the low power path is active and the high power path is inactive. The RF power amplifier circuits are designed in such a way that only one of the two paths is active at any given time. This is achieved with the help of switches placed in these paths. Switches, such as FET switches, placed in the high and low power paths control the switching between the two parallel paths. The voltage difference between a gate and a drain of the FET switch determines the switching on and off of the FET switch. The FET switch will be switched on when the gate and drain terminals are biased with a same voltage and switched off when the gate and drain terminals have a potential difference that is less than a pinch-off voltage of the FET switch. The logic levels available for biasing the FET switch are 0V and the battery/power amplifier collector bias voltage.

In the prior art, under the high power mode of operation, when a supply voltage V cc is reduced to a certain level such that the voltage difference between the gate and drain terminals of the FET switch placed in the inactive low power path becomes higher than the pinch-off voltage of the FET switch, the FET switch placed in the inactive low power path is switched on. Consequently, a portion of output power from a power amplifier placed in the high power path is diverted into a matching network in the low power path rather than being transferred to an RF output terminal. Therefore, the power amplifier placed in the high power path has to deliver higher output power to compensate for the loss of output power to the low power path when the supply voltage V cc is reduced. This results in a considerable amount of performance degradation in terms of gain, current consumption and linearity.

In view of the foregoing, there arises a need for an efficient multi-mode RF power amplifier circuit that provides improved isolation between the active and the inactive power paths.

An object of the invention is to realize a multi-mode RF power amplifier circuit that provides improved isolation between active and inactive power paths.

Another object of the invention is to eliminate the need of switches at an output terminal of the active and the inactive paths of a multi-mode RF power amplifier circuit.

Yet another object of the invention is to provide a multi-mode RF power amplifier circuit that can operate under dynamic bias voltage.

Still another object of the invention is to provide a multi-mode RF power amplifier circuit having improved gain, power added efficiency and linearity.

In accordance with the objects of the invention, various embodiments of the invention provide a power amplifier circuit for amplifying a radio frequency (RF) signal. The power amplifier circuit operates in at least one of a first power amplification mode and a second power amplification mode. The power amplifier circuit comprises a first power amplification path, one or more second power amplification paths and a first impedance matching network. The first power amplification path has an input terminal and an output terminal. The first power amplification path is active when the power amplifier circuit operates in the first power amplification mode. The one or more second power amplification paths have an input terminal and an output terminal. One of the one or more second power amplification paths is active and the remaining of the one or more second power amplification paths are inactive when the power amplifier circuit operates in the second power amplification mode. Also, the input terminal of each of the one or more second power amplification paths is coupled to the input terminal of the first power amplification path. The first impedance matching network is respectively connected between the output terminal of each of the one or more second power amplification paths and the output terminal of the first power amplification path. An output impedance of the first impedance matching network respectively connected between the output terminal of the each inactive second power amplification path and the output terminal of the first power amplification path satisfies a first pre-determined condition when the power amplifier circuit operates in the first power amplification mode. The output impedance of the first impedance matching network satisfies a second pre-determined condition when the power amplifier circuit operates in the second power amplification mode. An input impedance of the first impedance matching network connected between the output terminal of the active second power amplification path and the output terminal of the first power amplification path satisfies a third pre-determined condition when the power amplifier circuit operates in the second power amplification mode.

Various embodiments of the invention will, hereinafter, be described in conjunction with the appended drawings provided to illustrate and not to limit the invention, wherein like designations denote like elements, and in which:

FIG. 1 a is an exemplary block diagram of a multi-mode RF power amplifier circuit, in accordance with an embodiment of the invention;

FIG. 1 b is an exemplary block diagram of a multi-mode RF power amplifier circuit operating under high power mode, in accordance with an embodiment of the invention;

FIG. 1 c is an exemplary block diagram of a multi-mode RF power amplifier circuit operating under low power mode, in accordance with an embodiment of the invention;

FIG. 2 a is an exemplary detailed circuit implementation of a multi-mode RF power amplifier circuit, in accordance with an embodiment of the invention;

FIG. 2 b is an exemplary detailed circuit implementation of a multi-mode RF power amplifier circuit, in accordance with another embodiment of the invention;

FIG. 3 is an exemplary detailed implementation of a multi-mode RF power amplifier circuit, in accordance with another embodiment of the invention;

FIG. 4 a is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with only one switch, in accordance with an embodiment of the invention;

FIG. 4 b is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with only one switch, in accordance with another embodiment of the invention;

FIG. 5 a is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with a shared bias, in accordance with an embodiment of the invention;

FIG. 5 b is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with a shared bias, in accordance with another embodiment of the invention;

FIG. 6 is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with multiple low power paths, in accordance with an embodiment of the invention; and

FIG. 7 is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit implemented with a shared bias for multiple low power paths, in accordance with an embodiment of the invention.

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the invention, and is not intended to represent the only form in which the invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention.

The invention provides an improved multi-mode RF power amplifier circuit that operates under a dynamic power supply. According to the invention, the multi-mode RF power amplifier circuit operates in a high power mode and a low power mode. The multi-mode RF power amplifier includes a low power path and a high power path. Under the high power mode of operation, the high power path becomes active and the low power path becomes inactive. Each of the low power path and the high power path includes impedance matching networks and power amplifiers. Under either mode of operation, an inactive path will present at least 10 times higher input impedance than that of an active path. An impedance matching network connected between the output terminals of the high power path and the low power path provides isolation between the output terminals of the high power path and the low power path.

FIG. 1 a is an exemplary block diagram of a multi-mode RF power amplifier circuit 100 in accordance with an embodiment of the invention. The power amplifier circuit 100 operates under a first power amplification mode, hereinafter referred to as a “high power mode” and a second power amplification mode, hereinafter referred to as a “low power mode”. FIG. 1 is shown to include, a first power amplification path 102 , hereinafter referred to as a “high power path 102 ”, a second power amplification path 104 , hereinafter referred to as a “low power path 104 ”, a first impedance matching network 106 , a second impedance matching network 108 , and a third impedance matching network 110 . High power path 102 includes a first power amplifier 112 , a second power amplifier 114 , a fourth impedance matching network 116 , a sixth impedance matching network 118 , an eighth impedance matching network 120 , a first input switch 122 , an inductor L 1 , and an inductor L 2 . Low power path 104 includes a third power amplifier 124 , a fifth impedance matching network 126 , a seventh impedance matching network 128 , a second input switch 130 , and an inductor L 3 .

A radio frequency (RF) signal RF in to be amplified is applied to an input terminal of second impedance matching network 108 . An output terminal of second impedance matching network 108 is connected to a node N 1 . An input terminal of high power path 102 and an input terminal of low power path 104 are coupled to the node N 1 . An output terminal of high power path 102 is connected to a node N 2 . An input terminal of fourth impedance matching network 116 is connected to the node N 1 . An output terminal of fourth impedance matching network 116 is connected to a first terminal of first input switch 122 . A second terminal of first input switch 122 is connected to an input terminal of sixth impedance matching network 118 . An output terminal of sixth impedance matching network 118 is connected to an input terminal of first power amplifier 112 . An output terminal of first power amplifier 112 is connected to a node N 3 . An input terminal of eighth impedance matching network 120 and a first terminal of the inductor L 1 are connected to the node N 3 . A second terminal of the inductor L 1 is connected to a voltage supply V cc . An output terminal of eighth impedance matching network 120 is connected to an input terminal of second power amplifier 114 . An output terminal of second power amplifier 114 is connected to the node N 2 . A first terminal of the inductor L 2 is connected to the node N 2 . A second terminal of the inductor L 2 is connected to the voltage supply V cc . An input terminal of third impedance matching network 110 is connected to the node N 2 . An output terminal of second power amplifier 114 provides an amplified RF output signal RF out .

An input terminal of fifth impedance matching network 126 is connected to the node N 1 . An output terminal of fifth impedance matching network 126 is connected to a first terminal of second input switch 130 . A second terminal of second input switch 130 is connected to an input terminal of seventh impedance matching network 128 . An output terminal of seventh impedance matching network 128 is connected to an input terminal of third power amplifier 124 . An output terminal of third power amplifier 124 is connected to a node N 4 . A first terminal of inductor L 3 is connected to the node N 4 . A second terminal of inductor L 3 is connected to the voltage supply V cc . An input terminal of first impedance matching network 106 is connected to the node N 4 . An output terminal of first impedance matching network 106 is connected to the node N 2 .

According to an embodiment of the present invention as illustrated in FIG. 1 , high power path 102 and low power path 104 are placed in parallel to each other and each path is designed to operate under a certain output power range. At any given point of time, the RF signal RF in will be transmitted and amplified through one of the paths.

In an embodiment of the invention, the input terminal of second impedance matching network 108 receives the RF signal RF in . Under the high power mode operation, first power amplifier 112 and second power amplifier 114 amplifies the RF signal RF in and provides the amplified signal to the output terminal of high power path 102 . The amplified signal is applied to the input terminal of third impedance matching network 110 . Under the low power mode operation, power amplifier 124 amplifies the RF signal RF in and provides the amplified signal to the output terminal of low power path 104 . The amplified signal is applied to the input terminal of third impedance matching network 110 through first impedance matching network 106 . The output terminal of third impedance matching network 110 provides the RF out signal. First impedance matching network 106 , second impedance matching network 108 , third impedance matching network 110 , fourth impedance matching network 116 , fifth impedance matching network 126 , sixth impedance matching network 118 , seventh impedance matching network 128 , and eighth impedance matching network 120 matches an impedance provided at their respective input terminals to an impedance provided at their respective output terminals.

FIG. 1 b is an exemplary block diagram of the multi-mode RF power amplifier circuit 100 working under the high power mode in accordance with an embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 1 b ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers. Further, power amplifier circuit 100 (refer to FIG. 1 b ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ) except for first input switch 122 which has been switched on. The functional operation of components are identical in power amplifier circuit 100 (refer to FIG. 1 b ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical, except for first input switched 122 which has been switched on. Under the high power mode operation, first input switch 122 is switched on so that high power path 102 becomes the active path and second input switch 130 will be switched off so that low power path 104 becomes an inactive path. Therefore, one or more power amplifiers 112 and 114 present in high power path 102 amplify the RF signal RF in .

In an embodiment of the invention, under the high power mode operation of power amplifier circuit 100 , isolation between the input terminals of high power path 102 and low power path 104 is achieved when an input impedance of fifth impedance matching network 126 of inactive low power path 104 satisfies a fifth pre-determined condition. According to the fifth pre-determined condition, the input impedance of fifth impedance matching network 126 of inactive low power path 104 is at least five times greater than an input impedance of fourth impedance matching network 116 of active high power path 102 . In accordance with another embodiment of the present disclosure, the input impedance of fifth impedance matching network 126 of inactive low power path 104 is ten times greater than an input impedance of fourth impedance matching network 116 of active high power path 102 . Therefore, the RF signal RF in applied to the input terminal of high power path 102 sees the high impedance presented by inactive low power path 104 and is coupled to fourth impedance matching network 116 .

Under the high power mode operation of power amplifier circuit 100 , isolation between the output terminals of high power path 102 and low power path 104 is achieved when an output impedance of first impedance matching network 106 connected between active high power path 102 and inactive low power path 104 satisfies a first pre-determined condition. According to the first pre-determined condition, the output impedance of first impedance matching network 106 connected between active high power path 102 and inactive low power path 104 is at least five times greater than an input impedance of third impedance matching network 110 . In accordance with another embodiment of the present disclosure, the output impedance of first impedance matching network 106 connected between active high power path 102 and inactive low power path 104 is at least ten times greater than an input impedance of third impedance matching network 110 .

FIG. 1 c is an exemplary block diagram of the multi-mode RF power amplifier circuit 100 working under the low power mode, in accordance with an embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 1 c ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers. Further, power amplifier circuit 100 (refer to FIG. 1 c ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ), except for second input switch 130 which has been switched on. The functional operation of components are identical in power amplifier circuit 100 (refer to FIG. 1 c ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical, except for second input switch 130 which has been switched on. Under the low power mode operation, second input switch 130 is switched on so that low power path 104 becomes the active path and first input switch 122 is switched off so that high power path 102 becomes an inactive path. Therefore, one or more power amplifiers 124 present in low power path 104 amplifies the RF signal RF in .

In an embodiment of the invention, under the low power mode operation of power amplifier circuit 100 , isolation between the input terminals of high power path 102 and low power path 104 is achieved when an input impedance of fourth impedance matching network 116 satisfies a fourth pre-determined condition. According to the fourth pre-determined condition, an input impedance of fourth impedance matching network 116 of inactive high power path 102 is at least five times greater than an input impedance of fifth impedance matching network 126 of active low power path 104 . In accordance with another embodiment of the present disclosure, the input impedance of fourth impedance matching network 116 of inactive high power path 102 is ten times greater than an input impedance of fifth impedance matching network 126 of active low power path 104 . Therefore, the RF signal RF in applied to the input terminal of low power path 104 sees the high impedance presented by inactive high power path 102 and is coupled to fifth impedance matching network 126 .

Under the low power mode operation of power amplifier circuit 100 , the maximum power level of active low power path 104 is determined by an input impedance of first impedance matching network 106 connected between the output terminal of active low power path 104 and the output terminal of inactive high power path 102 . Under the low power mode operation, an input impedance of first impedance matching network 106 satisfies a third pre-determined condition. According to the third pre-determined condition, the input impedance of first impedance matching network 106 is comparatively greater than an input impedance of third impedance matching network 110 .

It will be readily apparent to one skilled in the art that impedance matching networks 106 , 108 , 110 , 116 , 118 , 120 , 126 and 128 shown in the FIG. 1 can be realized as either lumped passive components (capacitors, inductors and resistors) or distributed components or a combination of both.

Further, first input switch 122 and second input switch 130 can be realized in various mechanical or solid state technologies such as Microelectromechanical systems (MEMS), a Field Effect Transistor (FET), a Metal Semiconductor Field Effect Transistor (MESFET), a High Electron Mobility Transistor (HEMT), a Bipolar Junction Transistor (BJT), p-n diodes, and PIN diodes. Furthermore, the above mentioned technologies can be fabricated in various material systems such as bulk Si, Silicon On Insulator (SOI), Silicon On Sapphire (SOS), III-IV compound semiconductor such as Gallium Arsenide (GaAs) and Indium Phosphide (InP).

FIG. 2 a is an exemplary detailed circuit implementation of a multi-mode RF power amplifier circuit 200 , in accordance with an embodiment of the invention. Power amplifier circuit 200 (refer to FIG. 2 a ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ). Further, power amplifier circuit 200 (refer to FIG. 2 a ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ). The functional operation of components are identical in power amplifier circuit 200 (refer to FIG. 2 a ) and power amplifier circuit 100 (refer to FIG. 1 a ) is also identical.

First power amplifier 212 , second power amplifier 214 , and third power amplifier 224 respectively corresponds to first power amplifier 112 , second power amplifier 114 and third power amplifier 124 . In an embodiment, power amplifiers 212 , 214 , and 224 are shown in FIG. 2 a to include a transistor. The transistor can be realized in various mechanical or solid state technologies such as a Bipolar Junction Transistor (BJT), Field Effect Transistor (FET), a Hetero Junction Transistor (HJT), a Pseudomorphic High Electron Mobility Transistor (pHEMT), Complementary-symmetry Metal Oxide Semiconductor (CMOS), Laterally Diffused Metal Oxide Semiconductor (LDMOS), and Bipolar Complementary-symmetry Metal Oxide Semiconductor (BiCMOS). Further, the above mentioned technologies can be fabricated in various material systems such as bulk Si, Silicon On Insulator (SOI), Silicon On Sapphire (SOS), and III-IV compound semiconductor such as Gallium Arsenide (GaAs) and Indium Phosphide (InP).

First impedance matching network 206 , second impedance matching network 208 , third impedance matching network 210 , fourth impedance matching network 216 , fifth impedance matching network 226 , sixth impedance matching network 218 , seventh impedance matching network 228 , and eighth impedance matching network 220 corresponds to first impedance matching network 106 , second impedance matching network 108 , third impedance matching network 110 , fourth impedance matching network 116 , fifth impedance matching network 126 , sixth impedance matching network 118 , seventh impedance matching network 128 , and eighth impedance matching network 120 respectively.

Second impedance matching network 208 includes a capacitor C 1 . Fourth impedance matching network 216 includes a capacitor C 2 . Sixth impedance matching network 218 includes a capacitor C 3 , a capacitor C 4 and an inductor L 4 . A first terminal of the capacitor C 3 is connected to the input terminal of sixth impedance matching network 218 . A second terminal of the capacitor C 3 is connected to a node N 5 . A first terminal of the capacitor C 4 is connected to the node N 5 . A second terminal of the capacitor C 4 is connected to the output terminal of sixth impedance matching network 218 . A first terminal of the inductor L 4 is connected to the node N 5 and a second terminal of the inductor L 4 is connected to a ground.

Eighth impedance matching network 220 includes a capacitor C 5 , a capacitor C 6 and an inductor L 5 . A first terminal of the capacitor C 5 is connected to the input terminal of eighth impedance matching network 220 . A second terminal of the capacitor C 5 is connected to a node N 6 . A first terminal of the capacitor C 6 is connected to node N 6 . A second terminal of the capacitor C 6 is connected to the output terminal of eighth impedance matching network 220 . A first terminal of the inductor L 5 is connected to the node N 6 and a second terminal of the inductor L 5 is connected to the ground.

Third impedance matching network 210 includes an inductor L 6 , a capacitor C 7 and a capacitor C 8 . The first terminal of the inductor L 6 is connected to the input terminal of third impedance matching network 210 . A second terminal of the inductor L 6 is connected to a node N 7 . A first terminal of the capacitor C 7 is connected to the node N 7 . A second terminal of the capacitor C 7 is connected to the output terminal of third impedance matching network 210 . A first terminal of the capacitor C 8 is connected to the node N 7 . A second terminal of the capacitor C 8 is connected to the ground.

Fifth impedance matching network 226 includes a capacitor C 9 . Seventh impedance matching network 228 includes an inductor L 7 , a capacitor C 10 and a capacitor C 11 . A first terminal of the inductor L 7 is connected to the input terminal of seventh impedance matching network 228 . A second terminal of the inductor L 7 is connected to a first terminal of the capacitor C 11 . A second terminal of the capacitor C 11 is connected to the output terminal of seventh impedance matching network 228 . A first terminal of the capacitor C 10 is connected to the input terminal of seventh impedance matching network 228 . A second terminal of the capacitor C 10 is connected to the ground.

In an embodiment, first impedance matching network 206 includes an inductor L 8 , an inductor L 9 , a capacitor C 12 , a capacitor C 13 and a capacitor C 14 . A first terminal of the inductor L 8 is connected to the input terminal of first impedance matching network 206 . A second terminal of the inductor L 8 is connected to a first terminal of the capacitor C 12 . A second terminal of the capacitor C 12 is connected to the ground. A first terminal of the capacitor C 13 is connected to the input terminal of first impedance matching network 206 . A second terminal of the capacitor C 13 is connected to a node N 8 . A first terminal of the capacitor C 14 is connected to the node N 8 . A second terminal of the capacitor C 14 is connected to the ground. A first terminal of the inductor L 9 is connected to the node N 8 and a second terminal of the inductor L 9 is connected to the output terminal of first impedance matching network 206 .

First input switch 222 and second input switch 230 respectively correspond to first input switch 122 and second input switch 130 as shown in FIG. 1 a . In an embodiment, each first input switch 222 and second input switch 230 is shown as a transistor switch in FIG. 2 a.

FIG. 2 b is an exemplary detailed circuit implementation of multi-mode RF power amplifier circuit 200 , in accordance with another embodiment of the invention. Power amplifier circuit 200 (refer to FIG. 2 b ) has a component connection configuration identical to power amplifier circuit 200 (refer to FIG. 2 a ). Further, power amplifier circuit 200 (refer to FIG. 2 b ) includes the elements illustrated to be a part of power amplifier circuit 200 (refer to FIG. 2 a ) and using the same reference numbers. The functional operation of components shown to be identical in power amplifier circuit 200 (refer to FIG. 2 b ) and power amplifier circuit 200 (refer to FIG. 2 a ) is identical. Further, power amplifier circuit 200 (refer to FIG. 2 b ) has a component connection configuration identical to power amplifier circuit 200 (refer to FIG. 2 a ), except for the connection of the first terminal of the inductor L 3 which is shown to be connected to the second terminal of the inductor L 8 .

In the power amplifier circuit 200 shown in FIG. 2 b , a part of the inductor L 3 is absorbed into the inductor L 8 . Hence, the value and size of the inductor L 3 in FIG. 2 b would be smaller than that of the inductor L 3 shown in the FIG. 2 a.

The input impedances of the impedance matching circuits (such as first impedance matching network 106 , second impedance matching network 108 , third impedance matching network 110 , fourth impedance matching network 116 , fifth impedance matching network 126 , sixth impedance matching network 118 , seventh impedance matching network 128 , and eighth impedance matching network 120 ) depend on values of the inductors (such as L 4 , L 5 , L 6 , L 7 , and L 8 ) and capacitors (such as C 1 , C 2 , C 3 , C 4 , C 5 , C 6 , C 7 , C 8 , C 9 , C 10 , C 11 , C 12 , C 13 , and C 14 ) that form the impedance matching circuits. Accordingly, the pre-determined conditions (such as the first pre-determined condition, the second pre-determined condition, the third pre-determined condition, the fourth pre-determined condition, the fifth pre-determined condition, the sixth pre-determined condition, the seventh pre-determined condition, and the eight pre-determined condition) also depend on the values of the inductors and the capacitors that form the impedance matching circuits.

FIG. 3 is an exemplary detailed implementation of a multi-mode RF power amplifier circuit 300 , in accordance with another embodiment of the invention. Power amplifier circuit 300 includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) except for the inclusion of a reference voltage generator 302 , a control logic 304 , and bias circuits 306 a , 306 b , and 306 c . The component connection configuration and the functional operation of components shown to be identical in power amplifier circuit 100 (refer to FIG. 1 a ) and power amplifier circuit 300 is identical.

A first terminal of each bias circuit 306 a , 306 b , and 306 c is connected to control logic 304 . Control logic 304 is, in turn, connected to reference voltage generator 302 . A second terminal of each bias circuits 306 a , 306 b and, 306 c is respectively connected to a bias terminal of first power amplifier 112 , second power amplifier 114 and third power amplifier 124 .

A battery voltage V batt and an enabling voltage V enable is applied to reference voltage generator 302 . Reference voltage generator 302 generates a reference voltage based on the V batt and V enable . The reference voltage is applied to control logic 304 . Control logic further receives a voltage V mode which enables power amplifier circuit 300 to operate in one of the two power modes of operation. Output terminals of control logic 304 are coupled to each of bias circuits 306 a , 306 b and 306 c , first input switch 122 , and second input switch 130 . Bias circuits 306 a , 306 b and 306 c are respectively connected to power amplifiers 112 , 114 and 124 .

Bias circuits 306 a , 306 b and 306 c provide biasing voltage to power amplifiers 112 , 114 , and 124 respectively. Control logic 304 controls switching on and off of input switches 122 and 130 , and power amplifiers 112 , 114 , and 124 . Control logic 304 enables power amplifier circuit 300 to operate in one of the high power mode and the low power mode by activating the corresponding power amplification path and deactivating the other power amplification path. Control logic 304 enables an active power amplification path by switching on the corresponding input switch and turning on the power amplifiers connected in the power amplification path by biasing the corresponding bias circuits. Control logic 304 disables an inactive power amplification path by switching off the corresponding input switch and turning off the power amplifiers connected in the power amplification path by unbiasing the corresponding bias circuits. For example, under high power mode operation, control logic 304 enables high power path 102 to be active by switching on first input switch 122 and turning on power amplifiers 112 and 114 . Further, under high power mode operation, control logic 304 disables low power path 104 to be inactive by switching off second input switch 130 and turning off power amplifier 124 .

FIG. 4 a is an exemplary block diagram illustrating multi-mode RF power amplifier circuit 100 implemented with only one switch, in accordance with an embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 4 a ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers except for the exclusion of second input switch 130 and seventh impedance matching network 128 from low power path 104 . Power amplifier circuit 100 (refer to FIG. 4 a ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ) except for the connection of the second terminal of fifth impedance matching circuit 126 and the input terminal of power amplifier 124 connected in low power path 104 . The functional operation of components shown to be identical in power amplifier circuit 100 (refer to FIG. 4 a ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical. In low power path 104 , the second terminal of fifth impedance matching circuit 126 is connected to the input terminal of power amplifier 124 . First input switch 122 is switched on when power amplifier circuit 100 operates in the high power mode and first input switch 122 remains switched off when power amplifier circuit 100 operates in the low power mode.

FIG. 4 b is an exemplary block diagram illustrating multi-mode RF power amplifier circuit 100 implemented with only one switch, in accordance with another embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 4 b ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers, except for the exclusion of first input switch 122 and sixth impedance matching network 118 from high power path 102 . Power amplifier circuit 100 (refer to FIG. 4 b ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ), except for the connections of the second terminal of fourth impedance matching network 116 and the input terminal of power amplifier 112 connected in high power path 102 . The functional operation of components shown to be identical in power amplifier circuit 100 (refer to FIG. 4 b ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical. In high power path 102 , the second terminal of fourth impedance matching network 116 is connected to the input terminal of power amplifier 112 . Second input switch 130 is switched off when power amplifier circuit 100 operates in the high power mode and second input switch 130 remains switched on when power amplifier circuit 100 operates in the low power mode.

Multi-mode RF power amplifier circuitry implemented with only one switch is advantageous due to a reduction in chip size, simplified design and layout, and reduced cost.

FIG. 5 a is an exemplary block diagram illustrating multi-mode RF power amplifier circuit 100 implemented with a shared bias, in accordance with an embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 5 a ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers, except for the exclusion of the inductor L 3 from low power path 104 . Power amplifier circuit 100 (refer to FIG. 5 a ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ). The functional operation of components shown to be identical in power amplifier circuit 100 (refer to FIG. 5 a ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical, except for the functional operation of the inductor L 2 . The inductor L 2 connected to the V cc acts as a shared V cc bias for power amplifiers 114 and 124 .

FIG. 5 b is an exemplary block diagram illustrating multi-mode RF power amplifier circuit 100 implemented with a shared bias, in accordance with another embodiment of the invention. Power amplifier circuit 100 (refer to FIG. 5 b ) includes the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers, except for the exclusion of the inductor L 2 from high power path 102 . Power amplifier circuit 100 (refer to FIG. 5 b ) has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ). The functional operation of components shown to be identical in power amplifier circuit 100 (refer to FIG. 5 b ) and power amplifier circuit 100 (refer to FIG. 1 a ) is identical, except for the functional operation of the inductor L 3 . The inductor L 3 connected to the V cc acts as a shared V cc bias for power amplifiers 114 and 124 .

By using the shared bias in the RF power amplifier circuit, a large inductor can be eliminated from the amplifier circuit. As a result, the chip size and the cost can be reduced, and routing is simplified.

FIG. 6 is an exemplary block diagram illustrating a multi-mode RF power amplifier circuit 600 implemented with multiple low power paths, in accordance with an embodiment of the invention. Power amplifier circuit 600 includes high power path 102 and one or more low power paths 104 a , 104 b , and 104 n . High power path 102 and each low power path 104 a , 104 b and 104 n include the elements illustrated to be a part of power amplifier circuit 100 (refer to FIG. 1 a ) and using the same reference numbers, except for the exclusion of second power amplifier 114 and the inductor L 2 from high power path 102 . Further, high power path 102 and each low power path 104 a , 104 b , and 104 n has a component connection configuration identical to power amplifier circuit 100 (refer to FIG. 1 a ) except for the connection of the output terminal of power amplifier 112 of high power path 102 . The functional operation of components shown to be identical in power amplifier circuit 600 (refer to FIG. 6 ) and power amplifier circuit 100 (refer to FIG. 1 a ) is also identical.

In an embodiment of the invention, power amplifier circuit 600 operates over more than two power ranges and hence has more than two modes of operation. Each high power path 102 and low power path 104 a , 104 b , and 104 n is designed to operate over a pre-defined power range. Further, an optimum load impedance of each path is different from the other paths, such that the optimum load impedance of high power path 102 is lowest and the optimum load impedance of low power path 102 n is highest. When one of the power amplification paths is active, all the other power amplification paths are inactive. This is achieved by biasing the power amplifier corresponding to the active power amplification path and unbiasing the power amplifiers corresponding to the remaining inactive power amplification paths. Simultaneously, the input switch corresponding to the active power amplification path is switched on and the input switches corresponding to the remaining inactive power amplification paths are switched off. For example, under the high power mode operation, power amplifier 112 corresponding to high power path 102 is biased and input switch 122 corresponding to high power path 102 is switched on whereas, power amplifiers 124 a , 124 b and 124 n respectively corresponding to low power paths 104 a , 104 b , and 104 n are unbiased and input switch 130 a , 130 b , and 130 n respectively corresponding to low power paths 104 a , 104 b , and 104 n are switched off. Therefore, high power path 102 becomes active and low power paths 104 a , 104 b , and 104 n become inactive.

In an embodiment of the invention, under the high power mode operation of power amplifier circuit 600 , isolation between the input terminals of active high power path 102 and each inactive low power paths 104 a , 104 b and 104 n is achieved when an input impedance of fifth impedance matching networks 126 a , 126 b , and 126 n of inactive low power paths 104 a , 104 b , and 104 n satisfy a fifth pre-determined condition. According to the fifth pre-determined condition, the input impedance of fifth impedance matching network 126 a , 126 b , and 126 n of each of inactive low power paths 104 a , 104 b , and 104 n is comparatively greater than at least five times an input impedance of fourth impedance matching network 116 of high power path 102 . In accordance with another embodiment of the present disclosure, the input impedance of fifth impedance matching network 126 a , 126 b , and 126 n of each of inactive low power paths 104 a , 104 b , and 104 n is ten times greater than an input impedance of fourth impedance matching network 116 of active high power path 102 . Therefore, the RF signal RF in applied to the input terminal of high power path 102 sees the high impedance presented by inactive low power paths 104 a , 104 b , and 104 n and is coupled to fourth impedance matching network 116 .

Under the high power mode operation of power amplifier circuit 600 , isolation between the output terminals of active high power path 102 and inactive low power paths 104 a , 104 b and 104 n is achieved when an output impedance of first impedance matching network 106 a , 106 b and 106 c respectively connected between the output terminal of active high power path 102 and the output terminal of each inactive low power path 104 a , 104 b , and 104 c satisfies a first pre-determined condition. According to the first pre-determined condition, the output impedance of first impedance matching network 106 a , 106 b , and 106 c respectively connected between the output terminal of active high power path 102 and the output terminal of each inactive low power path 104 a , 104 b , and 104 c is comparatively greater than at least five times an input impedance of third impedance matching network 110 . In accordance with another embodiment of the present disclosure, the output impedance of first impedance matching network 106 a , 106 b , and 106 c respectively connected between the output terminal of active high power path 102 and the output terminal of each inactive low power path 104 a , 104 b , and 104 c is at least ten times greater than an input impedance of third impedance matching network 110 .

In an embodiment of the invention under the low power mode operation of power amplifier circuit 600 , one of low power amplification paths 104 a , 104 b , and 104 c is active and remaining low power amplification paths 104 a , 104 b , and 104 c are inactive. Simultaneously, high power path 102 is also inactive. For example, under low power mode operation, when low power path 104 a is active, the remaining low power paths 104 b and 104 n , and high power path 102 are inactive. Input switch 130 a corresponding to active low power path 104 a is switched on. Input switches 130 b and 130 n corresponding to inactive low power paths 104 b and 104 n respectively, and input switch 122 corresponding to inactive high power path 102 are switched off. The description below is based on the above example. A person skilled in the art will appreciate, that the description given below can be applied to other examples without deviating from the scope of the invention.

Under the low power mode operation of power amplifier circuit 600 , isolation between the input terminals of inactive high power path 102 and active low power path 104 a is achieved when an input impedance of fourth impedance matching network 116 of inactive high power path 102 satisfies a fourth pre-determined condition. According to the fourth pre-determined condition, the input impedance of fourth impedance matching network 116 of inactive high power amplification path 102 is comparatively greater than at least five times an input impedance of fifth impedance matching network 126 a of active low power path 104 a . In accordance with another embodiment of the present disclosure, the input impedance of fourth impedance matching network 116 of inactive high power path 102 is ten times greater than an input impedance of fifth impedance matching network 126 a of active low power path 104 a . Therefore, the RF signal RF in applied to the input terminal of active low power path 104 a , sees the high impedance presented by inactive paths 102 , 104 b , and 104 n and is coupled to fifth impedance matching network 126 a of active low power path 104 a.

Under the low power mode operation of power amplifier circuit 600 , the maximum power level of active low power path 104 a is determined by an input impedance of first impedance matching network 106 a connected between the output terminal of active low power path 104 a and the output terminal of inactive high power path 102 . Under the low power mode operation, an input impedance of first impedance matching network 106 a satisfies a third pre-determined condition. According to the third pre-determined condition, the input impedance of the first impedance matching network 106 a connected between the output terminal of active low power path 104 a and the output terminal of inactive high power path 102 is comparatively greater than an input impedance of third impedance matching network 110 .

In an embodiment of the invention, under the low power mode operation of power amplifier circuit 600 , isolation between the output terminals of inactive high power path 102 and inactive low power paths 104 b and 104 n is achieved when the output impedance of the first impedance matching networks 106 b and 106 n respectively connected between the output terminal of inactive high power path 102 and the output terminal of each inactive low power path 104 b and 104 n satisfies a second predefined condition. The second predefined condition is such that, the output impedance of the first impedance matching networks 106 b and 106 n , respectively connected between the output terminal of inactive high power path 102 and the output terminal of each inactive low power path 104 b and 104 n , is comparatively greater than at least five times an input impedance of third impedance matching network 110 . In accordance with another embodiment of the present disclosure, the output impedance of the first impedance matching networks 106 b and 106 n , respectively connected between the output terminal of inactive high power path 102 and the output terminal of the each inactive low power path 104 b and 104 n , is comparatively greater than at least ten times an input impedance of third impedance matching network 110 .

In an embodiment of the invention, under the low power mode operation of power amplifier circuit 600 , isolation between the input terminals of active low power path 104 a and the remaining inactive low power paths 104 b and 104 n is achieved when an input impedance of fifth impedance matching network 126 b and 126 n of each of inactive low power paths 104 b and 104 n satisfies a sixth pre-defined condition. The sixth pre-defined condition is such that the input impedance of fifth impedance matching network 126 b and 126 n of each inactive low power path 104 b and 104 n is comparatively greater than at least five times an input impedance of fifth impedance matching network 126 a of active low power path 104 a . In accordance with another embodiment of the present disclosure, the input impedance of fifth impedance matching network 126 b and 126 n of each inactive low power path 104 b and 104 n is comparatively greater than ten times an input impedance of fifth impedance matching network 126 a of active low power path 104 a.

FIG. 7 is a block diagram illustrating multi-mode RF power amplifier circuit 600 implemented with a shared bias for one or more low power paths, in accordance with an embodiment of the invention. Power amplifier circuit 600 includes the elements illustrated to be a part of power amplifier circuit 600 (refer to FIG. 6 ) and using the same reference number, except for the exclusion of the inductor L 3a , L 3b and L 3n from each low power paths 104 a , 104 b and 104 n . Power amplifier circuit 600 has a component connection configuration identical to power amplifier circuit 600 (refer to FIG. 6 ). The functional operation of components shown to be identical in power amplifier circuit 600 (refer to FIG. 7 ) and power amplifier circuit 600 (refer to FIG. 6 ) is identical, except for the functional operation of the inductor L 1 . The inductor L 1 connected to the V cc acts as a shared V cc bias for power amplifiers 112 , 124 a , 124 b , and 124 n.

By using the shared bias in the RF power amplifier circuit, a large inductor can be eliminated from the amplifier circuit. As a result, the chip size and the cost can be reduced, and routing is simplified.

Various embodiments of the invention provide several advantages. Negligible output power will be leaked into the inactive paths and its matching networks. This results in reduced current consumption and improved power added efficiency under the output power-back off operation.

Another advantage of the invention is the elimination of switches at an output of the active and inactive paths. Consequently, the power amplifier circuit of the invention will be able to operate under low bias voltage.

The power amplifier is capable of operating under dynamic bias supply, wherein the bias voltage is adjusted dynamically according to the output power of the RF power amplifier in order to further reduce current consumption under the power back-off operation.

While various embodiments of the invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art, without departing from the basic scope and spirit of the invention, as described in the claims that follow.