ESD protection circuit

This application claims the benefit of Taiwan application Serial No. 100115270, filed on Apr. 29, 2011, the subject matter of which is incorporated herein by reference.

The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit based on silicon controlled rectifier (SCR).

Chips and/or Integrated circuits are the most essential hardware foundation of the modern information society. To exchange signals with external circuits, a chip includes input/output ( 10 ) pads; to drain supply power for operation, the chip is also equipped with supply pads, such as power pads and ground pads respectively coupled to power voltage(s) and ground voltage(s). However, ESD of high voltage also conducts to internal circuits of a chip through pads of the chip; to prevent the internal circuits from damages of ESD, a chip needs to include ESD protection circuits. An ESD protection circuit provides a conduction path for discharging ESD current when ESD occurs, so the large ESD current will not jeopardize internal circuits of a chip.

Among various techniques of ESD protection, one kind of ESD protection technique is based on SCR. For a given layout area, an SCR conducts more current than other kinds of semiconductor devices, and high capability of current conduction is one of important demands for ESD protection. However, there are many problems to be overcome for SCR-based ESD protection. For example, an SCR needs to be triggered by a higher trigger voltage, and suffers a lower holding voltage; as the trigger voltage is high, the SCR can not quickly respond ESD events. After an SCR is turned on, it keeps conducting if the voltage applied to the SCR is higher than the holding voltage; as the holding voltage is low, the SCR conducts during normal operation of the chip, and hence affects operation of other internal circuits inside the chip.

Prior SCR-based ESD protection techniques can be briefly described as follows. In a prior art, such as the article “GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes”, Electrical Overstress/Electrostatic Discharge Symposium, 2001 by Russ et al., an SCR cooperates with a gate-grounded metal-oxide-semiconductor (MOS) transistor to lower the trigger voltage. Furthermore, SCR-based ESD protection techniques are also mentioned in U.S. patent/application such as U.S. Pat. No. 7,589,994, US2002/0130366, US2007/0096213, US2009/0268359 and US2010/0027173, etc.

To improve SCR-based ESD protection technique, the invention provides an SCR-based ESD protection in cooperating with a trigger circuit; the trigger circuit speeds up triggering of SCR, and further provides a parasitic shunt SCR to contribute more current conduction capability during ESD events.

An objective of the invention is to provide an ESD protection circuit includes a first SCR and a trigger circuit. The first SCR has a first coupling terminal, a second coupling terminal and a control terminal; the first coupling terminal and the second coupling terminal are respectively coupled to an anode terminal and a cathode terminal. The trigger circuit includes a first MOS transistor and a second transistor. The first MOS transistor has a first node, a second node and a third node; the first node and the third node are respectively coupled to the control terminal and the second coupling terminal. The second transistor has a fourth node and a fifth node; the fourth node is coupled to the anode terminal, and the fifth node is coupled to the second node. The first MOS transistor and the second transistor provide a second SCR between the first coupling terminal and the second coupling terminal.

Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIG. 1 illustrates an ESD protection circuit according to an embodiment of the invention;

FIG. 2 illustrates a layout of an ESD protection circuit according to an embodiment of the invention; and

FIG. 3 to FIG. 10 illustrate ESD protection circuits according to different embodiments of the invention.

Please refer to FIG. 1 illustrating an ESD protection circuit 10 a according to an embodiment of the invention. The ESD protection circuit 10 a includes an SCR 12 a , a trigger circuit 14 a and two optional serial circuits 16 a and 18 . Nodes na and nc respectively work as an anode terminal and a cathode terminal of the ESD circuit 10 a ; nodes na and n 2 are two coupling terminals of the SCR 12 a , and the node n 2 is coupled to the node nc through the serial circuit 16 a . A node n 0 can be regarded as a control terminal of the SCR 12 a . In this embodiment, the SCR 12 a is formed by two transistors Q 1 and Q 2 , and a resistor R 0 . The transistor Q 1 can be an NPN bipolar junction transistor with an emitter, a base and a collector respectively coupled to the nodes na, n 0 and n 3 . The transistor Q 2 can be a PNP bipolar junction transistor with an emitter, a base and a collector respectively coupled to the nodes n 2 , n 3 and n 0 . The resistor R 0 is coupled between the nodes n 2 and n 3 . Therefore, the transistors Q 1 and Q 2 form an SCR of alternate PNPN junctions between the nodes na and n 2 .

In the embodiment of FIG. 1 , the trigger circuit 14 a includes two transistors M 1 , M 2 and a resistor R 1 . The transistor M 1 can be an N-channel MOS transistor with a drain, a bulk, a source and a gate respectively coupled to the nodes n 0 , n 3 , n 2 and n 1 . The transistor M 2 can be a P-channel MOS transistor having a drain, a bulk, a source and a gate, the drain is coupled to the node n 1 , the bulk, the source and the gate are commonly coupled to the node na. The resistor R 1 is coupled between the nodes n 1 and n 2 .

Two terminals of the serial circuit 16 a are respectively coupled to the nodes n 2 and nc. The serial circuit 16 a can includes a predetermined number of diodes D 1 , each diode D 1 is serially coupled between the nodes n 2 and nc. The serial circuit 16 a can exclude any diode D 1 , i.e., the serial circuit 16 a can be omitted, the node n 2 can be directly merged to the node nc. The serial circuit 16 a can include a single diode D 1 with an anode and a cathode respectively coupled to the nodes n 2 and nc. The serial circuit 16 a can also include a plurality of diodes D 1 , one of the diodes D 1 has an anode coupled to the node n 2 , another of the diodes D 1 has a cathode coupled to the node nc; among the rest diodes D 1 , each diode D 1 has a cathode coupled to an anode of another diode D 1 .

The serial circuit 18 has two terminals respectively coupled to the nodes na and nc. The serial circuit 18 can include a predetermined number of diodes D 2 serially coupled between the node na and nc. The serial circuit 18 can exclude any diode D 2 ; that is, the serial circuit 18 can be omitted. The serial circuit 18 can include only a single diode D 2 with an anode and a cathode respectively coupled to the nodes nc and na. In an alternative embodiment, the serial circuit 18 includes a plurality of diodes D 2 , one of the diodes D 2 has an anode coupled to the node nc, another of the diodes D 2 has a cathode coupled to the node na; among the rest diodes D 2 , each diode D 2 has a cathode coupled to an anode of another diode D 2 .

The ESD protection circuit 10 a can be installed in a chip to protect internal circuits of the chip. For example, the node na can be coupled to a power pad or a signal 10 pad, and the node nc can be coupled to the ground voltage inside the chip.

Operation of the ESD protection circuit 10 a can be described as follows. In the trigger circuit 14 a , the transistor M 2 provides an equivalent (a parasitic) capacitor between the nodes na and n 1 , and the transistors M 1 and M 2 commonly provide a parasitic SCR 12 b between the nodes na and n 2 . When ESD occurs between the nodes na and nc to cause a rapidly rising strong positive voltage at the node na, the high voltage at the node na will be coupled to the node n 1 through the capacitor provided by the transistor M 2 , consequently the voltage at the node n 1 follows to rise. Hence, the transistor M 1 turns on to drain current from the node n 0 , the SCR 12 a is therefore trigged to turn on and starts to conduct current between the nodes na and n 2 ; at the same time, the SCR 12 b also turns on, so the SCR 12 a and SCR 12 b cooperate to conduct ESD currents from the node na to the node n 2 and node nc. Because the SCRs 12 a and 12 b are parallel-shunt between the nodes na and n 2 , currents conducted by the two SCRs add together to enhance ESD protection capability and efficiency (ESD current conducted per unit layout area).

On the other hand, when the chip powers on and enters normal operation, the capacitor provided by the transistor M 2 causes the voltage at the node n 1 to reach the voltage at the node n 2 , so the transistor M 1 turns off to stop conducting, hence the SCRs 12 a and 12 b also turn off, and thus normal operation of the chip is not affected.

Formation of the SCR 12 b by the trigger circuit 14 a can be further explained with FIG. 2 which illustrates a circuit layout 20 and its cross-section for implementing the ESD protection circuit 10 a according to an embodiment of the invention. The circuit layout 20 includes two N-wells NW 1 and NW 2 , regions a 1 to a 8 , g 1 and g 2 , as well as conductive routings r 1 to r 5 . The regions a 1 , a 2 , a 5 , a 6 and a 7 are P+ doped regions; the regions a 3 , a 4 and a 8 are N+ doped regions. The regions a 1 and a 2 are formed in the N-well NW 1 to respectively become the emitter and the base of the transistor Q 1 , and substrate of the circuit layout 20 forms the collector of the transistor Q 1 . The region a 3 , a 4 and the gate region g 1 respectively form the drain, the source and the gate of the transistor M 1 ; the routing r 2 conducts between the regions a 2 and a 3 , and the regions a 3 , a 4 and the substrate also form the collector, the emitter and the base of the transistor Q 2 , respectively. Resistance between the substrate and the region a 5 forms the resistor R 0 ; the routing r 3 conducts the regions a 4 and a 5 . The regions a 6 , g 2 and a 7 respectively form the source, the gate and the drain of the transistor M 2 .

For the regions a 3 , a 4 and a 6 , a 7 forming the transistors M 1 and M 2 , a parasitic PNP bipolar junction transistor Q 2 s is formed between the region a 4 , the substrate and the N-well NW 2 , and another parasitic NPN bipolar junction transistor Q 1 s is formed between the region a 6 , the N-well NW 2 and the substrate; resistance between the region a 5 and the substrate forms the resistor Rs. The routings r 1 , r 4 and r 5 conduct the regions a 1 , a 6 and a 8 to the same node na; the regions g 1 and a 7 are also conducted to the same node n 2 . Therefore, the transistor Q 1 s , Q 2 s and the resistor Rs form the parasitic SCR 12 b ( FIG. 1 ).

In other words, the trigger circuit 14 a of the invention not only triggers the SCR 12 a , but also provides another SCR 12 b by itself. When the trigger circuit 14 a causes the SCR 12 a to turn on, the SCR 12 b also turns on together; as the two SCRs are shunt, current conduction capability between the nodes na and n 2 is enhanced during ESD protection.

In the ESD protection circuit 10 a , the serial circuit 16 a can improve the holding voltages of the SCRs 12 a / 12 b , also suppress leakage currents of the SCR 12 a and the trigger circuit 14 a . In a chip of modern advanced process, because the chip can operate under lower power voltage, even the holding voltage of SCR is lower, incorrect triggering of SCR is rare. Therefore, the serial circuit 16 a can be omitted. The serial circuit 18 is adopted to protect positive ESD striking at the node nc; when ESD occurs between the nodes nc and na with a strong positive voltage rising at the node nc against the node na, the diode(s) D 2 of the serial circuit 18 will conduct from its anode to cathode, so the ESD current of the node nc can be conducted to the node na.

Please refer to FIG. 3 illustrating an ESD protection circuit 10 b according to an embodiment of the invention. The ESD protection circuit 10 b includes an SCR 12 a , a trigger circuit 14 b , serial circuits 16 b and 18 , and a feedback circuit 22 . The trigger circuit 14 b includes two transistors M 1 and M 2 ; a drain, a bulk, a gate and a source of the transistor M 1 are respectively coupled to the nodes n 0 , n 3 , n 1 and n 2 ; a source, a gate and a bulk of the transistor M 2 are commonly coupled to the node na, and a drain of the transistor M 2 is coupled to the gate of the transistor M 1 at the node n 1 .

In association with circuit architecture of the trigger circuit 14 b , the serial circuit 16 b includes a first number of diodes D 1 a , a second number of diodes D 1 b and a resistor Rf. An anode and a cathode of each diode D 1 a are serially coupled between the nodes n 2 and nf, an anode and a cathode of each diode D 2 a are serially coupled between the nodes nf and the resistor Rf; the node nf, as a feedback terminal, is coupled to the node n 1 through the feedback circuit 22 (e.g., a wire). The first number can be zero (none), one or multiple; the second number can be zero, one or multiple. The diodes D 1 a and D 2 a can be matched diodes, or different diodes.

Similar to the embodiments in FIG. 1 and FIG. 2 , in the trigger circuit 14 b of FIG. 3 , the transistors M 1 and M 2 also provides a parasitic SCR 12 b between the nodes na and n 2 . When ESD occurs between the nodes na and nc with the voltage at the node na rising, the transistor M 2 provides a capacitor between the nodes na and n 1 , the high voltage of the node na is thus coupled to the node n 1 , so the transistor M 1 turns on to trigger the SCR 12 a , and hence the SCR 12 a turns on also; meanwhile, the SCR 12 b turns on, too. Under such arrangement, the SCRs 12 a and 12 b both conduct ESD currents from the node na to the node n 2 for ESD protection.

During ESD, if the capacitor provided by the transistor M 2 between the nodes na and n 1 is small (of less capacitance), the voltage at the node n 1 falls more quickly. However, when the ESD current is conducted to the node nc from the node n 2 , a voltage is built across the resistor Rf, and is fed back to the node n 1 , i.e., the gate of the transistor M 1 , through the node nf. During an interval when ESD continues, the transistor M 1 will be kept turning on by the voltage fed back from the node nf, so the SCRs 12 a and 12 b are also kept conducting.

Please refer to FIG. 4 illustrating an ESD protection circuit 10 c according to an embodiment of the invention. Similar to the embodiment of FIG. 1 , the ESD protection circuit 10 c also includes an SCR 12 a , a trigger circuit 14 c and serial circuits 16 a and 18 ; the trigger circuit 14 c also includes two transistors M 1 , M 2 and a resistor R 1 ; the transistor M 2 provides a parasitic capacitor between the nodes na and n 1 , the transistors M 1 and M 2 also provide another SCR 12 b between the nodes na and n 2 . A difference is that, in the trigger circuit 14 c , a drain, a bulk, a gate and a source of the transistor M 1 are respectively coupled to the nodes na, n 3 , n 1 and n 2 . When ESD occurs between the nodes na and nc with a positive voltage striking the node na, the high voltage at the node na is coupled to the node n 1 by the transistor M 2 , such that the transistor M 1 turns on; the turned-on transistor M 1 will trigger the SCR 12 a with a bulk current conducted to a control terminal of the node n 3 , and thus both the SCRs 12 a and 12 b conduct ESD currents from the node na to the nodes n 2 and nc.

Please refer to FIG. 5 illustrating an ESD protection circuit 10 d according to an embodiment of the invention. The ESD protection circuit 10 d adopts the SCR 12 a , the serial circuits 16 a and 18 of the ESD protection circuit 10 a , and further includes a trigger circuit 14 d . The trigger circuit 14 d includes transistors M 1 , M 2 , M 3 , Mc and an inverter Iv. The transistors M 1 and M 3 can be N-channel MOS transistors; a drain, a bulk, a gate and a source of the transistor M 1 are respectively coupled to the nodes n 0 , n 3 , n 1 and n 2 , a drain and a gate of the transistor M 3 are coupled to a node n 4 , and a bulk and a source of the transistor M 3 are coupled to the node n 2 . The transistor M 2 can be a P-channel MOS transistor with a source and a bulk coupled to the node na, and a gate and a drain respectively coupled to nodes n 4 and n 1 b . Similar to the embodiments of FIG. 1 and FIG. 2 , the transistors M 1 and M 2 also form an SCR 12 b between the nodes na and n 2 ; on the other hand, the transistor M 2 provides a parasitic resistor between the nodes na and n 1 b . The transistor Mc can be a MOS transistor which functions as a capacitor coupled between the nodes n 1 b and n 2 . A drain and a source of the transistor Mc are coupled together at the node n 2 to form one terminal of the capacitor; a gate of the transistor Mc is coupled to the node n 1 b to form the other terminal of the capacitor. The inverter lv is coupled between the nodes n 1 b and n 1 .

When ESD occurs between the node na and nc with a rising voltage at the node na, a comparatively lower voltage at the node n 2 is coupled to the node n 1 b by the transistor Mc, so the voltage at the node n 1 b is low; the inverter lv inverts the low voltage at the node n 1 b to a high voltage at the node n 1 , and thus the transistor M 1 turns on. The turned-on transistor M 1 triggers the SCR 12 a to turn on, the SCR 12 b also turns on, and the SCRs 12 a and 12 b cooperate to conduct ESD currents from the node na to the nodes n 2 and nc.

Following the embodiment of FIG. 5 , please refer to FIG. 6 illustrating an ESD protection circuit 10 e according to an embodiment of the invention; the ESD protection circuit 10 e also includes an SCR 12 a , a trigger circuit 14 e and two serial circuits 16 a and 18 . Similar to the trigger circuit 14 d shown in FIG. 5 , the trigger circuit 14 e shown in FIG. 6 also includes transistors M 1 , M 2 , M 3 , Mc and an inverter lv, the transistor M 1 and M 2 also provides an SCR 12 b between the nodes na and n 2 ; a difference is that, a drain of the transistor M 1 is coupled to the node na. Operation of the trigger circuit 14 e is similar to operation of the trigger circuit 14 d , the transistor M 2 provides a resistor between the nodes na and n 1 b , the transistor Mc provides a capacitor between the nodes n 1 b and n 2 . When ESD occurs between the nodes na and nc to cause a rapidly rising voltage at the node na, the transistor Mc keeps a low voltage at the node n 1 b , hence the inverter Iv turns on the transistor M 1 by a high voltage at the node n 1 . The turned-on transistor M 1 triggers the SCR 12 a with the bulk of the transistor M 1 ; the SCR 12 b turns on at the same time to conduct ESD current along with the shunt SCR 12 a.

Please refer to FIG. 7 illustrating an ESD protection circuit 10 f according to an embodiment of the invention. The ESD protection 10 f adopts the SCR 12 a , the serial circuits 16 a and 18 of the ESD protection circuit 10 a , and includes a trigger circuit 14 f . The trigger circuit 14 f includes transistors M 1 , B 2 and a resistor R 1 . The transistor M 1 can be an N-channel MOS transistor with a drain, a bulk, a gate and a source respectively coupled to the nodes n 0 , n 3 , n 1 and n 2 . The transistor B 2 can be a PNP bipolar junction transistor with an emitter and a base coupled to the node na and a collector coupled to the node n 1 . The transistor B 2 provides a parasitic capacitor between the nodes na and n 1 ; the transistors M 1 and B 2 also form another SCR 12 b between the nodes na and n 2 .

When ESD event occurs between the nodes na and nc such that the voltage at the node na rises, the high voltage at the node na is coupled to the node n 1 by the capacitor provided by the transistor B 2 , hence the transistor M 1 turns on. The turned-on transistor M 1 triggers the SCR 12 a , thus the SCRs 12 a and 12 b together conduct ESD currents from the node na to the node nc.

Following the embodiment of FIG. 7 , please refer to FIG. 8 illustrating an ESD protection circuit 10 g according to an embodiment of the invention. The ESD protection circuit 10 g includes an SCR 12 a , a trigger circuit 14 g and two serial circuits 16 a and 18 . Similar to the trigger circuit 14 f shown in FIG. 7 , the trigger circuit 14 g also includes transistors M 1 and B 2 , and a resistor R 1 ; a difference is that, a drain of the transistor M 1 in coupled to the node na. Operation of the ESD protection circuit 10 g is analogous to operation of the ESD protection circuit 10 f.

Please refer to FIG. 9 illustrating an ESD protection circuit 10 h according to an embodiment of the invention. The ESD protection circuit 10 h adopts the SCR 12 a and the serial circuits 16 a and 18 of the ESD protection circuit 10 a , and includes a trigger circuit 14 h . The trigger circuit 14 h includes a transistor M 1 , a transistor DM 2 and a resistor R 1 . The transistor M 1 can be an N-channel MOS transistor with a drain, a bulk, a gate and a source respectively coupled to the nodes n 0 , n 3 , n 1 and n 2 . The transistor DM 2 is a diode with a cathode and an anode respectively coupled to the nodes na and n 1 . The transistor DM 2 provides a parasitic capacitor between the nodes na and n 1 ; the transistors M 1 and DM 2 also form another SCR 12 b between the nodes na and n 2 .

When ESD occurs between the nodes na and nc to cause a rising voltage at the node na, the high voltage at the node na is coupled to the node n 1 trough the transistor DM 2 , so the transistor M 1 turns on. The turned-on transistor M 1 triggers the SCR 12 a , such that the SCRs 12 a and 12 b cooperate to conduct ESD currents from the node na to the node nc.

In the embodiment of FIG. 9 , the drain of the transistor M 1 can also be coupled to the node na instead of the node n 0 .

Please refer to FIG. 10 illustrating an ESD protection circuit 10 i according to an embodiment of the invention; the ESD protection circuit 10 i adopts the SCR 12 a , the trigger circuit 14 and the serial circuit 16 a and 18 of the ESD protection circuit 10 a . The ESD protection circuit 10 i further includes a serial circuit 16 c and another serial circuit 18 b . Two terminals of the serial circuit 16 c are coupled between the nodes n 2 and nc 2 ; two terminals of the serial circuit 18 b are coupled between the nodes na and nc 2 . The serial circuit 16 c can include a predetermined number of diodes D 1 c , where the predetermined number can be zero, one or more. An anode and a cathode of each diode D 1 c are respectively coupled between the node n 2 and nc 2 . The serial circuit 18 b can include a predetermined number of diodes D 2 b , wherein the predetermined number can be zero, one or more; an anode and a cathode of each diode D 2 b are respectively coupled between the node nc 2 and na. In the chip equipped with the ESD protection circuit 10 i , the node nc and nc 2 can be respectively coupled to ground voltages of different power domains, such that the ESD protection circuit 10 i can perform ESD protection for different power domains. Different power domains can be domains applying different power voltages and/or different ground voltages within the same chip. The numbers of the diodes of the serial circuits 16 and 16 c can be the same or different, each diode D 1 and D 1 c can be matched or different. Similarly, the numbers of the diodes of the serial circuits 18 and 18 b can be the same or different, each diode D 2 and D 2 b can be matched or different.

Different but compatible portions shown in FIG. 1 and FIG. 3 to FIG. 10 can be selected and combined to form a coordinated ESD protection solution. For example, in the embodiment of FIG. 3 , the drain of the transistor M 1 can be coupled to the node na instead of n 0 , and the transistor M 2 can be replaced by the transistor B 2 ( FIG. 7 ) or DM 2 ( FIG. 9 ).

If a same chip includes multiple ESD protection circuits of the invention (like the ESD protection circuit 10 a ), the trigger circuits of different ESD protection circuits can be commonly coupled to a same node n 2 . Or, in each ESD protection circuit, the node n 2 of each of the different ESD protection circuits can be mutually isolated.

To sum up, comparing to the prior arts, the ESD protection circuit according to the invention includes the trigger circuit for rapid triggering the SCR when ESD occurs, thus the trigger voltage of the SCR is equivalently reduced. In addition, the trigger circuit itself provides another shunt SCR to enhance conduction capability of ESD current.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.