DC/DC converter and television using same

This application is based upon and claims the benefit of priority from the corresponding following Japanese Patent Applications, the entire contents of which are incorporated herein by reference.

(1) Japanese Patent Application No. 2011-048503 (filed Mar. 7, 2011) (2) Japanese Patent Application No. 2012-021852 (filed Feb. 3, 2012)

1. Field of the Invention

The present invention relates to a DC/DC converter, and in particular to a DC/DC converter using fixed ON time control.

2. Description of Related Art

DC/DC converters are widely adopted for use in power sources for liquid crystal televisions, digital versatile disc (DVD) players, Blu-ray Disc players, plasma display panels (PDPs), and the like.

Patent document 1 (Unexamined Japanese Patent Application Publication No. 2008-29159) provides a DC/DC converter performing fixed ON time pulse frequency modulation (PFM) control, that has a simple control circuit configuration, lowers switching frequency under light loads to reduce power consumption, and operates at an approximately constant switching frequency under heavy loads regardless of variations in input/output voltage. For this purpose, the converter is provided with a control circuit that performs pulse frequency modulation control such that the switching element has a fixed ON time and a variable OFF time. The control circuit links the ON time of the switching element to variations in at least one of an input voltage and an output voltage. Specifically, the ON time of the switching element, i.e., a switching transistor supplying energy to an inductor, is reduced as input voltage increases, or increased as output voltage increases.

The control circuit described in Patent document 1 has an error amplifier for amplifying the error between the output voltage and a target voltage, an oscillator whose frequency increases or decreases based on an error signal output by the error amplifier, and a one-shot circuit that is triggered by a frequency signal output by the oscillator, generating a specific ON time. The one-shot circuit includes a capacitor, a current supply circuit that supplies charging current to the capacitor, and a voltage detecting circuit that detects whether the voltage of the capacitor has surpassed a preset voltage.

Patent document 2 (Unexamined Japanese Patent Application Publication No. 2009-148155) proposes an internal ripple generating, fixed ON time voltage regulator with increased output voltage accuracy for a DC/DC converter using fixed ON time control.

According to paragraph 3 of Patent document 2, an output capacitor with an arbitrary equivalent series resistance (ESR) value is provided for the purpose of improving output voltage accuracy. According to paragraph 0009, the voltage regulator using fixed ON time, i.e., constant ON time, control is a type of voltage regulator that uses ripple mode control. According to paragraph 0011, it is possible to minimize noise and reduce variation in load voltage by reducing the ripple, but this impedes ripple mode voltage regulation. Reducing ripple size also decreases the comparison voltage differential, greatly impeding swift and accurate comparison. U.S. Pat. Nos. 7,482,791 and 7,482,793 may be referred to as patents of the same family as patent document 2.

U.S. Pat. Nos. 7,443,148, 7,482,791, and 7482793 may be referred to as patents of the same family as patent document 3 (Unexamined Japanese Patent Application Publication No. 2009-148157). Patent document 3 relates to patent document 2, and proposes a constant ON time voltage regulator with an increased maximum duty cycle. Provided within is a DC/DC converter with a fixed (constant) ON time, minimum OFF time control loop. Patent document 3 includes a fixed ON time control circuit that receives an input voltage, provides a switching output voltage on a switch output node using a minimum ON time, variable OFF time feedback control loop, and generates a first signal for turning off a high-side switch at the expiration of a first ON time duration or at the expiration of a maximum ON time. The first ON time duration is at least a minimum ON time and is allowed to expand to a maximum ON time when the feedback voltage remains less than a reference voltage.

Patent document 4 (U.S. Pat. No. 7,714,547) discloses a fixed ON time switch mode DC/DC converter. In FIG. 1 therein, a fixed ON time DC/DC converter 10 , a regulation circuit 12 , a combining circuit 16 , and a slope signal generator 18 are provided. The regulation circuit 12 is provided with a comparator 14 , a one-shot timing circuit 30 , and an S-R flip flop 32 .

Patent document 5 (Unexamined Japanese Patent Application Publication No. 2010-226930) provides a DC/DC converter enabling stabilization of switching frequency. According to paragraph 0003 thereof, a fixed ON time DC/DC converter using a comparator compares an output voltage to a reference voltage, and controls (for instance, turns ON) a switch (transistor) for a constant period using a signal generated in accordance with the results of the comparison. Thus, output voltage is regulated by regulating the OFF period of the switch.

According to paragraph 0005 of patent document 5, when the input voltage, output voltage, or output current of the DC/DC converter using a comparator varies, the switching duty ratio of the switch varies. This causes switching frequency (switching period) to vary. Such variation in switching frequency forebodes difficulties in preventing noise generated by switching. This is because, when frequency is constant, it is possible to take noise prevention steps suitable for that frequency. Patent document 5 also points out that when a plurality of DC/DC converters are operated, a problem arises in that electromagnetic interference (EMI) noise is generated by the mutual interference among the plurality of switching frequencies arising from the differences in switching frequency between the DC/DC converters.

FIG. 3 illustrates a synchronous rectifier buck DC/DC converter using fixed ON time control subjected to an experiment conducted during the process of arriving at the present invention. Much of the circuitry of a DC/DC converter 30 is contained within an integrated circuit IC 3 . The integrated circuit IC 3 has a high-side transistor QH and a low-side transistor QL. The low-side transistor QL functions as a synchronous rectifier transistor. A first primary electrode D of the high-side transistor QH is connected to an input voltage VIN, and a second primary electrode S thereof is connected to a first primary electrode D of the low-side transistor QL.

The high-side transistor QH and the low-side transistor QL may both be configured as, for example, n-channel MOS transistors, but are not limited thereto. For instance, a combination of an n-channel and a p-channel MOS transistor is also acceptable. Rather than a MOS transistor, a bipolar transistor configuration is also acceptable.

A second primary electrode S of the low-side transistor QL is connected to a ground potential GND.

Drive signals SDH and SDL are input to control electrodes G of the high-side transistor QH and the low-side transistor QL, respectively. The drive signals SDH and SDL are synchronous with each other, and the polarities thereof are set so that the ON/OFF states of the high-side transistor QH and the low-side transistor QL are the inverse of each other.

This document uses the terms “first primary electrode”, “second primary electrode”, and “control electrode” to refer to the various transistor electrodes. In the case of a MOS transistor, a first primary electrode may at times be a drain electrode or a source electrode. Because a second primary electrode may likewise be at times a source electrode or a drain electrode, it is impossible to define the electrodes as one specific type. However, a control electrode may be defined as a gate electrode. The same applies in the case of a bipolar transistor. What is referred to as a first primary electrode may be at times a collector electrode or an emitter electrode, and what is referred to as a second primary electrode may be at times an emitter electrode or a collector electrode, making it impossible to define the electrode as either type. However, a control electrode may be defined as a base electrode.

The second primary electrode S of the high-side transistor QH and the first primary electrode D of the low-side transistor QL have a common connection, and the common connection point thereof is connected to an external terminal T 1 . The external terminal T 1 is one of the external terminals provided on the integrated circuit IC 3 , and in particular the external terminal T 1 is equivalent to the output terminal of the DC/DC converter 30 . The integrated circuit IC 3 has numerous terminals apart from the external terminal T 1 , but these have been omitted from the drawing for simplicity of description.

An inductor L 1 and an output capacitor C 1 are connected in series between the external terminal (output terminal) T 1 and the ground potential GND. An output voltage VOUT is output from the common connection point of the inductor L 1 and the output capacitor C 1 .

The input voltage VIN supplied to the first primary electrode D of the high-side transistor QH is stepped down to a lower voltage, and the output voltage VOUT is output from the second primary electrode S of the high-side transistor QH. The magnitudes of the input voltage VIN and the output voltage VOUT are, for example, 12V and 5V direct current voltages, respectively.

FIG. 3 depicts a synchronous rectifier buck DC/DC converter that also constitutes a fixed ON time control DC/DC converter. The fixed ON time control DC/DC converter 30 has a one-shot circuit 30 A.

The one-shot circuit 30 A outputs a one-shot pulse PS 1 to an output terminal of a comparator CMP 1 . The one-shot pulse PS 1 is inputted to, for example, an S-R flip flop not shown in the drawings.

The one-shot circuit 30 A has a current mirror circuit CM 1 . The current mirror circuit CM 1 has at least one pair of transistors with an MOS or bipolar configuration. A constant current I 1 is output from one terminal of the current mirror circuit CM 1 , and the constant current I 1 travels from a first primary electrode D of a transistor Q 1 to a second primary electrode S.

An inverting input terminal (−) of an operational amplifier OP 1 and the second primary electrode S of the transistor Q 1 have a common connection, and a resistor R 1 is connected to the common connection point thereof. For this reason, the constant current I 1 is determined by the voltage of the inverting input terminal (−) of the operational amplifier OP 1 and by the resistor R 1 . Due to the circuit operation of the operational amplifier OP 1 , the voltage of the inverting input terminal (−) of the operational amplifier OP 1 is equal to a reference voltage VB 1 input to a non-inverting input terminal (+) of the operational amplifier OP 1 . The reference voltage VB 1 is determined by the magnitudes of an input voltage VIN and resistors R 2 and R 3 . The constant current I 1 is accordingly expressed by numerical formula 1, where r 1 is the resistance value of the resistor R 1 .

The constant current I 1 generated by the operational amplifier OP 1 , transistor Q 1 , resistors R 1 through R 3 , and input voltage VIN is output from the other terminal of the current mirror circuit CM 1 , and charges a capacitor C 2 . The current charging the capacitor C 2 can be easily adjusted to be greater or smaller than the constant current I 1 depending on the configuration of the current mirror circuit CM 1 , but, for simplicity of description, is the same within an embodiment of the present invention.

When the capacitor C 2 is charged by the constant current I 1 , and a transistor Q 2 is switched ON and OFF at a specified interval, a ramp wave signal ST with superior linearity is generated at one terminal of the capacitor C 2 , i.e., the non-inverting input terminal (+) of the comparator CMP 1 . A one-shot pulse PS 1 is generated by this ramp wave signal ST.

The amplitude STP of the ramp wave signal ST is determined by a reference voltage VFB 3 of the inverting input terminal (−) of the comparator CMP 1 . The reference voltage VFB 3 is determined by an output voltage VOUT and resistors R 4 and R 5 . For instance, when the output voltage VOUT is 5V and the resistance values of the resistors R 4 and R 5 are 40 KΩ and 10 KΩ, respectively, the reference voltage VFB 3 is 1V. Thus, when the ramp wave signal ST reaches 1V, the output of the comparator CMP 1 transitions from a low level to a high level, and a one-shot pulse PS 1 having an ON period T ON1 is output.

The ON period T ON1 of the one-shot pulse PS 1 is expressed by numerical formula 2, where VIN is inputted voltage, VOUT is output voltage, r 1 is the resistance value of the constant current I 1 and the resistor R 1 , and c 2 is the capacity of the capacitor C 2 .

As is clear from numerical formula 2, the ON period T ON1 of the one-shot pulse PS 1 output from the one-shot circuit 30 A is inversely proportional to the input voltage VIN, and directly proportional to the reference voltage VFB 3 , i.e., the output voltage VOUT.

Stated otherwise, numerical formula 2 illustrates that when a fixed ON time control DC/DC converter is configured using the one-shot circuit 30 A, the ON period T ON1 of the switching element is dependent upon the respective magnitudes of the input voltage VIN and the output voltage VOUT.

The inventors discovered that, in a fixed ON time control DC/DC converter using the one-shot circuit 30 A, when the load current IL, i.e., the current traveling from the high-side transistor QH toward the inductor L 1 , increases, the ON resistance of the high-side transistor QH ceases to be negligible, and the ON duty ratio D ON of a switching signal SW varies. Specifically, even when the voltage drop in the high-side transistor QH is no longer negligible due to the ON resistance of the high-side transistor QH, because the output voltage VOUT is controlled so as to reach a specific magnitude of, for example, 5V by the circuit configuration of the DC/DC converter, the ON duty ratio D ON increases. Stated otherwise, the OFF period T OFF grows shorter, the period decreases, and the operating frequency of the DC/DC converter 30 increases.

When the operating frequency of the DC/DC converter 30 increases, the output voltage VOUT varies due to EMI noise prevention being impeded and the operating point of the ripple generating circuit in the DC/DC converter using a ripple generating circuit varying. The ripple generating circuit will be described below.

FIG. 4 is a schematic illustration of variations arising in the switching signal SW output to the external terminal T 1 of FIG. 3 . A switching signal SW 1 illustrates an instance where the load current IL flowing through the DC/DC converter 30 is comparatively low, i.e., the load is comparatively light; and a switching signal SW 2 illustrates an instance where the load current IL is comparatively great, i.e., the load is comparatively heavy.

When the load current IL is comparatively small or the ON resistance R ONH of the high-side transistor QH is comparatively low, i.e., when the load is comparatively light, the voltage drop caused by the ON resistance R ONH of the high-side transistor QH is negligible, meaning that the amplitude V PSW1 of the switching signal SW 1 is roughly equivalent to the input voltage VIN. Here, the switching signal SW 1 is illustrated by an ON period T ON1 , an OFF period T OFF1 , and a period T 1 . The period T 1 is expressed as T 1 =T ON1 +T OFF1 , and the ON duty ratio D ON1 of the switching signal SW 1 is expressed by D ON1 =T ON1 /(T ON1 +T OFF1 ).

When the load current IL is comparatively great or the ON resistance R ONH of the high-side transistor QH is comparatively great, i.e., when the load is comparatively heavy, the voltage drop caused by the ON resistance R ONH of the high-side transistor QH ceases to be negligible, meaning that the amplitude V PSW2 of the switching signal SW 2 does not reach the input voltage VIN, but drops by the amount of a voltage drop V drop . The voltage drop V drop is expressed as the product of the ON resistance R ONH of the high-side transistor QH and the load current IL; i.e., V drop =R ONH ×IL. The switching signal SW 2 is illustrated with an ON period T ON2 , an OFF period TOFF 2 , and a period T 2 . The period T 2 is expressed as T 2 =T ON2 ±T OFF2 , and the ON duty ratio D ON2 of the switching signal SW 2 is expressed as D ON2 =T ON2 /(T ON2 +T OFF2 ).

Even when the amplitude V PSW2 of the switching signal SW 2 decreases, because the output voltage VOUT is set to a specific amplitude of, for instance, 5V due to the circuit configuration of the DC/DC converter, the OFF period T OFF2 of the high-side transistor QH grows shorter, and the ON duty ratio D ON2 grows larger than the ON duty ratio D ON1 of the switching signal SW 1 . That is, the relationship T 2 <T 1 holds between the period T 2 of the switching signal SW 2 and the period T 1 of the switching signal SW 1 , and the frequency of the switching signal SW 2 is greater than that of the switching signal SW 1 .

Variation in the frequency of the switching signal SW 2 hampers prevention of noise caused by the switching of the high-side transistor QH. This is because, while it is possible to provide a band-pass filter that dampens the frequency components when the frequency is constant, such a measure is not possible when the operating frequency of the DC/DC converter 30 varies at random.

FIG. 5 depicts another DC/DC converter 50 provided so as to prevent noise. The DC/DC converter 50 , like that of FIG. 3 , is a synchronous rectifier buck DC/DC converter using fixed ON time control. The DC/DC converter 50 is characterized in particular in being provided with a ripple generating circuit RI. The DC/DC converter using fixed ON time (constant ON time) control is a ripple mode control type, as suggested by patent document 3.

The DC/DC converter 50 has an integrated circuit IC 5 . The integrated circuit 105 has at least external terminals T 1 , T 2 , T 3 , and T 4 . The external terminal T 1 is equivalent to the output terminal of the DC/DC converter 50 , with an inductor L 1 and a output capacitor C 1 connected in series between the external terminal T 1 from which a switching signal SW is output and a ground potential GND, and an output voltage VOUT is output from the common connection point of the inductor L 1 and the output capacitor C 1 .

The external terminal T 1 is disposed at the common connection point of a high-side transistor QH and a low-side transistor QL. The high-side transistor QH is disposed toward an input voltage VIN, and the low-side transistor QL is disposed by a ground potential GND. The high-side transistor QH, low-side transistor QL, inductor L 1 , output capacitor C 1 , input voltage VIN, and output voltage VOUT are the same as those illustrated in FIG. 3 .

The external terminal T 2 is provided so as to lead the inverting input terminal (−) of a comparator CMP 2 out of the integrated circuit IC 5 . A feedback voltage VFB 5 consisting of an output voltage VOUT divided by resistors R 11 and R 12 is returned to the external terminal T 2 .

The external terminal T 3 is provided in order to connect a capacitor C 6 that generates a soft start voltage VSS. Such soft start voltage VSS is often used in a DC/DC converter of this kind, and the purpose thereof is to smooth the startup operation of the DC/DC converter 50 . A constant current source CC 1 and a bandgap voltage circuit BG are connected to the external terminal T 3 .

The bandgap voltage circuit BG generates a bandgap voltage of, for instance, 1.2V that is not dependent upon the magnitude of a power source voltage VC 1 or changes in ambient temperature.

The reference voltage generated by the bandgap voltage circuit BG is used to define the upper limit value of the soft start voltage VSS, or to set the average voltage of the soft start voltage VSS.

In the ripple generating circuit RI, a ripple is superimposed upon the soft start voltage VSS. Properly described, the ripple generating circuit RI functions as a circuit for generating a pseudo-ripple component. The provision of the ripple generating circuit RI can increase the coverage of the output capacitor C 1 .

Normally, a ripple control DC/DC converter requires an amplitude of a certain size in order to accurately detect output ripple voltage. For this reason, an output capacitor C 1 with a comparatively great ESR must be provided. However, it is not preferable for ESR and ripple voltage amplitude to be increased, as this reduces noise resistance properties as well as load voltage properties.

When a ripple generating circuit RI is provided, it can be made to conform to an output capacitor C 1 having a desired ESR value. For instance, when the ESR of the output capacitor C 1 is high, either no ripple voltage is generated in the ripple generating circuit RI, or the amplitude thereof can be kept low. When the ESR of the output capacitor C 1 is low, the amplitude of the ripple voltage generated in the ripple generating circuit RI can be adjusted so as to be high. A specific example of the ripple generating circuit RI will be described below.

A soft start voltage VSS upon which a ripple voltage VRI is imposed is inputted as a reference voltage VREF 5 to a non-inverting input terminal (+) of a comparator CM 2 . An inverting input terminal (−) of the comparator CM 2 is connected to the external terminal T 2 . A feedback voltage VFB 5 consisting of an output voltage VOUT divided by resistors R 11 and R 12 is returned to the external terminal T 2 .

The comparator CMP 2 compares the reference voltage VREF 5 upon which the ripple voltage is imposed with the feedback voltage VFB 5 , and outputs a comparison signal V CMP2 . When the feedback voltage VFB 5 is greater than the reference voltage VREF 5 , the comparison signal V CMP2 is of a low level; and, contrariwise, when the feedback voltage VFB 5 is less than the reference voltage VREF 5 , the comparison signal V CMP2 is of a high level.

The comparison signal V CMP2 is inputted to a one-shot circuit OS 1 as well as to a set terminal S of an S-R flip flop FF.

The one-shot circuit OS 1 outputs a one-shot pulse PS 1 using the rising or falling edge of the comparison signal V CMP2 . An output voltage VOUT is input to the one-shot circuit OS 1 via the external terminal T 4 . In this way, the one-shot circuit OS 1 is retained at a specific circuit operating point by the output voltage VOUT.

The one-shot pulse PS 1 output by the one-shot circuit OS 1 is inputted to a reset terminal R of the S-R flip flop.

The S-R flip flop FF is set by the comparison signal V CMP2 , and outputs an output signal, reset by the one-shot pulse PS 1 , that is inputted to a driver DRV.

The driver DRV generates drive signals DRVH and DRVL for driving the high-side transistor QH and the low-side transistor QL, respectively. When the high-side transistor QH is in an ON state, the driver DRV generates a drive signal so that the low-side transistor QL switches to an OFF state. The drive signals DRVH and DRVL are not necessarily set at inverse polarities; when the high-side transistor QH and the low-side transistor QL are of different conducting types, drive signals of the same polarity are input synchronously.

The high-side transistor QH is connected to an input voltage VIN, and supplies energy to the inductor L 1 connected to the external terminal T 1 . The low-side transistor QL is provided in order to synchronously rectify the energy accumulated within the inductor L 1 .

The inventors also discovered that, because an external terminal T 2 for inputting the feedback voltage VFB 5 to the comparator CMP 2 must be provided in the integrated circuit IC 5 , the number of external terminals on the ripple control DC/DC converter 50 of FIG. 5 increases, and, because these terminals lead outside the integrated circuit IC 5 , noise resistance properties are reduced.

FIG. 6 illustrates a ripple generating circuit used in the ripple control DC/DC converter of FIG. 5 . A ripple generating circuit RI is generated using the switching signal SW output from the external terminal T 1 . The ripple generating circuit RI is constituted by an operational amplifier OP 2 , resistors R 9 and R 10 , and a capacitor C 3 . A reference voltage VR 1 is inputted to the non-inverting input terminal (+) of the operational amplifier OP 2 . A common connection point of the resistor R 9 and the resistor R 10 , and an end of the capacitor C 3 , are connected to the inverting input terminal (−) of the operational amplifier OP 2 . The resistor R 10 and the capacitor C 3 are connected in a row, and constitute a so-called integrating circuit. The switching signal SW is integrated by this integrating circuit and further amplified, and a ramp wave-shaped pseudo-ripple voltage DVR 1 is generated at the output of the operational amplifier OP 2 .

The technical field of the DC/DC converter according to the present invention is roughly in common with that of the fixed ON time control DC/DC converters disclosed in patent documents 1 through 5. The DC/DC converter according to the present invention provides a DC/DC converter enabling the problems with noise resistance properties discussed with reference to FIGS. 3 and 5 to be improved.

The DC/DC converter according to the present invention has an input voltage; an output terminal for converting the input voltage and outputting an output voltage; an inductor connected to the output terminal; a switching element having a first primary electrode connected to the input voltage and a second primary electrode connected to the output terminal in order for energy to be supplied to the inductor; an output capacitor for smoothing the energy accumulated within the inductor, and for outputting the output voltage; a feedback voltage generating circuit for feeding back to the switching element the output voltage generated in the output capacitor; and an adder for adding the on voltage of the switching element when on and the feedback voltage generated in the feedback voltage generating circuit.

Another DC/DC converter according to the present invention is a DC/DC converter having an input voltage; an output terminal for converting the input voltage and outputting an output voltage; a switching element for performing repeated switching between ON and OFF states, the switching element connected between the input voltage and the output terminal and having a first primary electrode, a second primary electrode, and a control electrode; an inductor connected to one of either the first primary electrode or the second primary electrode of the switching element; an output capacitor for smoothing the energy accumulated within the inductor; a feedback voltage generating circuit made of a first feedback resistor and a second feedback resistor for feeding back the output voltage to the switching element; and an integrated circuit for driving the switching element; wherein the first feedback resistor and the second feedback resistor are built into the integrated circuit.

The present invention is configured so as to increase the ON duty ratio as the ON voltage generated by the ON resistance of the high-side transistor, i.e., the switching element, increases, enabling defects such as shifts in the operating point of the DC/DC converter or variations in operating frequency to be eliminated, and reduction of noise resistance properties to be prevented. Another invention of the present invention is configured so that a feedback resistor for determining an output voltage is built into an integrated circuit, enabling defects such as a reduction in noise resistance properties caused by external noise to be minimized.

Further features, elements, steps, advantages, and characteristics of the present invention will become apparent from the detailed description of the best mode for embodying the invention and the attached drawings relating thereto given below.

FIG. 1 is a schematic circuit diagram of a DC/DC converter according to a first embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a DC/DC converter according to a second embodiment of the present invention;

FIG. 3 is an illustration of a synchronous rectifier buck DC/DC converter using fixed ON time control subjected to an experiment conducted in the process of arriving at the first embodiment of the present invention;

FIG. 4 is a schematic illustration of a switching signal output to a switching element of the DC/DC converter shown in FIG. 3 ;

FIG. 5 is an illustration of a synchronous rectifier buck DC/DC converter using fixed ON time control subjected to an experiment conducted during the process of arriving at the second embodiment of the present invention;

FIG. 6 is an illustration of a ripple generating circuit used in the DC/DC converter of FIG. 5 ;

FIG. 7 is a timing chart describing the operation of a DC/DC converter 10 ;

FIG. 8 is a block diagram of an example of one configuration of a television installed with a DC/DC converter;

FIG. 9A is a front view of a television installed with a DC/DC converter;

FIG. 9B is a side view of a television installed with a DC/DC converter; and

FIG. 9C is a rear view of a television installed with a DC/DC converter;

First Embodiment

FIG. 1 depicts a DC/DC converter according to a first embodiment of the present invention. A DC/DC converter 10 utilizes the many circuit components shown in FIG. 3 ; description of the operation of these circuit components shall be omitted. A high-side transistor QH corresponds to the switching element spoken of in the context of the present invention, and a low-side transistor QL functions as a synchronous rectification element.

Briefly put, the first embodiment of the present invention illustrated in FIG. 1 is characterized in having an input voltage VIN, an external terminal T 1 that converts the input voltage VIN and outputs an output voltage VOUT, an inductor L 1 connected to the external terminal T 1 , a high-side transistor (switching element) QH having a first primary electrode D connected to the input voltage VIN and a second primary electrode S connected to the inductor L 1 so as to supply energy to the inductor L 1 , an output capacitor C 1 that smoothes the energy accumulated in the inductor L 1 and from which the output voltage VOUT is output, a feedback voltage generating circuit (feedback voltage VOUT, feedback resistors R 4 and R 5 ) that returns the output voltage VOUT generated in the output capacitor C 1 to the high-side transistor (switching element) QH, and an adder CB that adds the ON voltage on the high-side transistor (switching element) QH when in an ON state and a feedback voltage VFB 1 generated in the feedback voltage generating circuit (output voltage VOUT, feedback resistors R 4 and R 5 ).

The ON voltage of the switching element QH when in an ON state is output from a detection transistor QD connected in a row with the switching element QH. This will be described in more detail below.

The first point of difference between the DC/DC converter 10 of FIG. 1 and the DC/DC converter 30 of FIG. 3 is that a detection transistor QD is incorporated in a row with the high-side transistor QH. The first primary electrode D of the high-side transistor QH has a common connection with a first primary electrode D of the detection transistor QD via a detection resistor RD. The second primary electrode S of the high-side transistor QH and a second primary electrode S of the detection transistor QD have a common connection. The common connection point thereof leads to the external terminal T 1 .

A value is selected for the resistance of the detection resistor RD that is sufficiently high compared to that of an ON resistor RQD of the detection transistor QD when in an ON state; i.e., such that RD≧RQD. This is because such conditions allow a voltage roughly equivalent to the voltage drop generated by the ON resistance of the high-side transistor QH to be output from one terminal of the detection resistor RD. It is not preferable that the detection resistor RD and the ON resistance RQD be roughly equal, as this will allow only about half of the voltage drop generated by the ON resistance of the high-side transistor QH to be output from one terminal of the detection resistor RD.

There is no restriction whatsoever upon the relationship between the physical size of the detection transistor QD and that of the high-side transistor QH. As a result, the physical size of the detection transistor QD can be determined independent of consideration of the high-side transistor QH. In general, however, the smaller the physical size of the detection transistor QD, the greater the ON resistance RQD becomes. The detection resistor RD may be connected to the second primary electrode S of the detection transistor QD rather than the first primary electrode D.

A second point of difference between the present invention shown in FIG. 1 and the device of FIG. 3 is that a level shifter LS has been provided. The level shifter LS is provided so as to shift a detection voltage VQD output from a detection transistor QD away from the input voltage VIN toward the ground potential GND. Because the detection voltage VQD takes the input voltage VIN, which has a comparatively high potential, as a reference, left as-is, combination with the subsequent adder CB is impeded. For this reason, the detection voltage VQD is shifted away from the high potential side toward the low potential side; i.e., toward the ground potential GND. Thus, the level shifter LS is provided for the sake of easily making a direct current combination with the subsequent circuit.

A detection voltage VQD 1 shifted from the high potential side toward the low potential side is output at the output of the level shifter LS. The magnitude of the detection voltage VQD 1 is expressed by VQD 1 =R ONH ×I O , wherein R ONH is the ON resistance of the high-side transistor QH, and I O is the output current flowing through the high-side transistor QH. The detection voltage VQD 1 is added to the feedback voltage VFB 1 at the adder CB.

A third point of difference is the provision of the adder CB. The adder CB is provided in order to take the ON voltage of the high-side transistor QH when in an ON state from the detection transistor QD as a detection voltage VQD, and to add this detection voltage VQD (more specifically, the detection voltage VQD 1 input via the level shifter LS) to the feedback voltage VFB 1 of the output voltage VOUT. The feedback voltage VFB 1 is determined by the feedback resistors R 4 and R 5 and the output voltage VOUT. Thus, the feedback resistors R 4 and R 5 and output voltage VOUT constitute a feedback voltage generating circuit.

The output voltage VOUT is effectively the output voltage of the DC/DC converter output from the common connection point of the inductor L 1 and the output capacitor C 1 .

As described above, the ON duty ratio D ON of the buck DC/DC converter is uniquely determined by the magnitudes of the input voltage VIN and the output voltage VOUT. However, the ratio obtained in this state ignores the ON resistances of the high-side transistor QH and the low-side transistor QL. However, the heavier the load on the DC/DC converter 10 , the less negligible the ON resistance becomes.

The ON resistances of the high-side transistor QH and the low-side transistor QL when in an ON state in FIG. 1 are expressed by numerical formulas 3 and 4, wherein R ONH and R ONL are the ON resistances of the high-side transistor QH and the low-side transistor QL, respectively, T ON is the ON period of the high-side transistor QH, T OFF is the OFF period, and ΔI ON and ΔI OFF are the increases in the current flowing through the inductor L 1 during each period. In numerical formulas 3 and 4, L represents the inductance of the inductor L 1 , and I O represents the magnitude of the output current supplied from the high-side transistor QH or the low-side transistor (synchronous rectifier transistor) QL. The current path from the low-side transistor QL to the inductor L 1 is formed during the OFF period T OFF of the high-side transistor QH.

In numerical formulas 3 and 4, when a current flowing through the inductor L 1 is connected, the load current flowing through the inductor L 1 neither increases nor decreases, so that ΔI ON =ΔI OFF ; thus, the on duty ratio D ON is expressed by numerical formula 5.

When the ON resistance R ONH of the high-side transistor QH and the ON resistance R ONL of the low-side transistor QL are equal, the on duty ratio D ON of numerical formula 5 can be expressed by numerical formula 6.

As is apparent from formula 6, in the first embodiment of the present invention, the on duty ratio D ON of the high-side transistor QH, that is, the switching element, can be set so as to be inversely proportional to the input voltage VIN, and directly proportional to the sum of the output voltage VOUT and the voltage that is the product of the ON resistance R ONH of the high-side transistor QH and the output current I O . This enables defects such as increases in output current I O and operating frequency to be eliminated, and prevents reductions in noise resistance properties before they occur.

The variable control of the ON period T ON of the DC/DC converter 10 is amply apparent from the description above; for the sake of deepened understanding, a specific description is given below with reference to FIG. 7 .

FIG. 7 is a timing chart describing the operation of the DC/DC converter 10 in more detail, and, like the previous FIG. 4 , schematically illustrates variations occurring in the switching signal SW output at the external terminal T 1 depending on the severity of the load (magnitude of the load current IL).

In FIG. 7 , the topmost switching signal SW 1 illustrates behavior under light load, and the middle switching signal SW 2 and bottommost switching signal SW 3 illustrate behavior under heavy loads. The switching signal SW 2 and switching signal SW 3 are differentiated by whether or not variable control of the ON period T ON reflecting the load current IL as expressed by the above numerical formula 6 is being performed.

The switching signal SW 2 illustrates behavior when variable control of the ON period T ON reflecting the load current IL is not being performed, and the switching signal SW 3 illustrates behavior when variable control of the ON period T ON reflecting the load current IL is being performed (i.e., the first embodiment is adopted).

When variable control of the ON period T ON reflecting the load current IL is not performed, variation in the switching period occurs (T 1 ≠T 2 ) due to the severity of the load (magnitude of the load current IL), as can be seen by comparing switching signal SW 1 and switching signal SW 2 .

When variable control of the ON period T ON reflecting the load current IL is performed, the ON period T ON is shorter the lighter the load (the lower the load current IL) is, and the ON period T ON increases (T ON1 < ON3 ) the heavier the load (the higher the load current IL) is, as can be seen by comparing switching signal SW 1 and switching signal SW 3 , enabling the switching period (and, by extension, the switching frequency) to be kept constant regardless of load severity (magnitude of load current IL).

In this way, the activity of an ON time setter that sets the ON time T ON according to the magnitude of the load current IL flowing through the load (in the example of FIG. 1 , a circuit block constituted by the detection transistor QD, detection resistor RD, level shifter LS, and adder CB) minimizes frequency variation in the switching signal SW, enabling prevention of frequency variation in the pseudo-ripple generated based on the switching signal SW. As a result, it is possible to improve load regulation properties (stability of the output voltage OUT against load variations). This is also advantageous in protecting against the effects of EMI.

While FIG. 1 illustrates a synchronous rectifier buck DC/DC converter, the present invention can also be applied to a so-called diode rectifier-type buck DC/DC converter, where a diode is substituted for the low-side transistor (synchronous rectifier transistor) QL.

Second Embodiment

FIG. 2 illustrates a second embodiment of the present invention. This embodiment shares improvement in noise resistance properties in common with the first embodiment.

An integrated circuit IC 2 represents the primary circuit of a DC/DC converter 20 . The integrated circuit IC 2 can utilize the many circuit components included in the integrated circuit IC 5 shown in FIG. 5 ; description of the operation of these shall be omitted. Here, the points of difference between FIG. 2 and FIG. 5 will be described. A first point of difference is that the integrated circuit IC 2 does not include an external terminal T 2 . It is convenient to leave out the external terminal T 2 when constructing the integrated circuit IC 2 . This is because miniaturization of the package containing the integrated circuit IC 2 is thus made possible. When a different circuit component is used in place of the eliminated external terminal T 2 , the circuit functions built into the integrated circuit IC 2 can be increased.

A second point of difference between the second embodiment shown in FIG. 2 and the example shown in FIG. 5 is that feedback resistors R 11 a and R 12 a for returning the output voltage VOUT are included in the integrated circuit IC 2 . The feedback resistors R 11 a and R 12 a correspond to the feedback resistors R 11 and R 12 of the DC/DC converter 50 shown in FIG. 5 .

A third point of difference between the second embodiment and the example of FIG. 5 is that the non-inverting input terminal (+) of the comparator CMP 2 leads out of the integrated circuit IC 2 as an external terminal. The third point of difference is related to the second point of difference. The inclusion of the feedback resistors R 11 a and R 12 a in the integrated circuit IC 2 makes regulation of the output voltage VOUT from outside the integrated circuit IC 2 impossible. In order to eliminate this defect, a configuration is adopted wherein the non-inverting input terminal (+) of the comparator CMP 2 is directly led to the external terminal of the integrated circuit IC 2 , and soft start voltage VREF 2 is supplied to the non-inverting input terminal (+) of the comparator CMP 2 .

A fourth point of difference between the second embodiment and the example of FIG. 5 , related to the third point of difference, is that a resistor Rref is connected between the non-inverting input terminal (+) of the comparator CMP 2 , i.e., the external terminal T 3 , and the ground potential GND. Combining the resistor Rref with a capacitor C 4 connected in a row therewith enables the circuit operating point of the comparator CMP 2 to be regulated. Thus, regulation equivalent to that performed on the feedback resistors R 11 a and R 12 a is performed on the non-inverting input terminal (+) of the comparator CMP 2 .

Briefly put, the second embodiment of the present invention illustrated in FIG. 2 is characterized in that it is a DC/DC converter 20 having an input voltage VIN; an output terminal T 1 that converts the input voltage VIN and outputs an output voltage VOUT; a switching element QH having a first primary electrode D, a second primary electrode S, and a control electrode G connected between the input voltage VIN and the output terminal T 1 that repeatedly switches between ON and OFF states; an inductor L 1 connected to one of either a first primary electrode D or a second primary electrode S of the switching element QH; an output capacitor C 1 that smoothes the energy accumulated in the inductor L 1 ; a feedback voltage generating circuit constituted by a first feedback resistor R 11 a and a second feedback resistor R 12 a for returning an output voltage VOUT to the switching element QH; and an integrated circuit IC 2 for driving the switching element; and the first feedback resistor R 11 a and the second feedback resistor R 12 a are included in the integrated circuit IC 2 .

The comparator CMP 2 compares the soft start voltage VREF 2 input to the non-inverting input terminal (+) and a feedback voltage VFB 2 ; and a one-shot circuit OS 1 outputs a one-shot pulse PS 1 transitioning from a low level to a high level when the soft start voltage VREF 2 is greater than the feedback voltage VFB 2 , and a one-shot pulse transitioning from a high level to a low level when, conversely, the feedback voltage VFB 2 is greater than the soft start voltage VREF 2 . In the DC/DC converter 20 of FIG. 2 , this regulation and control of circuit operation is performed not by regulating the feedback voltage VFB 2 connected to the non-inverting input terminal (+) of the comparator CMP 2 , but rather by regulating the magnitude of the resistor Rref and capacitor C 4 connected to the external terminal T 3 .

<Application to a Television>

FIG. 8 is a block diagram illustrating an example of one configuration of a television installed with a DC/DC converter. FIGS. 9A through 9C are front, side, and rear views of a television installed with a DC/DC converter, respectively. A television X having this example configuration has a tuner X 1 , a decoder X 2 , a display X 3 , a speaker X 4 , a operating part X 5 , an interface X 6 , a controller X 7 , and a power source X 8 .

The tuner X 1 selects a desired channel broadcast signal from signals received by an antenna X 0 externally connected to the television X.

The decoder X 2 forms an image signal and an audio signal based on the broadcast signal selected with the tuner X 1 . The decoder X 2 also has the function of generating an image signal and an audio signal based on an external input signal from the interface X 6 .

The display X 3 outputs the image signal generated by the decoder X 2 as an image. An LCD panel or the like may be favorably used as the display X 3 .

The speaker X 4 outputs the audio signal generated by the decoder as sound.

The operating part X 5 is a human interface that accepts user input. A button, switch, remote controller, or the like may be used for the operating part X 5 .

The interface X 6 is a front end for receiving an external input signal from an external device (optic disc play, HDD, or the like).

The controller X 7 performs overall control of the operation of the above parts X 1 through X 6 . A CPU (central processing unit) or the like can be used for the controller X 7 .

The power source X 8 supplies power to the above parts X 1 through X 7 . The previously described DC/DC converter 10 or 20 may be favorably used as the power source X 8 .

In a first embodiment of the DC/DC converter according to the present invention, noise resistance properties can be improved by using a comparatively simple circuit configuration. In a second embodiment, an external terminal can be eliminated, and a feedback terminal of the output voltage, which is sensitive to the effects of noise, can be eliminated from the external terminal of the integrated circuit, improving noise resistance properties. Thus, the DC/DC converter according to the present invention demonstrates high industrial applicability potential.

A best mode for embodying the present invention has been described above, but it will be obvious to one skilled in the art that the teachings disclosed herein can be subjected to various modifications, and that various embodiments having configurations different from the specific examples given above are possible. Thus, the following claims are intended to encompass all possible modifications of the present invention to the extent that they remain within the spirit and technical scope of the present invention.

10 , 20 DC/DC CONVERTER

C 1 OUTPUT CAPACITOR

C 2 , C 3 , C 4 CAPACITOR

CC 1 CONSTANT CURRENT SOURCE

CM 1 CURRENT MIRROR CIRCUIT

CMP 1 , CMP 2 COMPARATOR

IC 1 , IC 2 INTEGRATED CIRCUIT

L 1 INDUCTOR

OS 1 ONE-SHOT CIRCUIT

Q 1 , Q 2 TRANSISTOR

T 1 , T 2 , T 3 , T 4 EXTERNAL TERMINAL

X 0 ANTENNA

X 1 TUNER

X 2 DECODER

X 3 DISPLAY

X 4 SPEAKER

X 5 OPERATING PART

X 6 INTERFACE

X 7 CONTROLLER