Motherboard with voltage-state display system

The present disclosure relates to motherboards, and particularly, to a motherboard having a voltage-state display system.

When a voltage mode of a central processing unit (CPU) needs to be determined, an oscillograph may be connected to each phase output terminal of a power controller of the CPU. However, it is inconvenient to connect the oscillograph to each phase output terminal of the power controller of the CPU every time the information is required.

Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, all the views are schematic, and like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a circuit diagram of a first exemplary embodiment of a motherboard.

FIG. 2 is a circuit diagram of a second exemplary embodiment of a motherboard.

The disclosure, including the accompanying drawings in which like references indicate similar elements, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to FIG. 1 , a first embodiment of a motherboard 300 includes a central processing unit (CPU) 30 , a drive 20 , and a voltage-state display system 100 .

The voltage-state display system 100 displays a voltage mode of the CPU 30 . The voltage-state display system 100 includes a power management chip 10 , a first transistor Q 1 , a second transistor Q 2 , a first light emitting diode (LED) D 1 , a second LED D 2 , a first resistor R 1 , and a second resistor R 2 . In the embodiment, the power management chip 10 is a two-phase power management chip.

The power management chip 10 includes a first phase output terminal 11 and a second phase output terminal 12 . The first phase output terminal 11 outputs a first pulse width modulation (PWM) signal. The first phase output terminal 11 is connected to a control terminal of the first transistor Q 1 . The second phase output terminal 12 outputs a second PWM signal. The second phase output terminal 12 is connected to a control terminal of the second transistor Q 2 . A first terminal of the first transistor Q 1 is connected to a cathode of the first LED D 1 . A second terminal of the first transistor Q 1 is grounded. An anode of the first LED D 1 is connected to a power terminal 40 of the motherboard 300 through the first resistor R 1 . A first terminal of the second transistor Q 2 is connected to a cathode of the second LED D 2 . A second terminal of the second transistor Q 2 is grounded. An anode of the second LED D 2 is connected to the power terminal 40 of the motherboard 300 through the second resistor R 2 .

The first and second phase output terminals 11 and 12 of the power management chip 10 are also connected to the drive 20 to respectively output the first and second PWM signals to the drive 20 . The drive 20 is connected to the CPU 30 to output corresponding voltages to the CPU 30 according to the received first and second PWM signals. The CPU 30 is connected to the power management chip 10 to output a control instruction to the power management chip 10 to denote the voltage mode needed by the CPU 30 , thereby controlling the power management chip 10 to adjust the first and second PWM signals.

According to INTEL standard, a power management chip has three work states, which are PS 0 state, PS 1 state, and PS 2 state. If the power management chip only includes first and second phase power output terminals, in the PS 0 state, the first and second phase output terminals both continuously output the PWM signal; in the PS 1 state, only the first phase output terminal continuously outputs the PWM signal; in the PS 2 state, only the first phase output terminal discontinuously outputs the PWM signal. If the power management chip includes at least three phase output terminals, in the PS 0 state, the at least three phase output terminals continuously output the PWM signals; in the PS 1 state, only first and second phase output terminals of the at least three phase output terminals continuously output the PWM signals; in the PS 2 state, only the first phase output terminal of the at least three phase output terminals discontinuously outputs the PWM signal.

When the power management chip is in the PS 0 state, the voltage mode of the CPU 30 is the PS 0 mode. When the power management chip is in the PS 1 state, the voltage mode of the CPU 30 is the PS 1 mode. When the power management chip is in the PS 2 state, the voltage mode of the CPU 30 is the PS 2 mode.

In the first embodiment, the power management chip 10 only includes the first phase output terminal 11 and the second phase output terminal 12 . Therefore, when the power management chip 10 is in the PS 0 state, the first phase output terminal 11 continuously outputs the first PWM signal to the control terminal of the first transistor Q 1 , and the second phase output terminal 12 continuously outputs the second PWM signal to the control terminal of the second transistor Q 2 . When the control terminals of the first and second transistor Q 1 and Q 2 receive the high level signal, the first and second transistors Q 1 and Q 2 are turned on, at that time, the first and second LEDs D 1 and D 2 emit light. When the control terminals of the first and second transistors Q 1 and Q 2 receive a low level signal, the first and second transistors Q 1 and Q 2 are turned off, at that time, neither of the first and second LEDs D 1 and D 2 emit light. Owing to frequencies of the first and second PWM signals being too high, when the power management chip 10 is in the PS 0 state, users can observe that the first and second LEDs D 1 and D 2 emits light.

When the power management chip 10 is in the PS 1 state, the first phase output terminal 11 of the power management chip 10 continuously outputs the first PWM signal to the control terminal of the transistor Q 1 . The second phase output terminal 12 of the power management chip 10 does not output the second PWM signal. Therefore, the first LED D 1 lights and the second LED D 2 is not lit.

When the power management chip 10 is in the PS 2 state, the first phase output terminal 11 of the power management chip 10 discontinuously outputs the first PWM signal to the control terminal of the first transistor Q 1 . The second phase output terminal 12 of the power management chip 10 does not output the second PWM signal. Owing to the first PWM signal outputting discontinuously to the control terminal of the first transistor Q 1 , when the power management chip 10 is in the PS 2 state, the first LED D 1 flickers, and the second LED D 2 does not light.

The voltage mode of the CPU 30 can be observed through the first and second LEDs D 1 and D 2 . When the first and second LEDs D 1 and D 2 are both lit, it denotes that the power management chip 10 is in the PS 0 state. Therefore, the voltage mode of the CPU 30 is the PS 0 mode. When the first LED D 1 lights, while the second LED D 2 is not lit, it denotes that the power management chip 10 is in the PS 1 state. Therefore, the voltage mode of the CPU 30 is the PS 1 mode. When the first LED D 1 flickers, and the second LED D 2 is not lit, it denotes that the power management chip 10 is in the PS 2 state. Therefore, the voltage mode of the CPU 30 is the PS 2 mode.

Referring to the FIG. 2 , a second embodiment of a motherboard 400 is similar to the first embodiment. In the second embodiment, the power management chip 220 is a four-phase power management chip. That is, the power management chip 220 includes a first phase output terminal 11 , a second phase power output terminal 12 , a third phase output terminal 223 , and a fourth phase output terminal 224 . The voltage-state display system 200 includes the power management chip 220 , a first transistor Q 1 , a second transistor Q 2 , a first LED D 1 , a second LED D 2 , a first resistor R 1 , a resistor R 2 , a third transistor Q 3 , a third LED D 3 , and a third resistor R 3 . The first to fourth phase output terminals 11 , 12 , 223 , and 224 are all connected to the drive 20 .

The power management chip 220 has three states, namely the PS 0 , PS 1 , and PS 2 states, and according to the above-mentioned INTEL standard, the state of a third PWM signal output by the third phase output terminal 223 is the same as the state of a fourth PWM signal output by the fourth phase output terminal 224 . That is, if the third phase output terminal 223 is continuously outputting the third PWM signal, so is the fourth phase output terminal 224 . Therefore, either one of the third and fourth phase output terminals 223 and 224 may be connected to the third LED D 3 to denote the voltage mode of the CPU 30 . In the second embodiment, the third LED D 3 is connected to the fourth phase output terminal 224 of the power management chip 220 . In detail, the fourth phase output terminal 224 of the power management chip 220 is connected to a control terminal of the third transistor Q 3 . A first terminal of the third transistor Q 3 is connected to a cathode of the third LED D 3 . A second terminal of the third transistor Q 3 is grounded. An anode of the second LED D 3 is connected to the power terminal 40 through the third resistor R 3 .

In the second embodiment, when all of the three LEDs D 1 -D 3 are lit, it denotes that the power management chip 10 is in the PS 0 state, and the voltage mode of the CPU 30 is the PS 0 mode. When the first LED D 1 or the first and second LEDs D 1 and D 2 together are lit, while the third LED D 3 is not lit, it denotes that the power management chip 10 is in the PS 1 state, and the voltage mode of the CPU 30 is the PS 1 mode. When the first LED D 1 flickers, and neither of the second and third LED D 2 and D 3 are lit, it denotes that the power management chip 10 is in the PS 2 state, and the voltage mode of the CPU 30 is the PS 2 mode.

In the embodiments, the first to third transistors Q 1 -Q 3 are n-channel field effect transistors (FETs). The control terminal, the first terminal, and the second terminal of each of the first to third transistors Q 1 -Q 3 are a gate, a drain, and a source of the FET.

Although numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.