Monolithic high-side switch control circuits

This application claims the benefit of U.S. Provisional Application No. 61/528,830, filed on Aug. 30, 2011, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention provides a control circuit, and more particularly to a control circuit for high-side switches.

2. Description of the Related Art

The present invention provides a control circuit for controlling high-side switches. The circuit is developed in a monolithic integrated circuit. It can be applied to circuits of battery management, circuits of battery cell balance, light-emitting diode (LED) backlight drivers and power converters.

An embodiment of a high-side switch control circuit comprises an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a current source. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp a maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The current source is coupled to the level-shifting transistor. The current source limits a maximum current of the level-shifting transistor.

Another exemplary embodiment of a high-side switch control circuit comprises an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a resistor. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp a maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The resistor is coupled to a source terminal of the level-shifting transistor. A gate voltage of the level-shifting transistor is regulable, and the resistor limits a maximum current of the level-shifting transistor.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows one embodiment of a control circuit according to the present invention;

FIG. 2 shows another embodiment of a control circuit according to the present invention; and

FIG. 3 shows an embodiment for a monolithic integrated circuit according to the present invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows one embodiment of a control circuit according to the present invention. The control circuit is used to control high-side switches. Referring to FIG. 1 , the control circuit includes a first circuit 10 which is developed in a P silicon substrate silicon of an integrated circuit. The control circuit further includes a second circuit 20 which is developed in an isolated well that is formed in the P silicon substrate.

Referring to FIG. 1 , the first circuit 10 includes level-shifting transistors 30 and 35 , current sources 70 and 75 , a low-impedance resistor 78 , and a low-impedance transistor 79 . The second circuit 20 includes on/off transistors 40 and 50 operated as switches, bias resistors 45 and 55 , and zener diodes 46 and 56 . The gate terminal of the on/off transistor 40 is coupled to a node N 20 , the source thereof is coupled to a terminal X N , and the drain terminal thereof is coupled to a terminal Y N . The on/off transistor 40 is coupled to turn on/off the terminals X N and Y N . The gate terminal of the on/off transistor 50 is coupled to a node N 21 , the source terminal thereof is coupled to a terminal X M , and the drain terminal thereof is coupled to a terminal Y M . The transistor 50 is coupled to turn on/off the terminals X M and Y M . The on/off transistor 40 is controlled by the level-shifting transistor 30 which is developed in the first circuit 10 , and in detailed, the on/off transistor 40 is turned on by the level-shifting transistor 30 . The on/off transistor 50 is controlled by the level-shifting transistor 35 which is developed in the first circuit 10 , and in detailed, the on/off transistor 50 is turned on by the level-shifting transistor 35 . The level-shifting transistors 30 and 35 are controlled by control signals S N and S M respectively. The bias resistor 45 is coupled between the terminal X N and the node N 20 and coupled to turn off the on/off transistor 40 . A zener diode 46 is coupled between the terminal X N and the node N 20 and utilized to clamp the maximum voltage applied to the on/off transistor 40 . The bias resistor 55 is coupled between the terminal X M and the node N 21 and coupled to turn off the on/off transistor 50 . The zener diode 56 is coupled between the terminal X M and the node N 21 and utilized to clamp the maximum voltage applied to the on/off transistor 50 . The current source 70 is coupled with the level-shifting transistor 30 in series to limit the maximum current of the level-shifting transistor 30 . In detailed, the gate of the level-shifting transistor 30 receives the control signal S N , the drain terminal thereof is coupled to the node N 20 , and the source terminal thereof is coupled to the current source 70 . The current source 75 is coupled with the level-shifting transistor 35 in series to limit the maximum current of the level-shifting transistor 35 . In detailed, the gate terminal of the level-shifting transistor 35 receives the control signal S M , the drain terminal thereof is coupled to the node N 21 , and the source terminal thereof is coupled to the current source 75 . Therefore, due to the limitation of the maximum currents of the level-shifting transistors 30 and 35 , the maximum power consumption of the level-shifting transistors 30 and 35 is regulated. The low-impedance resister 78 is coupled with the low-impedance transistor 79 in series between the source terminal of the level-shifting transistor 35 and a reference low voltage. The low-impedance resistor 78 will be coupled with the current source 75 in parallel once the low-impedance transistor 79 is turned on, which will provide a lower impedance path for turning on the on/off transistor 50 when the voltage of the terminal X M is low.

FIG. 2 shows another embodiment of a control circuit according to the present invention. In the embodiments of FIGS. 1 and 2 , the same elements are represented by the same reference labels and perform the same operation so the description is omitted here. The difference between the control circuits of the FIGS. 1 and 2 is that the control circuit of FIG. 2 includes resistors 90 and 95 which are applied to replace the current sources 70 and 75 shown in FIG. 1 to limit the maximum currents of the level-shifting transistors 30 and 35 , respectively. Moreover, the level-shifting transistors 30 and 35 are controlled by control voltages V N and V M replacing the control signals S N and S M shown in FIG. 1 , respectively. The control voltages V N and V M are regulated. In other words, the gate voltages of the level-shifting transistors 30 and 35 are regulated. Thus, the current of the level-shifting transistor 30 will be regulated.

I 30 =( V N −V GS )/ R 90

where the I 30 is the current of the level-shifting transistor 30 , V GS is the threshold voltage of the level-shifting transistor 30 , and the R 90 is the resistance of the resistor 90 .

According to the present invention, the control circuits of FIGS. 1 and 2 can be applied to circuits of battery management, circuits of battery cell balance, LED backlight driver, and power converters. Therefore, due to the limitation of the maximum currents of the level-shifting transistors 30 and 35 , the maximum power consumption of the level-shifting transistors 30 and 35 is regulated.

FIG. 3 shows an embodiment for a monolithic integrated circuit according to the present invention. Referring to FIG. 3 , the first circuit 10 shown in FIGS. 1 and 2 is developed in a P silicon substrate (P_Si). The elements of the second circuit 20 shown in FIGS. 1 and 2 are developed in an isolated N well (N). The second circuit 20 is isolated from the first circuit 10 .

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.