Chip package and method for forming the same

This Application claims the benefit of U.S. Provisional Application No. 61/436,762, filed on Jan. 27, 2011, the entirety of which is incorporated by reference herein.

1. Field of the Invention

The invention relates to a chip package, and in particular relates to a chip package having a shielding structure to prevent electromagnetic interference (EMI) and a fabrication method thereof.

2. Description of the Related Art

As sizes of chip packages continue to become thinner and lighter and signal transmission speed continues to increase, electromagnetic interference (EMI) and electrostatic discharge (ESD) problems for chip packages have worsened. Because sizes of chip packages continue to get smaller, design of ground wiring in chip packages have become more important.

An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side edges of the signal conducting layer and partially covers the ground conducting layer such that a side edge of the ground conducting layer is exposed at a side of the substrate.

An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate, wherein a device region, a signal pad, and a ground pad are respectively disposed in or on the substrate, and the signal pad is electrically connected to the device region; forming a signal conducting layer and a ground conducting layer on a surface of the substrate, wherein the signal conducting layer is electrically connected to the signal pad; forming a protection layer on the surface of the substrate, wherein the protection layer has at least an opening exposing a portion of the signal conducting layer and completely covers the entire side edges of the signal conducting layer, wherein a side edge of the ground conducting layer is exposed; forming a signal bump on the opening of the protection layer, wherein the signal bump is electrically connected to the signal pad through the signal conducting layer; and dicing the substrate to form at least one chip package, wherein the side edge of the ground conducting layer is exposed at a side of the substrate after the substrate is diced.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1A-1E are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention; and

FIGS. 2A-2D are top views showing chip packages according to embodiments of the present invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

The manufacturing method and method for use of the embodiment of the invention are illustrated in detail as follows. It is understood, that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer, include embodiments where the first and second layers are in direct contact and those where one or more layers are interposing the first and second layers.

A chip package according to an embodiment of the present invention may be used to package an image sensor chip. However, embodiments of the invention are not limited thereto. For example, the chip package of the embodiments of the invention may be applied to active or passive devices, or electronic components with digital or analog circuits, such as opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting heat, light, or pressure. Particularly, a wafer scale package (WSP) process may be applied to package semiconductor chips, such as image sensor devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, ink printer heads, or power IC modules.

The wafer scale package process mentioned above mainly means that after the package process is accomplished during the wafer stage, the wafer with chips is cut to obtain separate independent packages. However, in a specific embodiment, separate independent chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer scale package process. In addition, the above mentioned wafer scale package process may also be adapted to form chip packages of multi-layer integrated circuit devices by stacking a plurality of wafers having integrated circuits. In one embodiment, after the dicing process is performed, the obtained chip package is a chip scale package (CSP). The size of the chip scale package (CSP) may be only slightly larger than the size of the packaged chip. For example, the size of the chip scale package is not larger than 120% of the size of the packaged chip.

Before embodiments of the invention are illustrated, a chip package known by the inventor of the application is first illustrated. In the chip package, ground conducting structures are merely disposed on four corners of the substrate of the chip package. Thus, all of the ground conducting wires need to be led to at least one of the corners to lead out the electrostatic discharge current generated during the fabrication or use of the chip package. Thus, many conducting wires need to be formed on the substrate of the chip package. However, as wiring density of the chip in the chip package increases and size of the chip decreases, design of the ground conducting wires become more difficult. In order to resolve the problem discovered by the inventor, the inventor provides a solution as a method as described in following description.

FIGS. 1A-1E are cross-sectional views showing the steps of forming a chip package according to an embodiment of the present invention. As shown in FIG. 1A , a substrate 100 is provided, which has a surface 100 a and a surface 100 b . The substrate 100 is, for example, a semiconductor substrate such as (but is not limited to) a silicon substrate. The substrate 100 may also be an insulating substrate such as (but is not limited to) a ceramic substrate. In one embodiment, the substrate 100 may be, for example, a semiconductor wafer (such as a silicon wafer) such that a wafer-level packaging process may be performed to reduce fabrication time and cost.

In one embodiment, a device region 102 , a signal pad 104 S, and a ground pad 104 E may be disposed in or on the substrate 100 . For example, in the embodiment shown in FIG. 1A , the device region 102 , the signal pad 104 S, and the ground pad 104 E are disposed in the substrate 100 and exposed at the surface 100 a of the substrate 100 . The device region 102 may be formed with (but is not limited to) an optoelectronic device which may include an image sensor device or a light emitting device. The image sensor device is, for example, a CMOS image sensor (CIS) device or a charge-coupled device (CCD), and the light emitting device is, for example, a light emitting diode device. The signal pad 104 S is electrically connected to the device region 102 , which is used to transmit electrical signals into and/or from the device region 102 . The ground pad 104 E is used to lead out electrostatic discharge current. In one embodiment, the substrate 100 is a silicon wafer, wherein a plurality of device regions 102 , signal pads 104 S, and ground pads 104 E are formed therein or thereon.

Although only a signal layered conducting pad ( 104 S, 104 E) is shown in FIG. 1A , a plurality of conducting pads may be stacked with each other and/or arranged on the substrate 100 . For example, in one embodiment, the conducting pad ( 104 S, 104 E) is a stacked structure of a plurality of pads, at least a conducting pad, or a conducting pad structure including at least a conducting pad and at least an interconnection structure. In the following embodiments, for convenience, only a signal layered conducting pad ( 104 S, 104 E) is shown for simplicity.

As shown in FIG. 1A , a carrier substrate 106 may be optionally disposed on the substrate 100 . For example, a spacer layer 105 is first formed on the surface 100 a of the substrate, followed by disposing of the carrier substrate 106 on the spacer layer 105 . The carrier substrate 106 may be, for example, a transparent substrate such as a glass substrate, quartz substrate, or the like. In one embodiment, the carrier substrate 106 may be used as a support, and a thinning process may be performed on the surface 100 b of the substrate 100 to thin down the substrate 100 to a predetermined thickness for facilitating subsequent processes.

Then, a signal conducting layer electrically connected to the signal pad 104 S and a ground conducting layer electrically connected to the ground pad 104 E are formed on the substrate 100 . As shown in FIG. 1B , in one embodiment, a portion of the substrate 100 may be optionally removed from the surface 100 b of the substrate 100 to form a hole 108 S which extends towards the signal pad 104 S and exposes the signal pad 104 S. In one embodiment, a portion of the substrate 100 may also be optionally removed from the surface 100 b of the substrate 100 to form a hole 108 E extending towards the ground pad 104 E and exposing the ground pad 104 E. In the embodiment where the substrate 100 is a conductive substrate (such as a silicon wafer), an insulating layer needs to be formed on the substrate 100 . As shown in FIG. 1B , the insulating layer 110 extends from the surface 100 b of the substrate 100 into the hole 108 S and the hole 108 E. In one embodiment, an etching process may be performed to remove the insulating layer 110 on the bottoms of the hole 108 S and the hole 108 E such that the signal pad 104 S and the ground pad 104 E are exposed, respectively.

Next, a signal conducting layer 112 S electrically connected to the signal pad 104 S and a ground conducting layer 112 E electrically connected to the ground pad 104 E are formed on the surface 100 b of the substrate 100 , as shown in FIG. 1C . In one embodiment, a conducting material layer may be formed on the surface 100 b of the substrate 100 , which may extend into the hole 108 S and the hole 108 E to electrically connect to the signal pad 104 S and the ground pad 104 E, respectively. Then, the conducting material layer may be patterned to simultaneously form the signal conducting layer 112 S and the ground conducting layer 112 E. In one embodiment, in the step of patterning the conducting material layer, a dummy conducting layer 112 D may be optionally formed. In subsequent processes, a dumpy bump may be formed on the dummy conducting layer.

In one embodiment, a seed layer may be formed on the surface 100 b of the substrate 100 , and a mask layer is formed on the seed layer. Then, an electroplating process is performed on the seed layer to deposit a conducting material on the exposed seed layer. Then, the mask layer is exposed, and the seed layer previously covered by the mask layer is etched and removed such that the conducting material layer composed of the seed layer and the electroplated conducting material is patterned, thus forming the desired patterned conducting layer which includes, for example, the signal conducting layer 112 S, the ground conducting layer 112 E, and/or the dummy conducting layer 112 D.

As shown in FIG. 1C , the signal conducting layer 112 S has two side edges 113 S, and the ground conducting layer 112 E also has two side edges 113 E. One of the side edges 113 E of the ground conducting layer 112 E is located near a predetermined scribe line of the substrate 100 . After a subsequent dicing process is performed, the side edge 113 E of the ground conducting layer 112 E may be exposed at a side of the substrate 100 after being diced.

As shown in FIG. 1D , a protection layer 114 is formed on the surface 100 b of the substrate 100 . The protection layer 114 has at least an opening exposing a portion of the signal conducting layer 1125 . The protection layer 114 may also have another opening which may expose, for example, a portion of the dummy conducting layer 112 D and a portion of the ground conducting layer 112 E. In one embodiment, the protection layer 114 covers the entire side edges 113 E of the signal conducting layer 112 E. The protection layer 114 only partially covers the side edges of the ground conducting layer 112 E without covering the ground conducting layer 112 E nearby the predetermined scribe line and without covering the side edge 113 E of the ground conducting layer 112 E near the predetermined scribe line.

Next, as shown in FIG. 1D , a signal bump 116 S, a ground bump 116 E, and a dummy bump 116 D may be respectively formed on the signal conducting layer 112 S, the ground conducting layer 112 E, and the dummy conducting layer 112 D exposed by openings of the protection layer 114 . The dummy bump 116 D may be used to balance stress suffered by each of the bumps on the substrate 100 . In one embodiment, the ground bump 116 E may also be used to balance stress suffered by each of the bumps on the substrate 100 . In one embodiment, the dummy bump 116 D and/or the dummy conducting layer 112 D may not be formed. In one embodiment, the ground bump 116 E may not be formed.

Next, the substrate 100 may be diced along predetermined scribe lines on the substrate to form at least one chip package, wherein the side edge 113 E of the ground conducting layer 112 E is exposed at a side of the substrate 100 after being diced. For example, in the embodiment shown in FIG. 1D , the exposed side edge 113 E of the ground conducting layer 112 E is substantially coplanar with the side of the substrate 100 . The ground conducting layer 112 E which is not covered by the protection layer 114 and exposed near the side of the substrate 100 may be used to electrically contact with another conducting structure such that electrostatic discharge current generated during the fabrication or the use of the chip package is led out, ensuring normal operation of the device region 102 . In one embodiment, the dummy conducting layer 112 D and the dummy bump 116 D may also help to lead a portion of the electrostatic discharge current out.

For example, as shown in FIG. 1E , a shell 118 may be used to cover the formed chip package. In one embodiment, the shell 118 may include a conducting portion 118 a which is used to electrically contact with the exposed ground conducting layer 112 E. Thus, electrostatic discharge current generated during the fabrication or the use of the chip package may be led out by the shell 118 including the conducting portion 118 a.

FIGS. 2A-2D are top views showing chip packages according to embodiments of the present invention, wherein same or similar reference numbers are used to designate same or similar elements, and the protection layer 114 is not shown for simplicity. As shown in FIG. 2A , in this embodiment, the ground conducting layer 112 E is exposed at a side of the substrate 100 , which may conveniently contact with another conducting structure. Thus, electrostatic discharge current generated during the fabrication or the use of the chip package may be led out through the ground pad and the ground conducting layer 112 E in the hole 108 E.

In the embodiment shown in FIG. 2B , a side edge of the dummy conducting layer 112 D may also be exposed at a side of the substrate 100 (i.e., not covered by the protection layer 114 ), thus also helping to lead out electrostatic discharge current generated during the fabrication or the use of the chip package. In the embodiment shown in FIG. 2B , although both the side edges of the dummy conducting layer 112 D and the ground conducting layer 112 E are exposed at a same side of the substrate 100 , embodiments of the invention are not limited thereto. In another embodiment, the side edges of the dummy conducting layer 112 D and the ground conducting layer 112 E may be exposed at different sides of the substrate 100 , respectively.

In the embodiment shown in FIG. 2C , at least a second ground conducting layer 112 E 2 and/or a second ground bump 116 E 2 disposed thereon may be further included. The second ground conducting layer 112 E 2 may also electrically contact with a second ground pad (not shown) through a hole 108 E 2 , and a side edge of the second ground conducting layer 112 E 2 may also be exposed at a side of the substrate 100 . In one embodiment, the second ground conducting layer 112 E 2 may be electrically connected to the ground conducting layer 112 E through a conducting region 20 .

In the embodiment shown in FIG. 2D , a dummy conducting layer 112 D may also be electrically connected to the ground conducting layer 112 E through a conducting region 20 .

The ground conducting structure of the chip package according to the embodiment of the invention is not limited to be located at corners of the substrate and can lead the electrical path to the side of the substrate to electrically connect to another conducting structure. Not only is the chip package protected, but wire density of the chip package is also reduced, improving performance and yield of the chip package.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.