Switch circuit and semiconductor circuit

The present application claims priority from Japanese patent application JP 2011-073891 filed on Mar. 30, 2011, the content of which is hereby incorporated by reference into this application.

The present invention relates to technology for a switch circuit which can be integrated on a semiconductor substrate.

Among the transmission/reception switch circuits for application to ultrasonographs, there have been switch circuits each of which, having two MOS transistors, a main switch connected to a common source of the two MOS transistors, a drive circuit connected to a common gate of the two MOS transistors and a holding circuit, holds an on-state or off-state of the switch (see Japanese Unexamined Patent Application Publication No. 2004-363997, for example).

To achieve image accuracy improvement and device multifunctionality in development of medical ultrasonographs, it becomes necessary to enhance resolution by increasing the number of channels. Such an approach leads to enlarging the scale of circuits for use in ultrasonographs and results in increasing power consumption by ultrasonographs. Hence, they have been continuously promoting circuit integration in analog front end sections of ultrasonographs and power consumption reduction.

Generally, signals transmitted from a transmitter of an ultrasonograph are high-voltage signals, and they overload receivers receiving and amplifying reflected signals. As a countermeasure, a transmission/reception switch (T/R switch) is provided in a stage preceding the receiver of each ultrasonograph. When a signal is transmitted, the T/R switch is turned off so as to protect the receiver. When a signal is received, the T/R switch is turned on to allow a signal reflected from a living body to reach the receiver section. The signal reflected from a living body is a weak ultrasonic signal (of several to several tens of MHz), so that the T/R switch is required to have a low-noise characteristic and be capable of handling high-frequency signals without generating much switching noise.

An object of the present invention will be described with reference to FIG. 6 , which is a rearranged diagram showing a switch circuit disclosed in Japanese Unexamined Patent Application Publication No. 2004-363997, as an example for comparison. The circuit shown in FIG. 6 includes: a main switch having two NMOS transistors M 1 and M 2 connected to a common source; a holding circuit formed of a latch circuit having NMOS transistors M 3 and M 4 , zener diodes D 3 and D 4 and capacitors C 1 and C 2 connected to the common source; and NMOS transistors M 5 and M 6 and diodes D 1 and D 2 which control switching of the main switch and terminals Set and Reset through which control signals for switching control are inputted.

The main switch is turned on by turning M 5 on and M 6 off. At this time, C 1 in the latch circuit and capacitance Cgs between the gate and source of each of M 1 and M 2 in the main switch circuit are charged up to around Vdc to turn the main switch circuit on. After they are charged, even if M 5 is turned off, the charges held by C 1 and Cgs can maintain the on-state of the main switch circuit without requiring any steady current flow. The main switch is turned off by turning M 5 off and M 6 on. At this time, the gate voltage of M 3 rises to put M 3 in an on-state and the charges held by C 1 and Cgs are discharged via the common source thereby causing the main switch circuit to be turned off.

The on-state of the above main switch is, however, maintained only by the capacitance of charged Vgs section. Also, since the control signal from the holding circuit is sent directly to M 1 and M 2 in the main switch circuit, the state of the holding circuit can change, for example, when charges are discharged from M 1 and M 2 due to gate leakage or when the input signal voltage changes causing crosstalk via Cgd 1 , Cgd 2 and Cgs in the main switch circuit. This makes it difficult to maintain the on- or off-state of the main switch for an extended period of time and can cause erroneous on/off operation of the switch circuit.

Furthermore, when a negative high voltage (−HV) is applied from GND via an input/output terminal, the voltage of the common source S quickly follows the applied voltage thanks to the parasitic diode M 1 , but the voltage of the common gate G cannot instantaneously follow the applied voltage. This causes a high voltage to be instantaneously applied to C 1 and between the gate and source of each of M 1 and M 2 to possibly break the respective elements.

In view of the above, it is an object of the present invention to realize a T/R switch which can transmit a signal reflected from a living body to a receiver with low noise over a wide frequency band without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes.

A typical configuration of the present invention is as follows.

A switch circuit includes: a main switch having a first MOS transistor, to a drain terminal of which a first input/output terminal is connected, and a second MOS transistor, to a drain terminal of which a second input/output terminal is connected, wherein a source terminal of the first MOS transistor and a source terminal of the second MOS transistor are connected forming a common source terminal and wherein a gate terminal of the first MOS transistor and a gate terminal of the second MOS transistor are connected forming a common gate terminal; and a voltage control circuit which is connected to the common source terminal and the common gate terminal of the main switch, which makes potential of the common gate terminal follow, in phase, variation in common source potential (potential of the common source terminal), and which controls, using a gate control signal, turning on or off of the main switch.

The present invention makes it possible to realize a T/R switch which can transmit a signal reflected from a living body to a receiver over a wide frequency band and with low noise without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes.

FIG. 1 is a diagram showing the configuration of a switch circuit according to a first embodiment;

FIG. 2 is a diagram showing the configuration of a switch circuit according to a second embodiment;

FIG. 3 is a diagram showing the configuration of a switch circuit according to a third embodiment;

FIG. 4 is a diagram showing the configuration of a switch circuit according to a fourth embodiment;

FIG. 5 is a diagram showing the configuration of a semiconductor integrated circuit according to a fifth embodiment; and

FIG. 6 is a diagram showing, for comparison purposes, a switch circuit including two MOS transistors.

Embodiments of the present invention will be described below in detail based on drawings. Circuit elements included in each block of each embodiment are, for example, publicly known low-voltage and high-voltage CMOS transistors, resistors, capacitors, diodes, and current sources formed, using integrated circuit technology, on a single semiconductor substrate such as monocrystal silicon.

First Embodiment

FIG. 1 is a diagram showing a first embodiment of a switch circuit including a main switch and a floating voltage circuit.

The main switch includes two NMOS transistors HN 1 and HN 2 and two parasitic diodes D 1 and D 2 of the two NMOS transistors. The source terminals and gate terminals of the NMOS transistors HN 1 and HN 2 are connected to a common source terminal S H and a common gate terminal G H , respectively. The drain terminals of NMOS transistors HN 1 and HN 2 are connected to input/output terminals s 1 and s 2 , respectively. The two NMOS transistors HN 1 and HN 2 each have an on-resistance of several ohms causing the main switch to have an on-resistance of about 10 ohms.

The floating voltage circuit includes a first latch circuit Latch 1 , a second latch circuit Latch 2 , a floating voltage generator, and a noise cut circuit.

The first latch circuit Latch 1 shifts the level of a switch control input signal to the level of a main switch control signal SWIN 2 . The switch control input signal uses 0 V inputted from an input terminal SWIN 1 as a reference signal L and the potential of a reference power supply VDD as a reference signal H. The main switch control signal SWIN 2 uses the potential of the common source terminal S H as a reference. The second latch circuit Latch 2 generates, based on the input main switch control signal SWIN 2 , a gate control signal to be sent to the common gate terminal G H . The floating voltage generator includes a constant current source I 1 and a zener diode DZ 1 , generates, using the potential of the common source S H as a reference, a voltage required to perform on-control of the main switch, and supplies the generated voltage as a power supply for the second latch circuit Latch 2 from a node n 1 . The noise cut circuit includes a source follower circuit having a PMOS transistor HP 1 whose gate terminal is connected to the common source terminal S H and a diode D 3 whose anode is connected to the drain terminal of the PMOS transistor HP 1 and whose cathode is connected to a reference power supply VSS. The noise cut circuit separates a node n 2 connected to the common source terminal S H the potential of which is used as a reference potential for the second latch circuit Latch 2 and a node n 3 the potential of which is used as a reference potential for the first latch circuit Latch 1 and thereby causes the currents generated by the first latch circuit Latch 1 and the floating voltage generator to flow to the reference power supply VSS.

To turn on the main switch included in the switch circuit of the present embodiment, a signal L is inputted to the input terminal SWIN 1 . The input signal causes the first latch circuit. Latch 1 to function as a level shifter and, as a result, potential L′ higher than the potential of the common source terminal S H by the gate-source potential Vgsp of the PMOS transistor HP 1 is outputted to the switch circuit control signal SWIN 2 .

The floating voltage generator keeps, using the constant current source I 1 connected to the reference power supply VDD, a current flowing so as to keep the potential of the node n 1 equal to the sum of the potential of the common source terminal S H , the gate-source potential Vgsp of the PMOS transistor HP 1 , and the breakdown voltage VZ of the zener diode DZ 1 .

The second latch circuit Latch 2 receives, based on the potentials of the node n 1 and node n 2 , an on-control signal SWIN 2 and provides the common gate terminal G H with a potential equal to the sum of the potential of the common source terminal S H , the gate-source potential Vgsp of the PMOS transistor HP 1 , and the breakdown voltage VZ of the zener diode DZ 1 . As a result, a potential equal to the sum of Vgsp and VZ is applied between the gate and source of each of the NMOS transistors causing the main switch to turn on.

To turn off the main switch, a signal H is inputted to the input terminal SWIN 1 . The input signal causes the first latch circuit Latch 1 to function as a level shifter and, as a result, a potential H′ equal to the sum of the potential of the common source terminal S H , the gate-source potential Vgsp of the PMOS transistor HP 1 , and the breakdown voltage VZ of the zener diode DZ 1 is outputted to the switch circuit control signal SWIN 2 .

The second latch circuit Latch 2 receives the off-control signal SWIN 2 and outputs, based on the potentials of the node n 1 and node n 2 , a gate control signal so as to equalize the potentials of the common gate terminal G H and common source terminal S H . As a result, the potential difference between the gate and source of each of the NMOS transistors becomes 0 causing the main switch to turn off.

Switch circuit operation performed when the above-described switch circuit is applied to a transmission/reception (T/R) switch circuit of an ultrasonograph with a transmitter thereof connected to an input/output terminal s 1 and a receiver section thereof connected to an input/output terminal s 2 will be described below.

To turn on the main switch and allow a received signal ΔV 1 to pass through from the input/output terminal s 1 to the input/output terminal s 2 , the potentials of the common source terminal S H and the node n 2 are equalized with the potential of the received signal ΔV 1 . Since variation in the potential of the node n 2 is inputted to the gate terminal of the PMOS transistor HP 1 , the potential of the node n 3 becomes equal to the sum of the gate-source potential Vgsp of the PMOS transistor HP 1 and ΔV 1 . The floating voltage generator generates, based on the potential of the node n 3 , a potential equal to the sum of VZ, Vgsp, and ΔV 1 at the node n 1 .

The second latch circuit Latch 2 gives a gate control signal to the common gate terminal G H based on the potentials of the nodes n 1 and n 2 . Therefore, during on-operation, the common gate terminal G H can follow in phase the varying potential of the common source terminal S H , keeping the potential difference VZ+Vgsp constant. Hence, the gate-source potential variation ΔVgs of each of the NMOS transistors HN 1 and HN 2 in the main switch becomes 0 (ΔVgs=0), so that gate-drain capacitance Cgd and gate-source capacitance Cgs are neither charged nor discharged. This makes Cgd+Cgs virtually zero, so that substrate capacitance Csub 1 +Csub 2 is the only capacitance generated between ground and the NMOS transistors HN 1 and HN 2 . This enables transmission of a received signal over a wide frequency band without causing elements to break down.

Even though the on-resistance of HN 1 and HN 2 that can cause thermal noise can be reduced by enlarging the elements, doing so increases parasitic capacitance. Since, however, parasitic capacitance is greatly reduced in the above-described configuration with Cgd+Cgs being zero, the elements can be made larger to reduce the on-resistance while keeping the parasitic capacitance small. Thus, the switch circuit of the present embodiment is capable of low-noise transmission of a received signal.

Furthermore, in the configuration with Latch 2 provided between Latch 1 and the main switch, even when a voltage change via the input/output terminal s 1 causes crosstalk via Cgd and Cgs, Latch 1 maintaining an on- or off-state is not easily affected. Hence, the present embodiment is also effective in preventing malfunction of the main switch.

If current generated when Latch 1 or Latch 2 is turned on or off or current generated by the current source I 1 of the floating voltage generator is allowed to flow to the input/output terminals s 1 and s 2 via the common source terminal S H of the main switch, voltage noise may be generated by the resistance loads of the transmitter and receiver section connected to the input/output terminals s 1 and s 2 , causing the noise to be superimposed on the received signal passing the input/output terminals s 1 and s 2 .

In the present embodiment, the noise cut circuit is connected between the nodes n 2 and n 3 , so that the current generated when a signal inputted to the switch from SWIN 1 is level-shifted at Latch 1 and the current from the current source I 1 included in the floating voltage generator are led to the reference power supply VSS via the source and drain of the PMOS transistor HP 1 and the diode D 3 .

Therefore, the current generated when the control signal sent to the common gate terminal G H is switched by Latch 2 is the only current that flows, via the node n 2 , through the common source terminal S H . The current generated at Latch 2 that switches the control signal comprised of the potential difference VZ+Vgsp is much smaller than the current generated when the input signal is level-shifted at Latch 1 . It is, therefore, possible to realize a T/R switch with a very low noise characteristic.

Thus, without coupling the nodes n 2 and n 3 to equalize their potentials, providing the noise cut circuit between the nodes n 2 and n 3 makes it possible to realize a low noise characteristic in addition to a wide band characteristic.

Second Embodiment

FIG. 2 is a diagram showing a second embodiment of a switch circuit including a main switch and a floating voltage circuit.

The switch circuit of the second embodiment includes the switch circuit configuration shown in FIG. 1 with a slew rate adjuster additionally provided between the output terminal of Latch 2 and the common gate terminal G H . The slew rate adjuster is connected to the nodes n 1 and n 2 , and includes a buffer which operates with the potential generated in the floating voltage generator and the potential of the common source terminal S H with a resistor R 1 connected between the node n 1 and the buffer.

In the present embodiment, the slew rate of the gate control signal is varied by making the gate control signal outputted from Latch 2 pass through the buffer. When turning on the main switch which is in an off-state, an on signal equaling the sum of the common source terminal potential, Vgsp and VZ is outputted from the output terminal of Latch 2 and the on signal is buffered in the buffer circuit. At this time, the resistor R 1 connected to the node n 1 reduces the slew rate of the main switch being turned on.

This makes it possible to reduce the currents flowing to the input terminals s 1 and s 2 when the gate parasitic capacitances Cgd and Cgs of the NMOS transistors HN 1 and HN 2 are charged. By reducing the currents that can generate noise via external loads, noise superimposition on a signal received during reception operation can be greatly reduced.

Third Embodiment

FIG. 3 is a diagram showing a third embodiment of a switch circuit including a main switch and a floating voltage circuit.

The switch circuit of the third embodiment is equivalent to the switch circuit shown in FIG. 1 additionally including zener diodes DZ 2 and DZ 3 connected in series to the node n 2 to which the gate terminal of the PMOS transistor HP 1 included in the noise cut circuit is connected and to the node n 3 to which the source terminal of the PMOS transistor HP 1 is connected. The zener diodes DZ 2 and DZ 3 are connected to the node n 3 on their anode side and to the node n 2 on their cathode side.

In the present embodiment, gate control for the main switch is performed by the same means as used in the first embodiment. When the main switch is turned on and a received signal ΔV 1 is made to pass through from the input/output terminal s 1 to the input/output terminal s 2 , the potential of the common source terminal S H and the potential of the node n 2 become equal to the potential of the received signal ΔV 1 . When the received signal ΔV 1 passes the main switch, the gate-source voltage Vgsp of the PMOS transistor HP 1 is smaller than the sum, 2 VDth of threshold voltages of DZ 2 and DZ 3 , so that the currents from Latch 1 and I 1 flow to the reference power supply VSS via the drain and source of the PMOS transistor HP 1 without passing through DZ 2 and DZ 3 .

When the main switch is turned off and a +Vout signal is applied to the input/output terminal s 1 from a general transmitter used in an ultrasonograph, the potential of the common source terminal S H is fixed at a potential equal to the sum of the potential of the input/output terminal s 2 and the threshold voltage VF of the parasitic diode D 2 included in the NMOS transistor HN 2 . If the input/output terminal s 2 is grounded when the +Vout signal is received, the potential of the common source terminal S H will become VF (1 V or lower). Then, the same as when the main switch is turned on, the currents from Latch 1 and I 1 flow to the reference power supply VSS via the drain and source of the PMOS transistor HP 1 , so that the potentials of the common source terminal S H and common gate terminal G H are kept equal.

When the main switch is turned off and a −Vout signal is applied to the input/output terminal s 1 from a general transmitter used in an ultrasonograph, the potential of the common source terminal S H follows the −Vout signal via the parasitic diode D 1 of the NMOS transistor HN 1 . Namely, the potential of the common source terminal S H changes to a potential equal to the sum of the potential of the input/output terminal s 1 and the threshold voltage VF of the parasitic diode D 1 of the NMOS transistor HN 1 (−Vout+VF). Hence, the potential of the node n 3 connected to the source terminal of the PMOS transistor HP 1 becomes equal to the sum of −Vout, VF, and Vgsp. When, however, the potential of the node n 3 becomes lower than the potential (VSS+VF) determined by the reference power supply VSS and the threshold voltage of the diode D 3 , the PMOS transistor HP 1 enters an off-state, so that the currents from Latch 1 and the constant current source I 1 can no longer flow to the reference power supply VSS. When this occurs, the potential of the node n 3 cannot follow a sudden change in the potential of the node n 2 and, as a result, the PMOS transistor HP 1 is possibly broken.

In the present embodiment, to avoid such an occurrence, the zener diode DZ 2 is connected on its anode side to the node n 3 and the zener diode DZ 3 is connected on its cathode side to the node n 2 so as to cause, when the potential of the node n 3 differs 2VF or more from the potential of the node n 2 , the currents from Latch 1 and I 1 to flow to the common source terminal S H via DZ 2 and DZ 3 .

This enables the node n 3 to follow the potential of the node n 2 even when a signal with a voltage of −Vout is inputted to the input/output terminal s 1 causing the potential of the node n 2 to sharply change, so that the off signal for the main switch is stably maintained to protect the floating voltage circuit.

Also, with the diode D 3 provided between the drain of the PMOS transistor HP 1 and the reference power supply VSS, application, upon a potential drop at the node n 2 , of a high voltage between the gate and drain of the PMOS transistor HP 1 is prevented. This allows a small transistor with a low withstand voltage to be used as the PMOS transistor HP 1 .

Assume a case in which: the main switch is turned off; a −Vout signal is applied to the input/output terminal s 1 from a general transmitter used in an ultrasonograph; and, after a certain period of time, a +Vout signal is inputted from the input/output terminal s 1 . In this case, the potential change that takes place when the signal applied changes from −Vout to +Vout causes the current from the constant current source I 1 to flow to the nodes n 2 and n 3 and the potential of the common source terminal S H to rise from the sum of −Vout and VF. When the signal applied exceeds 0 V with the input/output terminal s 2 grounded, the potential of the common source terminal S H is fixed at the threshold voltage VF of the parasitic diode D 2 of the NMOS transistor HN 2 and the potential of the node n 3 is fixed at the sum of VF and Vgsp.

At this time, the PMOS transistor HP 1 enters an on-state and the current from the constant current source I 1 flows to the reference power supply VSS. Subsequently, a +Vout signal is applied to the input/output terminal s 1 with the potentials of the common source terminal S H and node n 3 fixed. Hence, the common source terminal S H and common gate terminal G H can quickly follow changes in the potential of the ±Vout signals so as to stably maintain the off-operation of the main switch.

Fourth Embodiment

FIG. 4 is a diagram showing a fourth embodiment of a switch circuit including a main switch and a floating voltage circuit.

The switch circuit of the fourth embodiment is equivalent to the switch circuit shown in FIG. 3 additionally provided with a GND switch connected to the input/output terminal s 2 .

The GND switch includes a PMOS transistor LP 1 and an NMOS transistor LN 1 . The drains of LP 1 and LN 1 are connected to a common drain terminal which is connected to the input/output terminal s 2 of the main switch. The sources of LP 1 and LN 1 are connected to a grounded common source terminal. An LP 1 control terminal G LP is connected to the gate terminal of LP 1 . An LN 1 control terminal G LN is connected to the gate terminal of LN 1 . Signals applied to the G LP and G LN are simultaneously controlled so as to turn on and off LP 1 and LN 1 simultaneously.

The GND switch operates complementarily to the main switch. Namely, when the main switch turns on, a signal L is inputted to G LP and G LN causing the GND switch to turn off and, when the main switch turns off, a signal H is inputted to G LP and G LN causing the GND switch to turn on.

Now, assume a case where: a transmitter used in a general ultrasonograph is connected to the input/output terminal s 1 ; a receiver is connected to a node n 4 where the input/output terminal s 2 and the GND switch are connected; and the main switch is turned off. When a signal of a maximum of ±Vout transmitted from the transmitter is inputted to the input/output terminal s 1 , the input signal is clamped by the parasitic diode D 1 or D 2 of the NMOS transistor HN 1 or HN 2 of the main switch, so that the input signal is not directly transmitted to the node n 4 inclusive of the input/output terminal s 2 . It is, however, possible that the potential of the node n 4 is caused to change by crosstalk from the input signal. An excessive potential change if caused may result in breaking receiver elements.

In the present embodiment, to avoid such a result, when a signal for turning the main switch off is received, the GND switch is turned on. This causes the node n 4 to be grounded, so that the potential change due to crosstalk from the input signal can be reduced. As a result, the receiver connected to the node n 4 can be protected.

As described above, applying the switch circuit of the present embodiment to a T/R switch makes it possible to realize a switch circuit which is, besides having wide-band, low-noise characteristics, highly effective as a receiver protection circuit.

Fifth Embodiment

FIG. 5 is a diagram showing an embodiment of a semiconductor integrated circuit including a transmitter and a T/R switch and configured on a single semiconductor substrate. The transmitter generates, based on an input logic signal, a pulse signal for transmission. The T/R switch is one to which the switch circuit shown in FIG. 4 is applied for use in an ultrasonograph.

The transmitter includes a logic circuit, a driver, and a pulser. The logic circuit transmits, based on a digital signal inputted from an input terminal IN, a drive circuit control signal TIN and a control signal for the T/R switch. The driver converts the drive circuit control signal TIN into a drive signal for the pulser. The pulser generates a transmission pulse signal having an amplitude variable range of approximately 0 to ±100 V and a frequency variable range of approximately 1 to 40 MHz.

The T/R switch includes, as described in connection with the fourth embodiment, a main switch, a floating voltage circuit, and a GND switch. The T/R switch separates the receiver and the transmitter.

The output section of the transmitter is connected to the input/output terminal s 1 of the T/R switch and, via an output terminal HVout of the semiconductor integrated circuit, to a transducer formed of a piezoelectric element. The receiver that receives and amplifies a reflected signal, then converts the signal into a digital signal is connected, via an output terminal LVout, to the input/output terminal s 2 of the T/R switch.

When outputting a transmission signal, the T/R switch is turned off so as to allow the transmission signal generated by the transmitter to be outputted, via HVout, to the transducer to generate ultrasonic sound waves. At this time, with the GND switch kept on, LVout connected to the receiver is fixed at 0 V thereby functioning as a receiver protection circuit.

When a reflected signal is received from the transducer, the T/R switch is switched from an off-state to an on-state and the signal received from HVout is transmitted to the receiver via LVout. The T/R switch of the present embodiment can realize a low-noise characteristic and makes it possible to transmit a received signal without degrading it in an ultrasonograph.

As described above, using the T/R switch of the present embodiment makes it possible to realize low-noise, wide-band transmission in an ultrasonograph. Furthermore, using a semiconductor integrated circuit including a T/R switch and a transmitter formed on a same chip can promote device cost reduction and device miniaturization.

Preferred embodiments of the present invention have been described above, but the invention is not limited by the above embodiments. It will be easily understood by those skilled in the art that various modifications including combining two or more of the above embodiments are possible within the scope of the invention.