Precision oscillator with temperature compensation

This application claims the benefit of U.S. Provisional Application No. 61/434,292 entitled “HIGH-PRECISION OSCILLATOR” filed on Jan. 19, 2011, the content of which is incorporated herein by reference in its entirety.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Oscillators are used in almost every modern electronic device and come in a large variety of configurations, Unfortunately, the performance of all of these oscillators is susceptible to a variety of factors, such as aging and environmental conditions, which cause the oscillators to drift in frequency. Unfortunately, compensating for such factors can add substantial expense for minimal performance gains. Accordingly, new approaches to oscillator compensation may be desirable.

Various aspects and embodiments of the invention are described in further detail below.

In an embodiment, an oscillator comprises a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input and second input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input and second input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.

In another embodiment, an oscillator comprises a first comparator and a second comparator, compensation circuitry electrically connected to the first comparator and the second comparator, the compensation circuitry configured to compensate for a difference in respective input offset voltages of the first comparator and the second comparator, and control circuitry electrically coupled to the first comparator and the second comparator, the control circuitry configured to control oscillation of the oscillator.

In yet another embodiment, an oscillator comprises a first capacitor electrically connected to a first charging switch and a first discharging switch; a second capacitor electrically connected to a second charging switch and a second discharging switch; a first comparator and a second comparator; and compensation means electrically connected to the first capacitor, the second capacitor, the first comparator and the second comparator, the compensation means for compensating for a difference in respective input offset voltages of the first comparator and the second comparator; and control means electrically coupled to the first comparator and the second comparator for controlling the charging switches and discharging switches.

Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

FIG. 1 is an example of a known oscillator.

FIG. 2 depicts various ideal and non-ideal waveforms produced by the oscillator of FIG. 1 .

FIG. 3 is an example oscillator modified to compensate for non-ideal components.

FIG. 4 depicts an example of a chopping circuit used in the oscillator of FIG. 3 .

FIG. 5 depicts the waveforms produced by the modified oscillator of FIG. 3 .

The disclosed methods and systems below may be described generally, as well as in terms of specific examples and/or specific embodiments. For instances where references are made to detailed examples and/or embodiments, it is noted that any of the underlying principles described are not to be limited to a single embodiment, but may be expanded for use with any of the other methods and systems described herein as will be understood by one of ordinary skill in the art unless otherwise stated specifically.

FIG. 1 is an example of a known oscillator 100 . The oscillator 100 includes a constant current source I C , a first charging switch SWC 1 , a second charging switch SWC 0 , a first discharging switch SWD 1 , a second discharging switch SWD 0 , a first capacitor C 1 , a second capacitor C 0 , a first comparator CP 1 , a second comparator CP 0 , an SR-latch L 1 , and a buffer B 1 .

In operation, the latch L 1 , which acts as control circuitry for the oscillator 100 , causes the various switches {SWC 1 , SWC 0 , SWD 1 , SWD 0 } to open and close in a controlled fashion thus charging and discharging capacitors C 1 and C 0 in an alternating manner as will be shown below with respect to FIG. 2 . Since C 1 and C 0 can be chosen as well-controlled temperature-independent metal-insulator-metal capacitors, it is advantageous for C 1 and C 0 to be much larger than other parasitic capacitances at the inputs of the comparators CP 1 and CP 0 , because the parasitic capacitances are hard to control and vary with temperature. This, in turn, limits the size of the input stages of comparators CP 1 /CP 0 and therefore results in a large input-referred offset of said comparators.

As the capacitors C 1 and C 0 alternatively charge and discharge, saw-tooth waveforms are produced (voltages V CH1 and V CH0 ), which are fed to inputs of comparators CP 1 and CP 0 to allow each the voltages V CH1 and V CH0 to be respectively compared to a reference voltage V REF . The output signals of the comparators CP 1 and CP 0 are then fed to respective inputs to the latch L 1 , which in turn changes state to provide feedback control to the switches {SWC 1 , SWC 0 , SWD 1 , SWD 0 }.

FIG. 2 depicts various ideal and non-ideal waveforms { 201 , 202 , 203 , 204 } produced by the oscillator of FIG. 1 .

Turning first to ideal waveform 201 , assuming that the capacitances of capacitors C 1 and C 0 are equal, the ideal voltage pattern for voltages V CH1 and V CH0 will be identical saw-tooth patterns displaced in time/phase by 180°. Note that, in the ideal case, the waveforms of voltages V CH1 and V CH0 will oscillate between zero volts and the reference voltage V REF . This is because as the respective comparators CP 1 and CP 0 change output state (e.g., when V CH1 ≧V REF ), the state of the outputs of latch L 1 will change, which in turn will change the on/off positions of the switches {SWC 1 , SWC 0 , SWD 1 , SWD 0 }. The output of the buffer 131 for the ideal case is depicted by waveform 203 .

Now turning to a non-ideal (actual, real-world) scenario, it is to be appreciated that real-world comparators have an input-offset voltage (typically represented by the symbol “Vos”) between their inputs. It is also to be appreciated that two different comparators can have different input-offset voltages, which for the purpose of this disclosure is represented by the symbol “V OFF .” This offset difference V OFF , which can change over time or over varying operating conditions, such as temperature, can affect the output frequency/periodicity of the oscillator 100 . As shown in waveform 202 , the exemplary offset V OFF causes amplitude and relative duration waveform differences in voltages V CH1 and V CH0 . The output of the buffer B 1 for the non-ideal case is depicted by waveform 204 , and can be easily contrasted with waveform 203 .

FIG. 3 is an example oscillator 300 modified to compensate for non-ideal components, such as the varying input-offset voltages discussed with respect to FIGS. 1 and 2 . As with the oscillator 100 of FIG. 1 , the modified oscillator 300 includes a constant current source I C , a first charging switch SWC 1 , a second charging switch SWC 0 , a first discharging switch SWD 1 , a second discharging switch SWD 0 , a first capacitor C 1 , a second capacitor C 0 , a first comparator CP 1 , a second comparator CP 0 , an SR-latch L 1 , and a buffer B 1 . However, the modified oscillator also includes a first chopper MX 1 and a second chopper MX 0 , and the control circuitry 310 is expanded from latch L 1 to further include a first exclusive-or (“XOR”) gate X 1 , a second XOR gate X 0 , a first flip-flop D 1 and a second flip-flop D 0 .

In operation, the control circuitry 310 (via latch L 1 ) causes the various switches {SWC 1 , SWC 0 , SWD 1 , SWD 0 } to open and close in a controlled fashion thus charging and discharging capacitors C 1 and C 0 in an alternating manner, with the resultant waveforms respectively fed to a respective first input to choppers MX 1 and MX 0 . The reference voltage V REF is fed to a second input of each chopper MX 1 and MX 0 .

The outputs of each chopper MX 1 and MX 0 will change depending on the state of control signals CHOP 1 and CHOP 0 respectively produced by flip-flops D 1 and D 0 . For example, for CHOP 1 =HIGH MX 1 will pass voltage V CH1 to the positive (+) input of comparator CP 1 and the reference voltage V REF to the negative input (−) of comparator CP 1 , while for CHOP 1 =LOW, MX 1 will pass voltage V CH1 to the negative input of comparator CP 1 and the reference voltage V REF to the positive input of comparator CP 1 . Chopper MX 0 acts in a similar fashion.

The output signals of the comparators CP 1 and CP 0 are then fed to their respective exclusive-or gates X 1 and X 0 , which in turn are logically combined with the CHOP 1 and CHOP 0 signals. The outputs of gates X 1 and X 0 are fed to respective inputs of latch L 1 , which in turn changes state to provide feedback control to the switches {SWC 1 , SWC 0 , SWD 1 , SWD 0 }.

Additionally, as the clock input of flip-flop D 1 is electrically connected to the positive output of the latch L 1 , the state of control signal CHOP 1 will change every time the positive output of the latch L 1 transitions from low to high. Similarly, as the clock input of flip-flop D 0 is electrically connected to the negative output of the latch L 1 , the state of control signal CHOP 0 will change every time the negative output of the latch L 0 transitions from low to high. The changing states of control signals CHOP 1 and CHOP 0 are fed back to control ports of the choppers MX 1 and MX 0 and to inputs of gates X 1 and X 0 , thus causing the choppers MX 1 and MX 0 and gates X 1 and X 0 to change operation in a deterministic fashion.

FIG. 4 depicts an example of a chopping circuit MX used in the oscillator of FIG. 3 . As shown in FIG. 4 , the chopping circuit MX includes an inverter I 1 and four switches SW 1 , SW 2 , SW 3 and SW 4 . The theory and operation of such chopping circuitry (also called chopping circuitry or choppers) are well known with respect to analog-to-digital conversion devices. When control signal CHOP is HIGH, input IN 0 is connected/coupled to output OUT 0 and input IN 1 is connected/coupled to output OUT 1 . When control signal CHOP is LOW, however, input IN 0 is connected/coupled to output OUT 1 and input IN 1 is connected/coupled to output OUT 0 .

FIG. 5 depicts waveforms { 501 , 502 } produced by the modified oscillator 300 of FIG. 3 . As shown in waveform 501 , the difference offset V OFF is still present and affects the oscillator 300 , but the overall effect upon voltages V CH1 and V CH0 is different. That is, a varying V OFF now causes complementary changes in V CH1 and V CH0 . While the resultant output V OUT of buffer 131 (shown in waveform 502 ) does not produce a perfect square wave, frequency/periodicity variance due to component differences is reduced or eliminated. Another advantage is that long-term influence of 1/f noise inherent in the comparators CP 1 and CP 0 is reduced or removed. It is to be appreciated that if the oscillator 300 is run at 2× speed, a divide-by-2 circuit, such as a D-flop, may be used to produce a more suitable square-wave output.

While the invention has been described in conjunction with the specific embodiments thereof that are proposed as examples, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the invention as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the scope of the invention.