Method of constraint-hierarchy-driven IC placement

This application claims the benefit of priority of U.S. Provisional Application No. 61/489,269, filed May 24, 2011, and titled “Constraint Hierarchy Driven Automatic IC Placement”, the contents of which are herein incorporated by reference in its entirety.

1. Field of the Invention

The invention relates in general to a computer-implemented method for generating placements for integrated circuits (ICs) and, in particular, to a method for generating placements for analog ICs using constraint trees.

2. Description of the Prior Art

In modern IC industry, analog ICs gain more and more importance. An analog IC is described by a netlist which includes a set of interconnected device modules such as transistors, capacitors, resisters and other devices. The functionality and performance of the analog ICs are heavily influenced by the placement of the device modules of the circuits. A computer-implemented placement tool processes a netlist to determine a suitable position and orientation for each of the device modules within the IC. To guarantee a correct functionality and best performance for the analog ICs, a set of constraints are provided for placing the device modules.

For example, “symmetry constraint” is introduced to reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations. According to the symmetry constraint, two device modules are placed symmetrically with respect to a common axis. Symmetry constraints are typically categorized into three types. The first type is horizontal one-dimensional symmetry constraint; the second type is vertical one-dimensional symmetry constraint; and the third type is two-dimensional symmetry constraint.

Another example is “proximity constraint” or “cluster constraint” which limits a particular group of devices placed near one another so that they can be interconnected by short wires.

Another common example of constraints is “matching constraint” which specifies a pre-defined matching placement pattern for a circuit. For instance, a current mirror circuit comprises two transistors which should be tightly coupled with a specific gate orientation. Other constraints such as spacing, boundary, clearance, etc., are also well-known and commonly used in analog IC placement.

U.S. Pat. No. 7,873,928 entitled “Hierarchical Analog IC Placement Subject to Symmetry, Matching and Proximity Constraints” discloses a method of defining a multiple-level hierarchy of constraint groups and generating an optimal placement. However, the proposed approach assumes that all the constraints are self-contained and does not mention how to deal with constraint conflicts.

FIG. 1 depicts a block diagram which illustrates a general concept of a prior approach in how to handle constraints. Block 11 represents a set of constraints for an IC design. The constraints 11 are directly saved into a constraint database 12 without any additional checking. A placer 13 refers to the constraint database 12 and tries to find placements that satisfy all the constraints in the constraint database 12 .

However, constraints can conflict with each other. It means that two constraints cannot be satisfied at the same time. Thus all the placer 13 can do is trying to satisfy as many constraints as possible without analyzing the conflicts in a systematical way.

Therefore, what is needed is a systematic approach to analyze an IC design and its corresponding constraints. In addition, the analysis result should be able to detect and resolve conflicts of constraints. Furthermore, it is desired to find a systematic approach to generate placements for the IC design while meeting all the constraints based on the analysis result.

One object of the present invention is to generate placements for a plurality of device modules within an analog integrated circuit (IC) subject to a set of constraints.

One embodiment in the present invention is to provide a computer-implemented method to partition the IC design into a hierarchy of groups of device modules by building a hierarchy tree of constraints to associate each of the groups with the corresponding constraint in a prioritized order. In the hierarchy tree, a root node represents the IC design; a plurality of nodes represents either the constraints or the device modules within the IC.

In the process of building the hierarchy tree, conflicts of constraints can be identified by checking whether nodes representing the constraints can be successfully inserted into the hierarchy tree or not. Furthermore, conflicts of the constraints can be resolved by removing the conflicted constraints with lower priorities.

Based on the hierarchy tree, a bottom-to-top process can be executed to generate placements for each of the constraints at a node. In addition, a cost-function is defined which may refer to the dimensions, and possibly other characteristics, of a placement; and each placement will be evaluated based on the cost function to prune some placements with higher costs. Moreover, placements can be further optimized by using a top-down process for wire length optimization.

Other objects, technical contents, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.

The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic block diagram of a prior approach to handle constraints;

FIG. 2 is a schematic block diagram of the present invention;

FIG. 3A and FIG. 3B illustrate a schematic flow diagram for creating a hierarchy tree and generating a placement;

FIG. 4A-FIG . 4 H show an example to explain the process of hierarchy tree creation;

FIG. 5 shows one embodiment to represent a symmetry constraint when creating a hierarchy tree;

FIG. 6 illustrates a schematic flow diagram for bottom-to-top placement generation process;

FIG. 7A-FIG . 7 C show an example to explain the process of generating a placement using bottom-to-top process; and

FIG. 8A-FIG . 8 D show an example to explain the process of top-down wire length optimization.

The detailed explanation of the present invention is described as following. The described preferred embodiments are presented for purposes of illustrations and description, and they are not intended to limit the scope of the present invention.

An analog integrated circuit (IC) design is typically provided in the form of a netlist having a plurality of interconnected device modules. Furthermore, a plurality of constraints are provided for generating the placement of the IC design.

In order to avoid possible ambiguity and to improve performance for placement generation, it is necessary to first analyze the relationship among the constraints, and a constraint hierarchy tree is introduced for this purpose. The IC design is partitioned into hierarchical groups of device modules in order to meet the constraints. Afterwards, a placement process is executed to reassemble the partitioned groups of device modules into a complete placement for the IC based on the constraint hierarchy tree systematically.

FIG. 2 illustrates a general concept of the invention. Block 23 is responsible for building a constraint hierarchy tree according to the set of constraints (block 21 ). A placer (block 22 ) refers to the hierarchy tree built by block 21 for generating placements of the IC design. Further details are described in the following sections.

Hierarchy Tree Generation

FIG. 3A and FIG. 3B show a schematic flow diagram which illustrates a method of processing the netlist to generate a hierarchy tree which is used to further generate possible placements for the IC design. Moreover, the method ensures that there exist no conflicts among the constraints in the hierarchy tree when it is finally built successfully.

First, please refer to FIG. 3A . A plurality of constraints are provided for the IC design (step 31 ). Some of the constraints may come from an existing database or can be provided by users. Others of the constraints can be obtained by matching the IC design with a plurality of pre-defined circuit patterns to extract the constraints. One example is to extract cluster constraints according to a plurality of identified circuit building blocks, such as voltage-controlled resistor, current mirror load, level shifter and differential pairs; another example is to extract cluster constraints by identifying device modules of the same type (e.g., PMOS and NMOS) with similar connection; and yet another example is to extract symmetry constraints by measuring all current flows from the power (VDD) to the ground (GND) of the IC design. If two current flows which are associated with two set of device modules respectively are of the same parameters, the corresponding two paths of the two current flows are identified to be symmetric. Consequently, each of the device modules in one path and the corresponding device module in the other path form a symmetry pair. In step 32 , the constraints are prioritized and a list of constraints is formed according to their priorities. Please note that a constraint which covers a smaller scope typically gains a higher priority.

In step 33 , according to the information in the netlist, an initial hierarchy tree is built. The initial hierarchy tree is a two-level tree which comprises a root node and a plurality of leaf nodes. The root node represents the IC design. Each of the leaf nodes represents one device module in the IC design.

Referring to step 34 in FIG. 3B , a node associated with a constraint with the highest priority in the constraint list is inserted into the hierarchy tree. The node represents the constraint. Furthermore, corresponding attributes for the constraint can be recorded in the node. For example, if the constraint is a symmetry constraint, attributes such as symmetry pairs and symmetry axes are recorded. If the constraint is a matching constraint, a corresponding matching placement pattern is recorded as an attribute.

In addition, there is only a single route for each of the leaf node to reach the root node. A node is eventually inserted into the existing hierarchy tree when there is no conflict between the constraint of the node and the constraints already existing in the hierarchy tree. In other words, if more than one route is found for any one of the leaf nodes to reach the root node after a constraint node is inserted, there is a conflict between the just-inserted constraint and the constraints currently in the hierarchy tree as shown in step 35 . To resolve the conflict, the inserted node representing the constraint is removed as illustrated in step 36 , in other words, the constraint is discarded (and may be reported to the user accordingly). In step 37 , the constraint which has been processed is removed from the constraint list. Then, if the constraint list is not empty in step 38 , a constraint with the highest priority in current constraint list will be processed by repeating step 34 to step 38 . If the constraint list is empty, the final hierarchy tree is built, and then at least one placement can be generated according to the hierarchy tree in step 39 . The details of generating the placements will be described later.

In one embodiment, if users need to refine constraints, it can be done by inserting, moving, or removing related nodes for the corresponding constraints on the constraint hierarchy tree directly. A graphical user interface may be used to display the tree, and the user can edit the tree visually and interactively. The edited tree can be used to produce a new list of constraints to save on disk. Through this systematic way, we can ensure that the refinement will not introduce any conflicts.

FIGS. 4A-4E illustrate an example of hierarchy tree generation. An IC design comprises device modules D 1 , D 2 , D 3 , D 4 , D 5 , D 6 and D 7 , and four constraints are provided. The first constraint is a symmetry constraint (denoted as S 0 ) which D 5 , D 6 and D 7 are subject to, i.e. constraint S 0 is applied to device modules D 5 , D 6 and D 7 ; the second constraint is a cluster constraint (denoted as C 0 ) which D 1 and D 2 are subject to; the third constraint is a cluster constraint (denoted as C 1 ) which D 3 and D 4 are subject to; and the fourth constraint is a cluster constraint (denoted as C 2 ) which D 4 and D 5 are subject to.

In order to build the hierarchy tree with constraints, a two-level hierarchy tree is initiated as shown in FIG. 4A in which a root node is denoted as “TOP” and seven leaf nodes are created for device modules D 1 -D 7 ; and the constraints are prioritized in the order of S 0 , C 0 , C 1 and C 2 .

As shown in FIG. 4B , a node “S 0 ” is inserted according to the constraint S 0 . For a symmetry constraint, some attributes, such as symmetry pairs and symmetry axes, are recorded and associated with the corresponding node. Then, as shown in FIG. 4C , a node “C 0 ” is inserted according to the constraint C 0 , and no conflict is detected. Next, a node “C 1 ” is inserted according to the constraint C 1 as shown in FIG. 4D , and no conflict is detected either.

Finally, as shown in FIG. 4E , a node “C 2 ” is inserted according to the constraint C 2 . However, two routes can be found from leaf node D 4 to reach the root node; and the same situation applies to leaf node D 5 as well, which means the C 2 constraint conflicts with the existing constraints and thus should be removed; and the hierarchy tree should be remained as it is in FIG. 4D .

After executing the above steps, a hierarchy tree is built with three constraints, S 0 , C 0 and C 1 , without any conflict, and the other constraint, C 2 , is discarded.

Please continue to refer to FIG. 4F to FIG. 4H which depict an example for multi-level constraints. An IC design comprises device modules D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 and D 8 , and six constraints are provided for generating placements. The first constraint is a symmetry constraint (denoted as S 0 ) which D 5 , D 6 and D 7 are subject to; the second constraint is a cluster constraint (denoted as C 0 ) which D 1 and D 2 are subject to; the third constraint is a cluster constraint (denoted as C 1 ) which D 3 and D 4 are subject to; the fourth constraint is a cluster constraint (denoted as C 2 ) which C 1 and D 8 are subject to; the fifth constraint is a cluster constraint (denoted as C 3 ) which C 0 and C 2 are subject to; and the sixth constraint is a cluster constraint (denoted as C 4 ) which C 3 and D 5 are subject to. In addition, the constraints are prioritized in the order of S 0 , C 0 , C 1 , C 2 , C 3 and C 4 .

After applying the same steps as in FIG. 4A to FIG. 4D for S 0 , C 0 , and C 1 , a node for constraint C 2 can be inserted in a similar way as shown in FIG. 4F , wherein the child nodes of C 2 are C 1 and D 8 . Next, a node for constraint C 3 is further inserted as illustrated in FIG. 4G , wherein the child nodes of C 3 are C 0 and C 2 . Finally, a node for constraint C 4 is inserted as in FIG. 4H in which a conflict is found, therefore, the constraint C 4 should be discarded.

From the examples demonstrated in FIG. 4A to FIG. 4H , it is concluded that there are two ways to detect conflicts among constraints. The first way is to check if more than one route can be found for any leaf node to reach the root node. As shown in FIG. 4E , device module D 4 has two routes to reach the root node, which indicates a conflict. The second way is to check if two constraints have a common set of device modules, wherein the common set of device modules is not equal to the set of device modules of one of the two constraints, and the common set of device modules is not equal to the set of device modules of the other of the two constraints. Referring to FIG. 4E again to compare the device modules of C 1 and C 2 , there is a common device module D 4 between C 1 and C 2 . Furthermore, D 4 is not equal to the set formed by D 3 and D 4 ; D 4 is not equal to the set formed by D 4 and D 5 , either. By using this way, a conflict can be detected as well.

Regarding representing a symmetry constraint in the hierarchy tree, in one embodiment, two additional nodes can be inserted under the node representing the constraint to create symmetrical sub-groups for the corresponding device modules. Please refer to FIG. 5 which illustrates the presentation for the example mentioned in FIGS. 4A-4E . Under the node S 0 , two nodes, “LEFT” and “RIGHT”, are inserted to indicate that the corresponding device modules are placed symmetrically with respect to a vertical axis. Furthermore, D 5 and D 7 * are arranged under node “LEFT” and D 6 and D 7 * are arranged under node “RIGHT”, which means D 5 and D 6 are symmetric with respect to the vertical axis and D 7 is self-symmetric with respect to the vertical axis.

Additionally, based on the nature of constraints, some constraints do not affect the structure of the hierarchy tree. In other words, it is not necessary to insert a node for those constraints, and these constraints will be treated as attributes when generating placements. Therefore, the above-mentioned constraints should be recorded in the nodes of the hierarchy tree for placement generation. For example, given an alignment constraint applied to a set of device modules which are subject to a cluster constraint, the alignment property will be recorded in the node which represents the cluster constraint. Another example is that, given a clearance constraint applied to a set of device modules which are subject to a cluster constraint, the clearance range will be recorded in the node which represents the cluster constraint. The above-mentioned constraints which do not affect the structure of the hierarchy tree will be referenced when generating placements.

Bottom-to-Top Placement Generation

For an IC design, typically at least one set of width and height dimensions is defined for each of the device modules, and a cost function can be used to measure a placement quality according to the dimensions of the device modules. Please refer to FIG. 6 which further depicts a detailed flow diagram for placement generation based on a hierarchy tree for the IC design.

First, all possible placements are generated for each of the nodes which represent constraints from the bottom to the top of the hierarchy tree (step 61 ).

Next, a cost function is evaluated for each placement associated with each of the constraints in step 62 . Then, according to the cost function evaluations, at least one better placement can be chosen for each of the nodes in step 63 . Thus, the number of possible placements in upper level of nodes can be reduced because some high-cost placements are pruned. As a result, the runtime of the placement program can be reduced. After confirming that no further nodes to be processed in step 64 , at least one placement for the root node can be generated by combining the placements of the root node's child nodes in step 65 .

Note that any floorplanning method (such as simulated annealing, greedy algorithm, etc.) and any floorplanning representation (such as sequence pair, B*-tree, transitive closure graph (TCG), etc.) can be used at step 61 and 65 as long as it can generate placement results. The details are not described herein.

FIGS. 7A-7C illustrate an example of bottom-to-top placement generation according to a built constrain hierarchy tree. In FIG. 7A , dimensions are defined for each of the device modules which are represented by the leaf nodes. Note that two possible dimensions are recorded for device module D 4 . Next, all possible placements for C 0 and C 1 are generated and recorded in the corresponding nodes. All possible placements for S 0 are also generated and recorded in the corresponding nodes according to the symmetry attributes. FIG. 7B shows some of the possible placements for C 0 , C 1 and S 0 . Finally, all possible placements are generated according the placements which are generated for C 0 , C 1 and S 0 . Note that only some of the possible placements for the root node are shown in FIG. 7C .

Top-Down Wire Length Optimization

Although dimension optimization is done for the placements through the bottom-to-top process as described above, placements with same dimensions may have different total wire lengths. Thus we can further optimize total wire length by using a top-down approach while keeping placement dimensions the same or even smaller.

Using the example mentioned above, FIG. 8A shows the result of rearranging one of the placements of the root node while keeping dimensions the same. Then at least one placement can be chosen with the smallest wire length.

The similar step can be performed for each of the constraints from the top to the bottom of the hierarchy tree. FIGS. 8B-8D show some placements for wire length optimization. As a result, at least one placement with smaller wire length can be selected from the placements to optimize the wire length for each of the nodes in the hierarchy tree by using the top-down process.

It is to be noted that during the top-down process for wire length optimization, the “current best” placement for the root note is always used for calculating the differences caused by various placements within the current node. After the placement with smallest total wire length is chosen for the current node, the “current best” placement for the root node is updated accordingly. Then, the process moves on to the next node in the hierarchy, and the optimization process continues.

In summary, the invention provides a systematic way to analyze the constraints for generating placements for an IC design. A constraint hierarchy tree is built according to each of the constraints systematically to identify and resolve the conflicts among the constraints. Once the hierarchy tree is built, a systematic placement process can be performed to generate at least one placement efficiently.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustrations and description. They are not intended to be exclusive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.