Resistive memory and program verification method thereof

This Application claims priority of Taiwan Patent Application No. 100131032, filed on Aug. 30, 2011, the entirety of which is incorporated by reference herein.

1. Technical Field

The disclosure relates to a resistive memory.

2. Description of the Related Art

An advantage of a resistive random access memory (RRAM) is that resistances of memory cells of the RRAM are easily differentiated between a high value and a low value. For example, if a memory cell of the RRAM is set, the resistance value of the memory cell should be at a low value. Then, the memory cell may be reset. After resetting the memory cell, the resistance value of the memory cell should be at a high value.

However, efficiency of the RRAM becomes lower as time goes by. For example, since the property of the RRAM degrades with time, when the memory cell is set, the resistance value of the memory cell may not be at a low value. Contrarily, the resistance value of the memory cell may be at a high value after the memory cell is set. Thus, error may occur in reading or writing of the memory cell.

In accordance with an embodiment, a resistive memory comprises a transistor and a variable resistor. The transistor comprises a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.

A program verification method for a resistive memory is provided. The resistive memory comprises a transistor and a variable resistor. The transistor comprises a gate, a source, and a drain. The variable resistor is coupled between the drain and a node. An exemplary embodiment of a program verification method is described in the following. During a setting period, a first gate voltage is provided to the gate, a first source voltage is provided to the source, and a first drain voltage is provided to the node. The first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, a second gate voltage is provided to the gate, a second drain voltage is provided to the node, and a second source voltage is provided to the source. The second drain voltage is less than the first drain voltage. The second source voltage is equal to the grounding voltage.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The disclosure can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an exemplary embodiment of a resistive memory;

FIGS. 2A˜2D are timing diagrams of other exemplary embodiments of a program verification operation.

FIGS. 3A˜3D are schematic diagrams of other exemplary embodiments of a program verification method.

The following description is of carrying out the disclosure. This description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is determined by reference to the appended claims.

FIG. 1 is a schematic diagram of an exemplary embodiment of a resistive memory. The resistive memory 100 comprises a transistor 110 and a variable resistor 130 . The transistor 110 comprises a gate 111 , a source 113 , and a drain 115 . The variable resistor 130 is coupled between the drain 115 and a node 150 .

During a setting period, the gate 111 receives a gate voltage Vg 1 . The source 113 receives a source voltage Vs 1 . The node 150 receives a drain voltage Vd 1 . In this embodiment, the source voltage Vs 1 is equal to a grounding voltage shown in FIGS. 2A and 2B .

After the setting period, the resistance value of the variable resistor 130 should be at a low value. However, the resistance value of the variable resistor 130 may not be at a low level due to the property of the resistive memory 100 being degraded. Thus, after the setting period, the resistance value of the variable resistor 130 is measured to determine whether the property of the variable resistor 130 is degraded.

In this embodiment, the resistance value of the variable resistor 130 is compared with a first pre-determined value. If the resistance value of the variable resistor 130 is less than the first pre-determined value, it represents that the property of the resistance value of the variable resistor 130 has not degraded. Thus, a setting operation of the resistive memory 100 is finished. Then, a reset operation may be performed for the resistive memory 100 to change the resistance value of the variable resistor 130 from a low value to a high value. In other embodiments, after setting the resistive memory 100 , the reset operation is not required to be performed. Contrarily, if the resistance value of the variable resistor 130 is not less than the first pre-determined value, it represents that the property of the variable resistor 130 has been degraded. Thus, a first verification operation is performed.

When the first verification operation is being performed, the gate 111 receives a gate voltage Vg 2 , the node 150 receives a drain voltage Vd 2 , and the source 113 receives a source voltage Vs 2 . In this embodiment the drain voltage Vd 2 is less than the drain voltage Vd 1 , and the source Vs 2 is equal to the grounding voltage. The disclosure does not limit the magnitude of the gate voltage Vg 2 . In one embodiment, the gate voltage Vg 2 is higher than the gate voltage Vg 1 , as shown in FIGS. 2A and 2B .

After the performance of the first verification operation, the resistance value of the variable resistor 130 should be at a high value. If the resistance value of the variable resistor 130 is a high value, the drain voltage Vd 2 is gradually increased until the resistance value of the variable resistor 130 is at a high value. In this embodiment, the resistance value of the variable resistor 130 is compared with a second pre-determined value. If the resistance value of the variable resistor 130 is not higher than the second pre-determined value, it represents that the resistance value of the variable resistor 130 is not at a high value. Thus, the drain voltage Vd 2 is gradually increased until the resistance value of the variable resistor 130 is higher than the second pre-determined value. If the resistance value of the variable resistor 130 is higher than the second pre-determined value, a second verification operation is performed.

When the second verification operation is being performed, the gate 111 receives a gate voltage Vg 3 , the node 150 receives a drain voltage Vd 3 , and the source 113 receives a source voltage Vs 3 . As shown in FIG. 2A , in one embodiment, the gate voltage Vg 3 is equal to the gate voltage Vg 1 , the drain voltage Vd 3 is higher than the drain voltage Vd 2 , and the source voltage Vs 3 is equal to the grounding voltage. The disclosure does not limit the relationship between the drain voltages Vd 1 and Vd 3 . The drain voltage Vd 3 may be higher than, less than or equal to the drain voltage Vd 1 .

After the performance of the second verification operation, the resistance value of the variable resistor 130 should be at a low value. Thus, in this embodiment, the resistance value of the variable resistor 130 is again compared with the first pre-determined value. If the resistance value of the variable resistor 130 is not less than the first pre-determined value, it represents that the resistance value of the variable resistor 130 is not at a low value. Thus, the drain voltage Vd 3 is gradually increased until the resistance value of the variable resistor 130 is less than the first pre-determined value.

In other embodiments (as shown in FIG. 2B ), when the second verification operation is being performed, the gate voltage Vg 3 is higher than the gate voltage Vg 1 , the drain voltage Vd 3 is equal to the grounding voltage, and the source voltage Vs 3 is higher than the source voltage Vs 2 . At this time, the resistance value of the variable resistor 130 should be less than a third pre-determined value. After the performance of the second verification operation, if the resistance value of the variable resistor 130 is not less than the third pre-determined value, the source voltage Vs 3 is gradually increased until the resistance value of the variable resistor 130 is less than the third pre-determined value. The third pre-determined value is equal to or higher than the first pre-determined value. If the third pre-determined value is equal to the first pre-determined value, a setting operation for the resistive memory 100 is finished after the performance of the second verification operation.

Contrarily, if the third pre-determined value is higher than the first pre-determined value, a third verification operation is performed. Referring to FIG. 2C , when the third verification operation is being performed, the gate 111 receives a gate voltage Vg 4 , the node 150 receives a drain voltage Vd 4 , and the source 113 receives a source voltage Vs 4 . In FIG. 2C , the gate voltage Vg 4 is equal to the gate voltage Vg 1 , the drain voltage Vd 4 is higher than the drain voltage Vd 2 , and the source voltage Vs 4 is equal to the grounding voltage.

In FIGS. 2A and 2B , the gate voltage Vg 2 is higher than the gate voltage Vg 1 . In another embodiment, the gate voltage Vg 2 is equal to the gate voltage Vg 1 . Referring to FIG. 2D , during a setting period, the gate 111 receives the gate voltage Vg 1 , the node 150 receives the drain voltage Vd 1 and the source 113 receives the source voltage Vs 1 . After the setting period, the resistance value of the variable resistor 130 should be at a low value.

If the resistance value of the variable resistor 130 is less than a first pre-determined value, it represents that the resistance value of the variable resistor 130 is at a low value. Thus, a setting operation for the resistive memory 100 is finished and then a reset operation can be performed for the resistive memory 100 to make the resistance value of the variable resistor 130 to be at a high value. Similarly, the reset operation is not required to be performed. For example, if the resistance value of the variable resistor 130 is at a low level, the reset operation can be omitted.

If the resistance value of the variable resistor 130 is not less than the first pre-determined value, it represents that the resistance value of the variable resistor 130 is not at a low level. Thus, a first verification operation is performed. When the first verification operation is being performed, the gate 111 receives the gate voltage Vg 2 , the node 150 receives the drain voltage Vd 2 , and the source 113 receives the source voltage Vs 2 . In this embodiment, the gate voltage Vg 2 is equal to the gate voltage Vg 1 , the drain voltage Vd 2 is less than the drain voltage Vd 1 , and the source voltage Vs 2 is equal to the source voltage Vs 1 .

After the performance of the first verification operation, the resistance value of the variable resistor 130 should be at a low value. Thus, the resistance value of the variable resistor 130 is compared with a second pre-determined value. If the resistance value of the variable resistor 130 is not less than the second pre-determined value, the drain voltage Vd 2 is gradually increased until the resistance value of the variable resistor 130 is less than the second pre-determined value. In one embodiment, the second pre-determined value is equal to the first pre-determined value.

FIGS. 3A˜3D are schematic diagrams of exemplary embodiments of a program verification method. The program verification method is applied to a resistive memory as shown in FIG. 1 . The operation of the program verification method is described in greater detail with reference to FIG. 1 .

Referring to FIG. 3A , during a setting period, a setting operation is performed (step S 310 A). In this embodiment, the setting operation is to provide a gate voltage Vg 1 to the gate 111 , provide a drain voltage Vd 1 to the node 150 and provide a source voltage Vs 1 to the source 113 . In one embodiment, the source voltage Vs 1 is equal to a grounding voltage GND.

It is determined whether the resistance value of the variable resistor 130 is less than a pre-determined value PV 1 (step S 320 A). If the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 , a reset operation is performed (step S 330 A) to set the resistance value of the variable resistor 130 to a high value. In other embodiments, the reset operation can be omitted if the resistance value of the variable resistor 130 is not required to be set to a high value.

If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 1 , a first verification operation is performed (step S 340 A). When the first verification operation is being performed, a gate voltage Vg 2 is provided to the gate 111 , a drain voltage Vd 2 is provided to the node 150 , and a source voltage Vs 2 is provided to the source 113 . In this embodiment, the gate voltage Vg 2 is higher than the gate voltage Vg 1 , the drain voltage Vd 2 is less than the drain voltage Vd 1 , and the source voltage Vs 2 is equal to the grounding voltage GND.

After the performance of the first verification operation, it is determined whether the resistance value of the variable resistor 130 is higher than a pre-determined value PV 2 (step S 350 A). If the resistance value of the variable resistor 130 is not higher than the pre-determined value PV 2 , the drain voltage Vd 2 is increased (step S 360 A) and then step S 350 A is executed to determine again whether the resistance value of the variable resistor 130 is higher than the pre-determined value PV 2 . If the resistance value of the variable resistor 130 is not higher than the pre-determined value PV 2 , the drain voltage Vd 2 is again increased until the resistance value of the variable resistor 130 is higher than the pre-determined value PV 2 . In this embodiment, the drain voltage Vd 2 is gradually increased such that the resistance value of the variable resistor 130 is higher than the pre-determined value PV 2 .

When the resistance value of the variable resistor 130 is higher than the pre-determined value PV 2 , a second verification operation is performed (step S 370 A). When the second verification operation is being performed, a gate voltage Vg 3 is provided to the gate 111 , a drain voltage Vd 3 is provided to the node 150 , and the source voltage Vs 3 is provided to the source 113 . In this embodiment, the gate voltage Vg 3 is equal to the gate voltage Vg 1 , the drain voltage Vd 3 is higher than the drain voltage Vd 2 , and the source voltage is equal to the grounding voltage GND.

After the performance of the second verification operation, it is determined whether the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 (step S 380 A). If the resistance value of the variable resistor 130 is less than the pre-determine value PV 1 , a reset operation is performed (step S 330 A) such that the resistance value of the variable resistor 130 is at a high value. In other embodiments, the reset operation can be omitted if the resistance value of the variable resistor 130 is not required to be set to a high value.

If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 1 , the drain voltage Vd 3 is increased (step S 390 A) and then step S 380 A is executed to determine whether the resistance value of the variable resistor 130 is not less than the pre-determined value PV 1 . If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 1 , the drain voltage Vd 3 is increased until the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 . In this embodiment, the drain voltage Vd 3 is gradually increased.

FIG. 3B is a schematic diagram of another exemplary embodiment of the resistive memory. FIG. 3B is similar to FIG. 3A except for steps S 370 B, S 380 B and S 390 B. Since steps S 310 A˜S 360 A and S 310 B˜S 360 B have the same principle, descriptions of step S 310 B˜S 360 B are omitted for brevity.

In step S 370 B, a second verification operation is performed. A gate voltage Vg 3 is provided to the gate 111 . A drain voltage Vd 3 is provided to the node 150 . A source voltage Vs 3 is provided to the source 113 . In this embodiment, the gate voltage Vg 3 is higher than the gate voltage Vg 1 , the drain voltage Vd 3 is equal to the grounding voltage GND, and the source voltage Vs 3 is higher than the source voltage Vs 2 .

Next, it is determined whether the resistance value of the variable resistor 130 is less than a pre-determined value PV 3 (step S 380 B). If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 3 , the source voltage Vs 3 is increased (step S 390 B) and then step S 380 B is executed to again determine whether the resistance value of the variable resistor 130 is less than the pre-determined value PV 3 until the resistance value of the variable resistor 130 is less than the pre-determined value PV 3 . In this embodiment, the source voltage Vs 3 is gradually increased to make the resistance value of the variable resistor 130 to be less than the pre-determined value PV 3 . In one embodiment, the pre-determined value PV 3 is equal to or higher than the pre-determined value PV 1 .

Assuming the pre-determined value PV 3 is equal to the pre-determined value PV 1 . When the resistance value of the variable resistor 130 is less than the pre-determined value PV 3 , it represents that a setting operation is finished for the resistive memory 100 . In one embodiment, after setting the resistive memory 100 , a reset operation is performed for the resistive memory 100 (step S 330 B). In other embodiments, if the reset operation is not required for the resistive memory 100 , step 330 B is omitted.

In addition, assuming the pre-determined value PV 3 is higher than the pre-determined value PV 1 . Referring to FIG. 3C , a third verification operation is performed (step S 381 C). When the third verification operation is being performed, a gate voltage Vg 4 is provided to the gate 111 , a drain voltage Vd 4 is provided to the node 150 and a source voltage Vs 4 is provided to the source 113 . The gate voltage Vg 4 is equal to the gate voltage Vg 1 . The drain voltage Vd 4 is higher than the drain voltage Vd 2 . The source voltage Vs 4 is equal to the grounding voltage.

As shown in FIG. 3C , after step S 381 C, it is determined whether the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 (step S 382 C). If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 1 , the source voltage Vs 4 is increased (step S 391 C) until the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 . If the resistance value of the variable resistor 130 is less than the pre-determined value PV 1 , it represents that a setting operation for the resistive memory 100 is finished. Thus, a reset operation can be executed for the resistive memory 100 . However, the reset operation can be omitted if the resistive memory 100 is not required to be reset.

FIG. 3D is a schematic diagram of another exemplary embodiment of the resistive memory. FIG. 3D is similar to FIG. 3A except for steps S 340 D˜S 360 C. Since steps S 310 A˜S 330 A and S 310 D˜S 330 D have the same principle, descriptions of step S 310 D˜S 330 D are omitted for brevity.

In step S 340 D, a first verification operation is performed. A gate voltage Vg 2 is provided to the gate 111 . A drain voltage Vd 2 is provided to the node 150 . A source voltage Vs 2 is provided to the source 113 . In this embodiment, the gate voltage Vg 2 is equal to the gate voltage Vg 1 , the drain voltage Vd 2 is less than the drain voltage Vd 1 and the source voltage Vs 2 is equal to the grounding voltage GND.

Then, it is determined whether the resistance value of the variable resistor 130 is less than the pre-determined value PV 2 (step S 350 D). If the resistance value of the variable resistor 130 is less than the pre-determined value PV 2 , a reset operation is performed (step S 330 D) to reset the resistance value of the variable resistor 130 from a low value to a high value. In some embodiments, step S 330 D can be omitted.

If the resistance value of the variable resistor 130 is not less than the pre-determined value PV 2 , the drain voltage Vd 2 is increased (step S 360 D) and then step S 350 D is performed to again and again determine whether the resistance value of the variable resistor 130 is less than the pre-determined value PV 2 until the resistance value of the variable resistor 130 is less than the pre-determined value PV 2 . In one embodiment, the pre-determined value PV 2 is equal to the pre-determined value PV 1 .

When the first and the second verification operations are performed, the resistance value of the resistive memory can be set to a low value to compensate for the aging issue. In addition, the gate voltage Vg, the drain voltage Vd and the source voltage Vs are controlled such that the resistance value of the resistive memory is set to a low value and only one verification operation is performed.

While the disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.