Inductance-capacitance (LC) oscillator

This application claims the priority benefit of Taiwan application serial no. 100123881, filed on Jul. 6, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

1. Field of the Disclosure

The disclosure relates to an oscillator, more particularly, the disclosure relates to an inductance-capacitance (LC) oscillator.

2. Description of Related Art

As demands for transmission speed of data of a modern communication system are increased, a transceiver has to provide better transmission quality and wider bandwidth, so that an operating frequency and the bandwidth of the transceiver are required to be increased. Moreover, an oscillator (OSC) is highly related to phase noise in a phase-locked loop (PLL), which is also a critical circuit in the wireless communication system, and determines the transmission quality of the transceiver. The commonly used oscillators include ring oscillators and inductance-capacitance (LC) oscillators. Although the ring oscillator has wide bandwidth and low area, it has high dc power consumption and high phase noise, so that the LC oscillator is generally used.

An exemplary embodiment of the disclosure provides an inductance-capacitance (LC) oscillator including a first varactor cell, a first transistor, a second transistor and a first pair of differential transformers. The first varactor cell is used for providing a first variable capacitance to tune the frequency of a first differential oscillation signal generated by the LC oscillator, and outputting the first differential oscillation signal. The first transistor is coupled between a core dc supply voltage and a first terminal of the first varactor cell. The second transistor is coupled between a ground potential and a second terminal of the first varactor cell. The first pair of differential transformers is connected in cascade with the first transistor and the second transistor between the core dc supply voltage and the ground potential, and is used for increasing the output swing of the first differential oscillation signal, and making a current flowing through the first transistor to be reused by the second transistor.

Another exemplary embodiment of the disclosure provides a method for generating a differential oscillation signal by using an LC oscillator, which adopts both a current reuse manner and a transformer feedback manner.

Another exemplary embodiment of the disclosure provides a method for generating M differential oscillation signals with N phases by using an LC oscillator, which adopts a current reuse manner, a transformer feedback manner and a cascade coupling manner at the same time, where N and M are positive integers, and N=2M.

In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic of an inductance-capacitance (LC) oscillator 10 according to an exemplary embodiment of the disclosure.

FIG. 2 is a schematic of an LC oscillator 20 according to another exemplary embodiment of the disclosure.

Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic of an inductance-capacitance (LC) oscillator 10 according to an exemplary embodiment of the disclosure. Referring to FIG. 1 , the LC oscillator 10 includes a varactor cell 101 , transistors M 1 and M 2 , a pair of differential transformers T and an output buffer unit 103 .

In the present exemplary embodiment, the varactor cell 101 is used for providing a variable capacitance to adjust/tune the frequency of a differential oscillation signal (for example, a first oscillation signal OUT+ and a second oscillation signal OUT−) generated by the LC oscillator 10 , and outputting the differential oscillation signal (OUT+, OUT−).

In detail, the varactor cell 101 may include two varactors C V1 and C V2 . First ends of the varactors C vi and C V2 receive a varactor control voltage V CTRL through a resistor R, and second ends of the varactors C V1 and C V2 are respectively served as a first terminal and a second terminal of the varactor cell 101 , and are respectively coupled to the drains of the transistors M 1 and M 2 .

In the present exemplary embodiment, the second ends of the varactors C V1 and C V2 are used for outputting the differential oscillation signal (OUT+, OUT−). Moreover, the varactor cell 101 may further include (fixed) capacitors C 1 and C 2 . First ends of the capacitors C 1 and C 2 are respectively coupled to the second ends of the varactors C V1 and C V2 , and second ends of the capacitors C 1 and C 2 are coupled to a ground potential. Basically, the capacitance provided by the varactor cell 101 can be adjusted in response to the varactor control voltage V CTRL , so as to change the frequency of the differential oscillation signal (OUT+, OUT−) generated by the LC oscillator 10 .

The transistor M 1 can be implemented by a PMOS transistor, so that the transistor M 1 is referred to as the PMOS transistor M 1 . The PMOS transistor M 1 is coupled between the core dc supply voltage V CORE and the first terminal of the varactor cell 101 . Moreover, the transistor M 2 can be implemented by an NMOS transistor, so that the transistor M 2 is referred to as the NMOS transistor M 2 . The NMOS transistor M 2 is coupled between the ground potential and the second terminal of the varactor cell 101 .

The pair of differential transformers T is connected in cascade with the PMOS transistor M 1 and the NMOS transistor M 2 between the core dc supply voltage WORE and the ground potential, and is used for increasing the output swing (amplitude) of the differential oscillation signal (OUT+, OUT−), and making a current flowing through the PMOS transistor M 1 to be reused by the NMOS transistor M 2 (i.e. current reuse).

In detail, the pair of differential transformers T includes two transformers T 1 and T 2 . A secondary side V s1 of the transformer T 1 is coupled between the core dc supply voltage V CORE and the source of the PMOS transistor M 1 . A primary side V d2 of the transformer T 2 and a primary side V d1 of the transformer T 1 are connected in cascade between a drain of the PMOS transistor M 1 and the drain of the NMOS transistor M 2 , and a secondary side V s2 of the transformer T 2 is coupled between the source of the NMOS transistor M 2 and the ground potential. Moreover, the gate of the PMOS transistor M 1 is coupled to the drain of the NMOS transistor M 2 , and the gate of the NMOS transistor M 2 is coupled to the drain of the PMOS transistor M 1 .

In the present exemplary embodiment, an equivalent inductor of the transformers T 1 and T 2 and an equivalent capacitor of the varactor cell 101 may be formed as a resonator of the LC oscillator 10 . Moreover, the PMOS transistor M 1 and the NMOS transistor M 2 can provide negative resistance through the cross-coupling pair, so as to compensate the loss of the resonator of the LC oscillator 10 . In detail, the negative resistance provided by the PMOS transistor M 1 and the NMOS transistor M 2 is used to counteract a parasitic resistance of the resonator of the LC oscillator 10 , so as to maintain stable oscillation of the LC oscillator 10 .

On the other hand, under a feedback action of the transformers T 1 and T 2 , the voltages on the drain and source of each of the PMOS transistor M 1 and the NMOS transistor M 2 may have the same phase. In this way, the feedback action of the transformers T 1 and T 2 can effectively enhance the output swing of the differential oscillation signal (OUT+, OUT−), which not only avails the LC oscillator 10 to be operated under a lower core dc supply voltage V CORE , but also avails improving the output power of the LC oscillator 10 and reducing the phase noise of the LC oscillator 10 . From the measurement, the output power of the LC oscillator 10 can be greater than −20 dBm, and in case of a offset frequency of 1 MHz, the phase noise of the LC oscillator 10 can be smaller than −109 dBc/Hz, though the disclosure is not limited thereto.

Moreover, in order to maintain/increase the signal quality of the differential oscillation signal (OUT+, OUT−) for providing to the related circuit for utilization, in the present exemplary embodiment, the output buffer unit 103 is coupled to the varactor cell 101 , and used for receiving and boosting the differential oscillation signal (OUT+, OUT−), namely, the buffered first oscillation signal OUT+′ and the buffered second oscillation signal OUT−′.

In detail, the output buffer unit 103 may include transistors M 3 and M 4 , a differential inductor L BUF , and two capacitors C BUF1 and C BUF2 . The transistors M 3 and M 4 can all be implemented by NMOS transistors, so that the transistors M 3 and M 4 are referred to as NMOS transistors M 3 and M 4 . The gate of the NMOS transistor M 3 is coupled to the second end of the varactor C V2 , and the source of the NMOS transistor M 3 is coupled to the ground potential. The gate of the NMOS transistor M 4 is coupled to the second end of the varactor C V1 , and a source of the NMOS transistor M 4 is coupled to the ground potential.

The differential inductor L BUF is an electronic device having three terminals. A first terminal of the differential inductor L BUF is coupled to a direct current (DC) bias voltage V BUF , a second terminal of the differential inductor L BUF is coupled to the drain of the NMOS transistor M 3 , and a third terminal of the differential inductor L BUF is coupled to the drain of the NMOS transistor M 4 . Moreover, first ends of the capacitors C BUF1 and C BUF2 are respectively coupled to the drains of the NMOS transistors M 3 and M 4 , and second ends of the capacitors C BUF1 and C BUF2 respectively output the buffered first oscillation signal OUT+′ and second oscillation signal OUT−′. In this way, the signal quality of the differential oscillation signal (OUT+, OUT−) can be increased and provided to the related circuit for utilization.

On the other hand, FIG. 2 is a circuit diagram of an LC oscillator 20 according to another exemplary embodiment of the disclosure. Referring to FIG. 2 , compared to the LC oscillator 10 of FIG. 1 that has two phase outputs)(OUT+′(0°), OUT−′(180°)), the LC oscillator 20 of the present exemplary embodiment has four phase outputs ((OUT+′(0°), OUT−′(180°), OUT++′(270°), OUT−−′(90°)).

In detail, compared to the LC oscillator 10 , the LC oscillator 20 further includes a varactor cell 101 ′, transistors, M 5 , M 6 , M 7 , M 8 , M 11 and M 12 , a pair of differential transformers T′, resistors R′, R G1 , R G2 , R G3 and R G4 , capacitors C 3 -C 6 and an output buffer unit 103 ′. The same referential numbers in FIG. 1 and FIG. 2 denote the similar coupling relations and functions, so that details thereof are not repeated. Therefore, only the differences there between are described below.

In the present exemplary embodiment, the varactor cell 101 ′ is used for providing the variable capacitance to adjust/tune the frequency of a differential oscillation signal (for example, a third oscillation signal OUT++ and a fourth oscillation signal OUT−−) generated by the LC oscillator 20 , and outputting the differential oscillation signal (OUT++, OUT−−). In detail, the varactor cell 101 ′ may include two varactors C V1 ′ and C V2 ′. First ends of the varactors C V1 ′ and C V2 ′ receive the varactor control voltage V CTRL through a resistor R′, and second ends of the varactors C V1 ′ and C V2 ′ are respectively served as a first terminal and a second terminal of the varactor cell 101 ′, and are respectively coupled to drains of the transistors M 7 and M 8 .

In the present exemplary embodiment, the second ends of the varactors C V1 ′ and C V2 ′ are used for outputting the differential oscillation signal (OUT++, OUT−−). Moreover, the varactor cell 101 ′ may further include (fixed) capacitors C 1 ′ and C 2 ′. First ends of the capacitors C 1 ′ and C 2 ′ are respectively coupled to the second ends of the varactors C V1 ′ and C V2 ′, and second ends of the capacitors C 1 ′ and C 2 ′ are coupled to the ground potential. Similarly, the capacitance provided by the varactor cell 101 ′ can by adjusted in response to the varactor control voltage V CTRL , so as to change the frequency of the differential oscillation signal (OUT++, OUT−−) generated by the LC oscillator 20 .

Moreover, the transistor M 7 can be implemented by a PMOS transistor, so that the transistor M 7 is referred to as the PMOS transistor M 7 . The PMOS transistor M 7 is coupled between the core dc supply voltage V CORE and the first terminal of the varactor cell 101 ′. On the other hand, the transistor M 8 can be implemented by an NMOS transistor, so that the transistor M 8 is referred to as the NMOS transistor M 8 . The NMOS transistor M 8 is coupled between the ground potential and the second terminal of the varactor cell 101 ′.

The pair of differential transformers T′ is connected in cascade with the PMOS transistor M 7 and the NMOS transistor M 8 between the core dc supply voltage V CORE and the ground potential, and is used for increasing the output swing of the differential oscillation signal (OUT++, OUT−−), and making a current flowing through the PMOS transistor M 7 to be reused by the NMOS transistor M 8 (i.e. current reuse).

In detail, the pair of differential transformers T′ includes two transformers T 3 and T 4 . A secondary side V s3 of the transformer T 3 is coupled between the core dc supply voltage V CORE and the source of the PMOS transistor M 7 . A primary side V d4 of the transformer T 4 and a primary side V d3 of the transformer T 3 are connected in cascade between the drain of the PMOS transistor M 7 and the drain of the NMOS transistor M 8 , and a secondary side V s4 of the transformer T 4 is coupled between the source of the NMOS transistor M 8 and the ground potential. Moreover, the gate of the PMOS transistor M 7 is coupled to the drain of the NMOS transistor M 8 , and a gate of the NMOS transistor M 8 is coupled to the drain of the PMOS transistor M 7 .

On the other hand, the transistor M 5 can be implemented by a PMOS transistor, so that the transistor M 5 is a referred to as the PMOS transistor M 5 . The PMOS transistor M 5 is coupled between a first end of the secondary side V s1 of the transformer T 1 and the source of the PMOS transistor M 1 , where the source of the PMOS transistor M 5 is coupled to the first end of the secondary side V s1 of the transformer T 1 , the drain of the PMOS transistor M 5 is coupled to the source of the PMOS transistor M 1 , and a second end of the secondary side V s1 of the transformer T 1 is coupled to the core dc supply voltage V CORE . A first end of the resistor R G1 is used for receiving a gate control voltage V G , and a second end of the resistor R G1 is coupled to a gate of the PMOS transistor M 5 . A first end of the capacitor C 3 is coupled to the gate of the PMOS transistor M 5 , and a second end of the capacitor C 3 is coupled to a node N 1 and the second end of the varactor C V1 ′.

The transistor M 6 can be implemented by an NMOS transistor, so that the transistor M 6 is a referred to as the NMOS transistor M 6 . The NMOS transistor M 6 is coupled between a first end of the secondary side V s2 of the transformer T 2 and the source of the NMOS transistor M 2 , where the source of the NMOS transistor M 6 is coupled to the first end of the secondary side V s2 of the transformer T 2 , the drain of the NMOS transistor M 6 is coupled to the source of the NMOS transistor M 2 , and a second end of the secondary side V s2 of the transformer T 2 is coupled to the ground potential. A first end of the resistor R G2 is used for receiving the gate control voltage V G , and a second end of the resistor R G2 is coupled to a gate of the NMOS transistor M 6 . A first end of the capacitor C 4 is coupled to the gate of the NMOS transistor M 6 , and a second end of the capacitor C 4 is coupled to a node N 2 and the second end of the varactor C V2 ′.

The transistor M 11 can be implemented by a PMOS transistor, so that the transistor M 11 is a referred to as the PMOS transistor M 11 . The PMOS transistor M 11 is coupled between a first end of the secondary side V s3 of the transformer T 3 and the source of the PMOS transistor M 7 , where the source of the PMOS transistor M 11 is coupled to the first end of the secondary side V s3 of the transformer T 3 , the drain of the PMOS transistor M 11 is coupled to the source of the PMOS transistor M 7 , and a second end of the secondary side V s3 of the transformer T 3 is coupled to the core dc supply voltage V CORE . A first end of the resistor R G3 is used for receiving the gate control voltage V G , and a second end of the resistor R G3 is coupled to the gate of the PMOS transistor M 11 . A first end of the capacitor C 5 is coupled to the gate of the PMOS transistor M 11 , and a second end of the capacitor C 5 is coupled to a node N 3 and the second end of the varactor C V2 .

The transistor M 12 can be implemented by an NMOS transistor, so that the transistor M 12 is a referred to as the NMOS transistor M 12 . The NMOS transistor M 12 is coupled between a first end of the secondary side V s4 of the transformer T 4 and the source of the NMOS transistor M 8 , where a source of the NMOS transistor M 12 is coupled to the first end of the secondary side V s4 of the transformer T 4 , a drain of the NMOS transistor M 12 is coupled to the source of the NMOS transistor M 8 , and a second end of the secondary side V s4 of the transformer T 4 is coupled to the ground potential. A first end of the resistor R G4 is used for receiving the gate control voltage V G , and a second end of the resistor R G4 is coupled to a gate of the NMOS transistor M 12 . A first end of the capacitor C 6 is coupled to the gate of the NMOS transistor M 12 , and a second end of the capacitor C 6 is coupled to a node N 4 and the second end of the varactor C V1 .

In this way, a method and principle for the LC oscillator 20 generating the differential oscillation signal (OUT++, OUT−−) are similar to that for the LC oscillator 10 generating the differential oscillation signal (OUT+, OUT−), so that details thereof are not repeated. Similarly, in order to maintain/increase the signal quality of the differential oscillation signal (OUT++, OUT−−) for providing to the related circuit for utilization, in the present exemplary embodiment, the output buffer unit 103 ′ is coupled to the varactor cell 101 ′, and used for receiving and boosting the differential oscillation signal (OUT++, OUT−−), namely, the buffered third oscillation signal OUT++′ and the buffered fourth oscillation signal OUT−−′.

In detail, the output buffer unit 103 ′ may include transistors M 9 and M 10 , a differential inductor L BUF ′, and two capacitors C BUF1 ′ and C BUF2 ′. The transistors M 9 and M 10 can all be implemented by NMOS transistors, so that the transistors M 9 and M 10 are referred to as NMOS transistors M 9 and M 10 . The gate of the NMOS transistor M 9 is coupled to the second end of the varactor C V2 ′, and the source of the NMOS transistor M 9 is coupled to the ground potential. The gate of the NMOS transistor M 10 is coupled to the second end of the varactor C V1 ′, and a source of the NMOS transistor M 10 is coupled to the ground potential.

The differential inductor L BUF ′ is an electronic device having three terminals. A first terminal of the differential inductor L BUF ′ is coupled to the DC bias voltage V BUF , a second terminal of the differential inductor L BUF ′ is coupled to the drain of the NMOS transistor M 9 , and a third terminal of the differential inductor L BUF ′ is coupled to the drain of the NMOS transistor M 10 . Moreover, first ends of the capacitors C BUF1 ′ and C BUF2 ′ are respectively coupled to the drains of the NMOS transistors M 9 and M 10 , and second ends of the capacitors C BUF1 ′ and C BUF2 ′ respectively output the buffered third oscillation signal OUT++′ and fourth oscillation signal OUT−−′. In this way, the signal quality of the differential oscillation signal (OUT++, OUT−−) is increased and provided to the related circuit for utilization.

It should be noticed that due to the added part of FIG. 2 , the LC oscillator 20 has four phase outputs)((OUT+′(0°), OUT−′(180°), OUT++′(270°), OUT−−′(90°)). In other words, phase differences between the first oscillation signal OUT+ and the oscillation signals OUT−, OUT++ and OUT−− are respectively 180°, 270° and 90°. Therefore, the LC oscillator 20 having four phase outputs can be applied to a direct-conversion transceiver system, though the disclosure is not limited thereto.

Of course, according to the descriptions of the exemplary embodiments of FIG. 1 and FIG. 2 , those skilled in the art can deduce an implementation method of the LC oscillator capable of generating M differential oscillation signals with N phases (N and M are positive integer and N=2M) according to a current reuse manner (i.e. cascade connection of the PMOS transistor M 1 /M 7 and the NMOS transistor M 2 /M 8 ), a transformer feedback manner (i.e. a feedback effect/action formed by the transformers T 1 /T 3 and T 2 /T 4 ) and a cascade coupling manner (i.e. adding of the PMOS transistor M 5 /M 11 and the NMOS transistor M 6 /M 12 ), and details thereof are not repeated herein.

In summary, the LC oscillator 10 / 20 of the disclosure simultaneously uses the current reuse architecture (i.e. cascade connection of the PMOS transistor M 1 /M 7 and the NMOS transistor M 2 /M 8 ) and the transformer feedback technique (i.e. the feedback effect formed by the transformers T 1 /T 3 and T 2 /T 4 ) to achieve both low dc power consumption and low phase noise. Therefore, the LC oscillator 10 / 20 of the disclosure can be applied to a transceiver system of a wire or wireless communication device.

Moreover, since the LC oscillator 10 / 20 of the disclosure has low phase noise, it can be applied to various systems, for example, a multi-phase clock generating circuit, a vehicle radar system, and a microwave and millimeter-wave circuit system, etc., and the circuit configuration of the LC oscillator 10 / 20 can be implemented through a low cost silicon-based process, so that practicability thereof is improved.

Besides, any oscillation circuit structure that simultaneously uses the current reuse manner/architecture and the transformer feedback manner/technique in the single oscillator to implement the oscillation is considered to be within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.