Serial port connection circuit and server

1. Technical Field

The present disclosure relates to serial port connection circuits, and particularly to a serial port connection circuit with high compatibility and a server using the serial port connection circuit.

2. Description of Related Art

Serial ports are widely used in electronic devices, such as servers. For example, baseboard management controllers (BMCs) and input/output (I/O) chips of servers can be electrically connected to other electronic devices via serial ports. Serial ports for BMCs are mostly incompatible with serial ports for I/O chips. Therefore, many servers may need various serial ports for the BMCs and the I/O chips, respectively, which may adversely affect miniaturization of the servers and increase cost of the servers.

Therefore, there is room for improvement within the art.

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the various drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the figures.

FIG. 1 is a block diagram of a server, according to an exemplary embodiment.

FIG. 2 is a circuit diagram of the server shown in FIG. 1 .

FIG. 1 and FIG. 2 show a server 100 according to an exemplary embodiment. The server 100 includes a baseboard management controller (BMC) 10 , an input/output (I/O) chip 20 , a serial port connection circuit 30 , and a serial port 40 . Both the BMC 10 and the I/O chip 20 are electrically connected to the serial port 40 via the serial port connection circuit 30 . Thus, the serial port connection circuit 30 can selectively connect the BMC 10 or the I/O chip 20 to the serial port 40 , such that the BMC 10 and the I/O chip 20 can be selectively connected to other electronic devices via the serial port 40 .

The BMC 10 can be a typical BMC used in electronic devices. The BMC 10 includes a first enabling pin EN 1 , a second enabling pin EN 2 , and a plurality of data transmission pins. In this embodiment, the BMC 10 includes eight data transceiving pins C 1 -C 8 . The I/O chip 20 can be a typical I/O chip used in electronic devices. The I/O chip 20 also includes a plurality of data transceiving pins. In this embodiment, the I/O chip 20 includes eight data transceiving pins D 1 -D 8 .

The serial port connection circuit 30 includes a first data transmission unit U 1 , a second data transmission unit U 2 , a third data transmission unit U 3 , and a fourth data transmission unit U 4 , which are all multiple selectors. In this embodiment, each of the four data transmission units U 1 , U 2 , U 3 , U 4 includes four first data transmission pins 1 A- 4 A, four second data transmission pins 1 B 1 - 4 B 1 , four third data transmission pins 1 B 2 - 4 B 2 , a first selection control pin S, and a second selection control pin OE. The first selection control pins S of the first and second data transmission units U 1 , U 2 are both electrically connected to the first enabling pin EN 1 . The first selection control pins S of the third and fourth data transmission units U 3 , U 4 are both electrically connected to the second enabling pin EN 2 . The second selection control pins OE of the data transmission units U 1 , U 2 , U 3 , U 4 are all grounded.

The data transceiving pins C 1 -C 4 of the BMC 10 are correspondingly electrically connected to the first data transmission pins 1 A- 4 A of the first data transmission unit U 1 . The data transceiving pins C 5 -C 8 of the BMC 10 are correspondingly electrically connected to the second data transmission pins 1 B 1 - 4 B 1 of the fourth data transmission unit U 4 . The data transceiving pins D 1 -D 4 of the I/O chip 20 are correspondingly electrically connected to the first data transmission pins 1 A- 4 A of the second data transmission unit U 2 . The data transceiving pins D 5 -D 8 of the I/O chip 20 are correspondingly electrically connected to the third data transmission pins 1 B 2 - 4 B 2 of the fourth data transmission unit U 4 . The second data transmission pins 1 B 1 - 4 B 1 of the first data transmission unit U 1 are correspondingly electrically connected to the second data transmission pins 1 B 1 - 4 B 1 of the second data transmission unit U 2 . The third data transmission pins 1 B 2 - 4 B 2 of the first data transmission unit U 1 are correspondingly electrically connected to the second data transmission pins 1 B 1 - 4 B 1 of the third data transmission unit U 3 . The third data transmission pins 1 B 2 - 4 B 2 of the second data transmission unit U 2 are correspondingly electrically connected to the third data transmission pins 1 B 2 - 4 B 2 of the third data transmission unit U 3 .

The serial port connection circuit 30 further includes a voltage regulating unit 31 , such as an adapter or other voltage converters. The first data transmission pins 1 A- 4 A of the third data transmission unit U 3 and the first data transmission pins 1 A- 4 A of the fourth data transmission unit U 4 are all electrically connected to the voltage regulating unit 31 , and the voltage regulating unit 31 is electrically connected to the serial port 40 .

In this embodiment, in each of the data transmission units U 1 , U 2 , U 3 , U 4 , the first data transmission pins 1 A- 4 A are selectively connected to the second data transmission pins 1 B 1 - 4 B 1 or the third data transmission pins 1 B 2 - 4 B 2 according to logic statuses of the first selection control pin S and the second selection control pin OE. In particular, when both the first selection control pin S and the second selection control pin OE are at logic 0, the data transmission unit allows data transmission between the first data transmission pins 1 A- 4 A and the second data transmission pins 1 B 1 - 4 B 1 . When the first selection control pin S is at logic 1 and the second selection control pin OE is at logic 0, the data transmission unit allows data transmission between the first data transmission pins 1 A- 4 A and the third data transmission pins 1 B 2 - 4 B 2 . When the first selection control pin S is at logic 0 and the second selection control pin OE is at logic 1, or both the first selection control pin S and the second selection control pin OE are at logic 1, the data transmission unit prohibits through data transmission.

In use, when the BMC 10 needs to be electrically connected to other electronic devices (e.g., debug devices) via the serial port connection circuit 30 and the serial port 40 , the first enabling pin EN 1 is set at logic 1, and the second enabling pin EN 2 is set at logic 0. Thus, the first selection control pins S of the first and second data transmission units U 1 , U 2 are set at logic 1, and the first selection control pins S of the third and fourth data transmission units U 3 , U 4 are set at logic 0. Because the second selection control pins OE of all of the data transmission units U 1 , U 2 , U 3 , U 4 are all grounded, that is, always set at logic 0, the first and second data transmission units U 1 , U 2 respectively allow data transmission between their first data transmission pins 1 A- 4 A and their third data transmission pins 1 B 2 - 4 B 2 , and the third and fourth data transmission units U 3 , U 4 respectively allow data transmission between their first data transmission pins 1 A- 4 A and their second data transmission pins 1 B 1 - 4 B 1 . In this way, the data transceiving pins C 1 -C 4 of the BMC 10 can transmit data to and receive data from the serial port 40 via the first data transmission unit U 1 and the third data transmission unit U 3 connected in series, and the data transceiving pins C 5 -C 8 of the BMC 10 can transmit data to and receive data from the serial port 40 via the fourth data transmission unit U 4 . The voltage regulating unit 31 can regulate voltages of the data transmitted between the BMC 10 and the serial port 40 . At the same time, data transmission between the I/O chip 20 and the serial port 40 and data transmission between the I/O chip 20 and the BMC 10 are both prohibited.

When the I/O chip 20 needs to be electrically connected to other electronic devices (e.g., external devices such as mice, keypads, and printers) via the serial port connection circuit 30 and the serial port 40 , both the first enabling pin EN 1 and the second enabling pin EN 2 are set at logic 1. Thus, the first selection control pins S of the data transmission units U 1 , U 2 , U 3 , U 4 are all set at logic 1. Because the second selection control pins OE of the data transmission units U 1 , U 2 , U 3 , U 4 are all always set at logic 0, each of the data transmission units U 1 , U 2 , U 3 , U 4 allows data transmission between the first data transmission pins 1 A- 4 A and the third data transmission pins 1 B 2 - 4 B 2 . In this way, the data transceiving pins D 1 -D 4 of the I/O chip 20 can transmit data to and receive data from the serial port 40 via the second data transmission unit U 2 and the third data transmission unit U 3 connected in series, and the data transceiving pins D 5 -D 8 of the I/O chip 20 can transmit data to and receive data from the serial port 40 via the fourth data transmission unit U 4 . The voltage regulating unit 31 can regulate voltages of the data transmitted between the I/O chip 20 and the serial port 40 . At the same time, data transmission between the BMC 10 and the serial port 40 and data transmission between the BMC 10 and the I/O chip 20 are both prohibited.

Furthermore, when the first enabling pin EN 1 is set at logic 0, the data transceiving pins C 1 -C 4 of the BMC 10 can transmit data to and receive data from the data transceiving pins D 1 -D 4 of the I/O chip 20 via the first data transmission pins 1 A- 4 A and the second data transmission pins 1 B 1 - 4 B 1 of the first data transmission unit U 1 , and the second data transmission pins 1 B 1 - 4 B 1 and the first data transmission pins 1 A- 4 A of the second data transmission unit U 2 . In this way, the BMC 10 and the I/O chip 20 can be electrically connected to each other and cooperatively establish a Serial over LAN (SoL) function.

The present disclosure enables the BMC 10 and the I/O chip 20 of the server 100 to be selectively connected to other electronic devices via the same serial port 40 . Compared with common servers, the server 100 does not need different serial ports configured for respectively connecting the BMC 10 and the I/O chip 20 to other electronic devices, and can have less serial ports. Thus, the present disclosure can achieve further miniaturization and conserve cost.

It is to be further understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, together with details of structures and functions of various embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.