Scan driver and organic light emitting display using the same

This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0064435, filed on Jun. 30, 2011, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

1. Field

Embodiments relate to a scan driver and an organic light emitting display using the same.

2. Description of the Related Art

Various flat panel displays (FPD) capable of reducing weight and volume have been developed. The FPDs include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display.

Embodiments may be directed to a scan driver and an organic light emitting display.

According to an embodiment, there may be a scan driver, including a plurality of stages for simultaneously outputting first scan signals in a simultaneous driving period and for progressively outputting second scan signals in a progressive driving period. Each of the stages includes a first signal processing unit coupled to an input terminal, a first clock terminal, a third clock terminal, an auxiliary terminal, a first power source terminal, and a second power source terminal to output a first output signal and a second output signal and a second signal processing unit coupled to a second clock terminal and the first power source terminal to receive the first output signal and the second output signal and to output a first scan signal and a second scan signal to an output terminal.

The first signal processing unit may include a first transistor whose gate electrode is coupled to the input terminal, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to a first node, a second transistor whose gate electrode is coupled to the first clock terminal, whose first electrode is coupled to the input terminal, and whose second electrode is coupled to a third node, a third transistor whose gate electrode is coupled to the first node, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the third node, a fourth transistor whose gate electrode is coupled to the second power source terminal, whose first electrode is coupled to the third node, and whose second electrode is coupled to a second node, a fifth transistor whose gate electrode is coupled to the auxiliary terminal, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the first node, a sixth transistor whose gate electrode is coupled to the third clock terminal, whose first electrode is coupled to the first node, and whose second electrode is coupled to the second power source terminal, and a seventh transistor whose gate electrode is coupled to the auxiliary terminal, whose first electrode is coupled to the second node, and whose second electrode is coupled to the auxiliary terminal.

The first output signal may be output from the first node and the second output signal may be output from the second node.

The second signal processing unit may include an eighth transistor whose gate electrode is coupled to the first node, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the output terminal and a ninth transistor whose gate electrode is coupled to the second node, whose first electrode is coupled to the output terminal, and whose second electrode is coupled to the second clock terminal.

The second signal processing unit may further include a first capacitor coupled between the first node and the first power source terminal and a second capacitor coupled between the second node and the output terminal.

The first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth transistors may be PMOS transistors.

The output terminal includes an output terminal of an ith (i is a natural number) stage and the input terminal includes an input terminal of an (i+1)th stage, the output terminal of the ith stage being electrically coupled to the input terminal of the (i+1)th stage.

In the simultaneous driving period, supply of clock signals to the first clock terminal, the second clock terminal, and the third clock terminal may be maintained, an auxiliary signal may be supplied to the auxiliary terminal, and a second power source supplied to the second power source terminal may have a high level voltage.

In the progressive driving period, the clock signals may be progressively and repeatedly supplied to the first clock terminal, the second clock terminal, and the third clock terminal, supply of the auxiliary signal to the auxiliary terminal may be stopped, and the second power source supplied to the second power source terminal may have a low level voltage.

In an initializing period that exists between the simultaneous driving period and the progressive driving period, the clock signals are simultaneously supplied to the first clock terminal, the second clock terminal, and the third clock terminal, supply of the auxiliary signal to the auxiliary terminal is stopped, and the second power source supplied to the second power source terminal has the low level voltage.

According to another embodiment, there may be an organic light emitting display, including a pixel unit including pixels receiving first scan signals, second scan signals, and data signals, a scan driver including a plurality of stages for simultaneously outputting the first scan signals in a simultaneous driving period and for progressively outputting the second scan signals in a progressive driving period, and a data driver for supplying the data signals to the pixels. Each of the stages includes a first signal processing unit coupled to an input terminal, a first clock terminal, a third clock terminal, an auxiliary terminal, a first power source terminal, and a second power source terminal to output a first output signal and a second output signal and a second signal processing unit coupled to a second clock terminal and the first power source terminal to receive the first output signal and the second output signal and to output one of the first scan signals and one of the second scan signals to an output terminal.

The first signal processing unit may include a first transistor whose gate electrode is coupled to the input terminal, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to a first node, a second transistor whose gate electrode is coupled to the first clock terminal, whose first electrode is coupled to the input terminal, and whose second electrode is coupled to a third node, a third transistor whose gate electrode is coupled to the first node, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the third node, a fourth transistor whose gate electrode is coupled to the second power source terminal, whose first electrode is coupled to the third node, and whose second electrode is coupled to a second node, a fifth transistor whose gate electrode is coupled to the auxiliary terminal, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the first node, a sixth transistor whose gate electrode is coupled to the third clock terminal, whose first electrode is coupled to the first node, and whose second electrode is coupled to the second power source terminal, and a seventh transistor whose gate electrode is coupled to the auxiliary terminal, whose first electrode is coupled to the second node, and whose gate electrode is coupled to the auxiliary terminal.

The first output signal may be output from the first node and the second output signal is output from the second node.

The second signal processing unit may include an eighth transistor whose gate electrode is coupled to the first node, whose first electrode is coupled to the first power source terminal, and whose second electrode is coupled to the output terminal and a ninth transistor whose gate electrode is coupled to the second node, whose first electrode is coupled to the output terminal, and whose second electrode is coupled to the second clock terminal.

The second signal processing unit may further include a first capacitor coupled between the first node and the first power source terminal and a second capacitor coupled between the second node and the output terminal.

The first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth transistors may be PMOS transistors.

The output terminal includes an output terminal of an ith (i is a natural number) stage and the input terminal includes an input terminal of an (i+1)th stage, the output terminal of the ith stage being electrically coupled to the input terminal of the (i+1)th stage.

In the simultaneous driving period, supplies of clock signals to the first clock terminal, the second clock terminal, and the third clock terminal may be maintained, an auxiliary signal may be supplied to the auxiliary terminal, and a second power source supplied to the second power source terminal may have a high level voltage.

In the progressive driving period, clock signals may be progressively and repeatedly supplied to the first clock terminal, the second clock terminal, and the third clock terminal, supply of an auxiliary signal to the auxiliary terminal may be stopped, and a second power source supplied to the second power source terminal may have a low level voltage.

In an initializing period that exists between the simultaneous driving period and the progressive driving period, clock signals may be simultaneously supplied to the first clock terminal, the second clock terminal, and the third clock terminal, supply of an auxiliary signal to the auxiliary terminal may be stopped, and a second power source supplied to the second power source terminal may have a low level voltage.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

FIG. 1 is a view illustrating an organic light emitting display;

FIG. 2 is a view illustrating an organic light emitting display according to an exemplary embodiment;

FIG. 3 is a view illustrating the structures of the stages included in the scan driver of FIG. 2 ;

FIG. 4 is a view illustrating the circuit structures of the stages of FIG. 3 ;

FIG. 5 is a waveform chart illustrating the operations of the stages of FIG. 3 ;

FIG. 6 is a view illustrating other structures of the stages included in the scan driver of FIG. 2 ; and

FIG. 7 is a waveform chart illustrating the operations of the stages of FIG. 6 .

Korean Patent Application No. 10-2011-0064435, filed on Jun. 30, 2011, in the Korean Intellectual Property Office, and entitled: “Scan Driver and Organic Light Emitting Display Using the Same” is incorporated by reference herein in its entirety.

Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation.

Hereinafter, the scan driver and the organic light emitting display using the same will be described with reference to the embodiments and the drawings for describing the embodiments.

FIG. 2 is a view illustrating an organic light emitting display according to an exemplary embodiment.

Referring to FIG. 2 , the organic light emitting display according to the embodiment includes a pixel unit 120 including pixels 110 coupled to scan lines S 1 to Sn, data lines D 1 to Dm, a first power source ELVDD, and a second power source ELVSS, a scan driver 130 for supplying first scan signals and second scan signals to the pixels 110 , and a data driver 150 for supplying data signals to the pixels 110 through the data lines D 1 to Dm, and may further include a timing controller 160 for controlling the scan driver 130 and the data driver 150 .

The scan driver 130 generates the first scan signals and the second scan signals by the control of the timing controller 160 to simultaneously supply the generated first scan signals to the pixels 110 in a simultaneous driving period Pe and to progressively supply the generated second scan signals to the pixels 110 in a progressive driving period Ps.

Signals supplied to the pixels 110 in the simultaneous driving period Pe may be defined as the first scan signals and signals supplied to the pixels 110 in the progressive driving period Ps may be defined as the second scan signals. In addition, the first scan signals and the second scan signals may be realized by low level voltages.

The simultaneous driving period Pe and the progressive driving period Ps may progressively proceed in one frame period and an initializing period Pi may proceed between the simultaneous driving period Pe and the progressive driving period Ps.

In addition, in order to generate and supply the first scan signals and the second scan signals, a plurality of stages 2001 to 200 n are included.

The data driver 150 generates the data signals for determining the emission brightness components of the pixels 110 by the control of the timing controller 160 and supplies the generated data signals to the data lines D 1 to Dm.

Then, the data signals are supplied to the pixels 110 selected by the scan signals progressively supplied in the progressive driving period Ps and the pixels 110 charge the voltages corresponding to the data signals supplied thereto and emit light with the brightness components corresponding to the charged voltages.

In addition, the scan driver 130 may transmit the first scan signals and the second scan signals to the pixels 110 through the scan lines S 1 to Sn illustrated in FIG. 2 .

FIG. 3 is a view illustrating the structures of the stages included in the scan driver of FIG. 2 . In FIG. 3 , only a first stage 2001 , a second stage 2002 , a third stage 2003 , and a fourth stage 2004 are illustrated. The other stages 2005 to 200 n are omitted for convenience sake.

Referring to FIG. 3 , each of the stages 2001 to 200 n includes an input terminal IN, a first clock terminal CK 1 , a second clock terminal CK 2 , a third clock terminal CK 3 , an auxiliary terminal B_SUB, a first power source terminal B_VGH, a second power source terminal B_VGL, and each of output terminals OUT 1 to OUTn.

A start pulse FLM is supplied to the input terminal IN of the first stage 2001 and the input terminal IN of each of the other stages 2002 to 200 n is coupled to the output terminals of previous stages.

Therefore, the output terminal OUTi of an ith stage 200 i is electrically coupled to the input terminal IN of an (i+1)th stage 200 i +1 so that the signal output from the output terminal OUTi of the ith stage 200 i is supplied to a corresponding pixel 110 and is supplied to the input terminal IN of the (i+1)th stage 200 i +1.

A first power source VGH is supplied to the first power source terminal B_VGH of each of the stages 2001 to 200 n . A second power source VGL is supplied to the second power source terminal B_VGL of each of the stages 2001 to 200 n.

The first power source VGH uniformly maintains the voltage thereof in one frame period. The voltage of the second power source VGL varies in one frame period.

For example, the first power source VGH may uniformly maintain a voltage in a high level in one frame period. The second power source VGL may be set as a voltage in a high level in the simultaneous driving period Pe and may be set as a voltage in a low level in the initializing period Pi and the progressive driving period Ps.

Since clock signals must be progressively supplied to the first clock terminal CK 1 , the second clock terminal CK 2 , and the third clock terminal CK 3 of each of the stages 2001 to 200 n in the progressive driving period Ps, the first clock terminal CK 1 of the first stage 2001 is coupled to the first clock signal SCK 1 , the second clock terminal CK 2 of the first stage 2001 is coupled to the second clock signal SCK 2 , and the third clock terminal CK 3 of the first stage 2001 is coupled to the third clock signal SCK 3 .

In addition, the first clock terminal CK 1 of the second stage 2002 is coupled to the second clock signal SCK 2 , the second clock terminal CK 2 is coupled to the third clock signal SCK 3 , and the third clock terminal CK 3 is coupled to the first clock signal SCK 1 .

The first clock terminal CK 1 of the third stage 2003 is coupled to the third clock signal SCK 3 . The second clock terminal CK 2 of the third stage 2003 is coupled to the first clock signal SCK 1 . The third clock terminal CK 3 of the third stage 2003 is coupled to the second clock signal SCK 2 .

The first clock signal SCK 1 , the second clock signal SCK 2 , and the third clock signal SCK 3 are repeatedly supplied as illustrated in FIG. 5 . The second clock signal SCK 2 may be delayed from the first clock signal SCK 1 by one horizontal period 1 H and the third clock signal SCK 3 may be delayed from the second clock signal SCK 2 by one horizontal period 1 H.

FIG. 4 is a view illustrating the circuit structures of the stages of FIG. 3 . In FIG. 4 , for convenience sake, an ith (i is a natural number) stage and an (i+1)th stage will be illustrated.

Each of the stages 2001 to 200 n includes a first signal processing unit 310 and a second signal processing unit 320 . For convenience sake, the ith stage 200 i illustrated in FIG. 4 will be described.

The first signal processing unit 310 is coupled to the input terminal IN, the first clock terminal CK 1 , the third clock terminal CK 3 , the auxiliary terminal B_SUB, the first power source terminal B_VGH, and the second power source terminal B_VGL and outputs a first output signal Sout 1 and a second output signal Sout 2 .

The second signal processing unit 320 is coupled to the second clock terminal CK 2 and the first power source terminal B_VGH and receives the first output signal Sout 1 and the second output signal Sout 2 output from the first signal processing unit 310 to output the first scan signals and the second scan signals to the output terminal OUTi.

At this time, the first signal processing unit 310 includes a first transistor M 1 to a seventh transistor M 7 .

The gate electrode of the first transistor M 1 is coupled to the input terminal IN. The first electrode of the first transistor M 1 is coupled to the first power source terminal B_VGH. The second electrode of the first transistor M 1 is coupled to a first node N 1 . In addition, the first transistor M 1 is turned on when a scan signal is input from a previous stage to the input terminal IN to transmit the first power source VGH to the first node N 1 .

The gate electrode of the second transistor M 2 is coupled to the first clock terminal CK 1 . The first electrode of the second transistor M 2 is coupled to the input terminal IN. The second electrode of the second transistor is coupled to a third node N 3 . In addition, the second transistor M 2 is turned on when a clock signal is supplied to the first clock terminal CK 1 to transmit the voltage of the input terminal IN to the third node N 3 .

The gate electrode of the third transistor M 3 is coupled to the first node N 1 . The first electrode of the third transistor M 3 is coupled to the first power source terminal B_VGH. The second electrode of the third transistor M 3 is coupled to the third node N 3 . In addition, the turn on and off of the third transistor M 3 are controlled by the voltage of the first node N 1 . When the third transistor M 3 is turned on, the first power source VGH is transmitted to the third node N 3 .

The gate electrode of the fourth transistor M 4 is coupled to the second power source terminal B_VGL. The first electrode of the fourth transistor M 4 is coupled to the third node N 3 . The second electrode of the fourth transistor M 4 is coupled to a second node N 2 . In addition, the turn on and off of the fourth transistor M 4 are controlled by the second power source VGL. When the fourth transistor M 4 is turned on, the voltage of the third node N 3 is transmitted to the second node N 2 .

The gate electrode of the fifth transistor M 5 is coupled to the auxiliary terminal B_SUB. The first electrode of the fifth transistor M 5 is coupled to the first power source terminal B_VGH. The second electrode of the fifth transistor M 5 is coupled to the first node N 1 . In addition, the fifth transistor M 5 is turned on when the auxiliary signal SUB is supplied to transmit the first power source VGH to the first node N 1 .

The gate electrode of the sixth transistor M 6 is coupled to the third clock terminal CK 3 . The first electrode of the sixth transistor M 6 is coupled to the first node N 1 . The second electrode of the sixth transistor M 6 is coupled to the second power source terminal B_VGL. In addition, the sixth transistor M 6 is turned on when a clock signal is supplied to the third clock terminal CK 3 to transmit the second power source VGL to the first node N 1 .

The gate electrode of the seventh transistor M 7 is coupled to the auxiliary terminal B_SUB. The first electrode of the seventh transistor M 7 is coupled to the second node N 2 . The second electrode of the seventh transistor M 7 is coupled to the auxiliary terminal B_SUB. In addition, the seventh transistor M 7 is turned on when the auxiliary signal SUB is supplied to transmit the second power source VGL to the second node N 2 .

In addition, the second signal processing unit 320 includes an eighth transistor M 8 and a ninth transistor M 9 .

The gate electrode of the eighth transistor M 8 is coupled to the first node N 1 . The first electrode of the eighth transistor M 8 is coupled to the first power source terminal B_VGH. The second electrode of the eighth transistor M 8 is coupled to the output terminal OUTi. In addition, the turn on and off of the eighth transistor M 1 are controlled by the voltage of the first node N 1 . When the eighth transistor M 1 is turned on, the first power source VGH is transmitted to the output terminal OUTi.

The gate electrode of the ninth transistor M 9 is coupled to the second node N 2 . The first electrode of the ninth transistor M 9 is coupled to the output terminal OUTi. The second electrode of the ninth transistor M 9 is coupled to the second clock terminal CK 2 . In addition, the turn on and off of the ninth transistor M 9 are controlled by the voltage of the second node N 2 . When the ninth transistor M 9 is turned on, the clock signal of the second clock terminal CK 2 is transmitted to the output terminal OUTi.

In addition, the second signal processing unit 320 may further include a first capacitor C 1 and a second capacitor C 2 .

The first capacitor C 1 is coupled between the first node N 1 and the first power source terminal B_VGH. Therefore, the first capacitor C 1 is coupled between the gate electrode of the eighth transistor M 8 and the first electrode of the eighth transistor M 8 .

The second capacitor C 2 is coupled between the second node N 2 and the output terminal OUTi. Therefore, the second capacitor C 2 is coupled between the gate electrode of the ninth transistor M 9 and the first electrode of the ninth transistor M 9 .

The first output signal Sout 1 output from the first signal processing unit 310 is transmitted to the second signal processing unit 320 through the first node N 1 . The second output signal Sout 2 output from the first signal processing unit 310 is transmitted to the second signal processing unit 320 through the second node N 2 .

The first node N 1 is a contact point at which the second electrode of the first transistor M 1 , the gate electrode of the third transistor M 3 , the second electrode of the fifth transistor M 5 , the first electrode of the sixth transistor M 6 , and the gate electrode of the eighth transistor M 8 meet each other.

The second node N 2 is a contact point at which the second electrode of the fourth transistor M 4 , the first electrode of the seventh transistor M 7 , and the gate electrode of the ninth transistor M 9 meet each other.

The third node N 3 is a contact point at which the second electrode of the second transistor M 2 , the second electrode of the third transistor M 3 , and the first electrode of the fourth transistor M 4 meet each other.

The above-described transistors M 1 to M 9 of the first signal processing unit 310 and the second signal processing unit 320 may be realized by PMOS transistors. The first electrode and the second electrode of each of the transistors are set as different electrodes. For example, when the first electrode is a drain electrode, the second electrode may be set as a source electrode.

In addition, the output terminal OUTi of the ith stage 200 i may be electrically coupled to the input terminal IN of the (i+1)th stage 200 i +1.

FIG. 5 is a waveform chart illustrating the operations of the stages of FIG. 3 . Referring to FIGS. 4 and 5 , the operation of the scan driver 130 according to present embodiments will be described.

In each frame period, the simultaneous driving period Pe, the initializing period Pi, and the progressive driving period Ps progressively proceed.

In the simultaneous driving period Pe, the scan driver 130 simultaneously supplies the first scan signals to the pixels 110 . As illustrated in FIG. 5 , the first scan signals are simultaneously output from the output terminals OUT 1 to OUTn of the stages 2001 to 200 n.

In the simultaneous driving period Pe, the supply of clock signals to the first clock terminal CK 1 , the second clock terminal CK 2 , and the third clock terminal CK 3 is maintained. The auxiliary signal SUB is supplied to the auxiliary terminal B_SUB. The second power source VGL supplied to the second power source terminal B_VGL is set as a high level voltage.

For example, as illustrated in FIG. 5 , the clock signals SCK 1 , SCK 2 , and SCK 3 supplied to the clock terminals CK 1 , CK 2 , and CK 3 may be realized by low level voltages. The auxiliary signal SUB may be set to have a voltage for turning on the fifth transistor M 5 and the seventh transistor M 7 and may be realized by a low level voltage.

At this time, the point of time at which the supply of the auxiliary signal SUB starts and the point of time at which the second power source VGL is transited from a low level voltage to a high level voltage may be the same.

In addition, the point of time at which the supply of the auxiliary signal SUB starts and the point of time at which the second power source VGL is transited from a low level voltage to a high level voltage may be before the point of time at which the supply of the clock signals SCK 1 , SCK 2 , and SCK 3 starts. The point of time at which the supply of the auxiliary signal SUB is completed and the point of time at which the second power source VGL is transited from a high level voltage to a low level voltage may be after the point of time at which the supply of the clock signals SCK 1 , SCK 2 , and SCK 3 is completed

The fifth transistor M 5 is turned on by the supply of the auxiliary signal SUB so that the first power source VGH is transmitted to the first node N 1 . Therefore, the third transistor M 3 and the eighth transistor M 8 maintain a turn off state.

In addition, since the second power source VGL is transited to a high level voltage, the fourth transistor M 4 is turned off.

In accordance with the supply of the auxiliary signal SUB, the seventh transistor M 7 is turned on and transmits a voltage value obtained by subtracting the absolute value of the threshold voltage Vth 7 of the seventh transistor M 7 from the voltage of the auxiliary signal SUB to the second node N 2 .

Therefore, the ninth transistor M 9 is turned on and the clock signal of the second clock terminal CK 2 is transmitted to the output terminal OUTi. At this time, since the supply of all of the clock signals SCK 1 , SCK 2 , and SCK 3 is maintained, a low level voltage is output to the output terminal OUTi.

In addition, since the simultaneous driving period Pe simultaneously proceeds in all of the stages 2001 to 200 n , the stages 2001 to 200 n may simultaneously output low level voltages as the first scan signals.

The initializing period Pi is shorter than the progressive driving period Ps or the simultaneous driving period Pe. The clock signals are simultaneously supplied to the first clock terminal CK 1 , the second clock terminal CK 2 , and the third clock terminal CK 3 . In addition, the supply of the auxiliary signal SUB to the auxiliary terminal B_SUB is stopped and the second power source VGL supplied to the second power source terminal B_VGL is set as a low level voltage.

At this time, the clock signals SCK 1 , SCK 2 , and SCK 3 may be supplied in one horizontal period (the supply period of the scan signals, 1 H).

Since the clock signals SCK 1 , SCK 2 , and SCK 3 are simultaneously supplied in the initializing period Pi in a partial period, the sixth transistor M 6 is turned on so that the second power source VGL is transmitted to the first node N 1 .

Since the second power source VGL is a low level voltage in the initializing period Pi, the eighth transistor M 8 is turned on so that the first power source VGH is output to the output terminal OUTi.

In addition, since the initializing period Pi is simultaneously performed in all of the stages 2001 to 200 n and the first power source VGH is a high level voltage, all of the stages 2001 to 200 n output high level voltages to the output terminals OUT 1 to OUTn to initialize the outputs of the stages 2001 to 200 n.

In the progressive driving period Ps, the scan driver 130 progressively supplies the second scan signals to the pixels 110 . As illustrated in FIG. 5 , the second scan signals are progressively output from the output terminals OUT 1 to OUTn of the stages 2001 to 200 n.

Therefore, the clock signals are progressively and repeatedly supplied to the first clock terminal CK 1 , the second clock terminal CK 2 , and the third clock terminal CK 3 of each of the stages 2001 to 200 n . In addition, the supply of the auxiliary signal SUB is stopped to the auxiliary terminal B_SUB and the second power source VGL supplied to the second power source terminal B_VGL is set to have a low level voltage.

For example, as illustrated in FIG. 5 , the clock signals SCK 1 , SCK 2 , and SCK 3 supplied to the clock terminals CK 1 , CK 2 , and CK 3 may be realized by low level voltages. The auxiliary signal SUB may be set as a voltage for turning on the fifth transistor M 5 and the seventh transistor M 7 and may be realized by a low level voltage.

Therefore, in the progressive driving period Ps, a high level voltage may be applied to the auxiliary terminal B_SUB.

The operation of the ith stage 200 i will be described as follows. With the start of the progressive driving period Ps, the second scan signal output from the output terminal OUTi−1 of a previous stage 200 i −1 is input to the input terminal OUTi (in the case of the first stage 2001 , the start pulse FLM is input to the input terminal IN) and a clock signal (for example, the first clock signal SCK 1 ) is input to the first clock terminal CK 1 .

Since the supply of the auxiliary signal SUB is stopped in the progressive driving period Ps, the fifth transistor M 5 and the seventh transistor M 7 maintain turn off states.

In addition, since the second power source VGL maintains a low level voltage, the fourth transistor M 4 maintains a turn on state.

Since the scan signal (for example, a low level voltage) output from the output terminal OUTi−1 of the previous stage 200 i −1 is supplied to the input terminal IN, the first transistor M 1 is turned on. Therefore, the first power source VGH is transmitted to the first node N 1 through the first transistor M 1 . Since the first power source VGH is a high level voltage, the third transistor M 3 and the eighth transistor M 8 are turned off.

Since a low level clock signal is supplied to the first clock terminal CK 1 , the second transistor M 2 is turned on so that the low level voltage of the input terminal IN is transmitted to the second node N 2 through the third node N 3 and the fourth transistor M 4 .

Therefore, the ninth transistor M 9 is turned on so that the voltage of the second clock terminal CK 2 is output to the output terminal OUTi. At this time, since the voltage of the second clock terminal CK 2 is set to be in a high level, the high level voltage is output to the output terminal OUTi.

Then, when a clock signal (for example, the second clock signal SCK 2 ) is supplied to the second clock terminal CK 2 , a low level voltage is output through the ninth transistor M 9 that maintains a turn on state by the voltage charged in the second capacitor C 2 . Therefore, the low level voltage may be output to the output terminal OUTi as the second scan signal.

Then, when a clock signal (for example, the third clock signal SCK 3 ) is supplied to the third clock terminal CK 3 , the sixth transistor M 6 is turned on so that the second power source VGL is transmitted to the first node N 1 . Therefore, the eighth transistor M 8 is turned on so that the first power source VGH is transmitted to the output terminal OUTi. Therefore, as a result, the output terminal OUTi outputs a high level voltage again.

Next, in the (i+1)th stage 200 i +1, the second scan signal output from the output terminal OUTi of the ith stage 200 i is received to the input terminal IN to perform the above-described operation of the ith stage 200 i in the same way so that the second scan signal may be output to the output terminal OUTi+1 thereof.

Such a chain of operations are performed so that the stages 2001 to 200 n progressively output the second scan signals in the progressive driving period Ps.

FIG. 6 is a view illustrating other structures of the stages included in the scan driver of FIG. 2 . FIG. 7 is a waveform chart illustrating the operations of the stages of FIG. 6 .

In the above-described FIG. 5 , the scan signals of one horizontal period 1 H are output in the progressive driving period Ps. However, through the structure illustrated in FIG. 6 , the scan signals (one horizontal period 1 H overlaps between adjacent outputs) of two horizontal periods 2 H may be output.

Therefore, since the clock signals supplied to the stages 2002 to 200 n must be also supplied in the two horizontal periods 2 H, six clock signals SCK 1 , SCK 2 , SCK 3 , SCK 4 , SCK 5 , and SCK 6 are used.

The six clock signals SCK 1 , SCK 2 , SCK 3 , SCK 4 , SCK 5 , and SCK 6 are repeatedly supplied as illustrated in FIG. 8 and are supplied in the two horizontal periods 2 H. The current clock signal is delayed from a previous clock signal by one horizontal period 1 H so that the current clock signal overlaps the previous clock signal in one horizontal period 1 H.

For example, the second clock signal SCK 2 is delayed from the first clock signal SCK by one horizontal period 1 H and the second clock signal SCK 2 and the first clock signal SCK overlap in one horizontal period 1 H.

As a result, in the stages 2002 to 200 n , like in the structures of the stages illustrated in FIG. 3 , in the progressive driving period Ps, the clock signals are progressively supplied to the first clock terminal CK 1 , the second clock terminal CK 2 , and the third clock terminal CK 3 of each of the stages 2001 to 200 n . Thus, the difference between the periods of the supplied clock signals in FIGS. 5 and 6 are that FIG. 6 has two horizontal periods 2 H instead of one horizontal period 1 H.

For example, in the first stage 2001 , the first clock terminal CK 1 may be coupled to the first clock signal SCK 1 , the second clock terminal CK 2 may be coupled to the third clock signal SCK 3 , and the third clock terminal CK 3 may be coupled to the fifth clock signal SCK 5 .

In addition, in the second stage 2002 , the first clock terminal CK 1 may be coupled to the second clock signal SCK 2 , the second clock terminal CK 2 may be coupled to the fourth clock signal SCK 4 , and the third clock terminal CK 3 may be coupled to the sixth clock signal SCK 6 .

Since the operations of the stages 2001 to 200 n are the same as described above (related to FIG. 5 ), description thereof will be omitted.

By way of summation and review, among flat panel displays, an organic light emitting display displays an image using organic light emitting diodes (OLED) that generate light by recombining electrons and holes. The organic light emitting display has high response speed and is driven with low power consumption.

FIG. 1 is a view illustrating an organic light emitting display with respect to which the embodiments described above represent advances in the art. Referring to FIG. 1 , the organic light emitting display includes a pixel unit 20 with pixels 10 coupled to scan lines S 1 to Sn, data lines D 1 to Dm, a first power source ELVDD, and a second power source ELVSS, a scan driver 30 for supplying scan signals to the pixels 10 through the scan lines S 1 to Sn, and a data driver 50 for supplying data signals to the pixels 10 through the data lines D 1 to Dm.

At this time, in one frame period, the scan driver 30 simultaneously supplies first scan signals to the pixels 10 in a simultaneous driving period in order to initialize and compensate for the pixels 10 . The scan driver 30 also progressively supplies second scan signals to the pixels 10 in a progressive driving period that proceeds after the simultaneous driving period in order to write down the data signals.

Therefore, the scan driver 30 includes a simultaneous driving stage 32 for simultaneously supplying the first scan signals to the pixels and a progressive driving stage 34 for progressively supplying the second scan signals to the pixels 10 .

As the simultaneous driving stage 32 and the progressive driving stage 34 are provided, the number of transistors and capacitors that constitute the circuits of the stages 32 and 34 increases. Thus, a circuit structure of the scan driver 30 becomes complicated.

In contrast, embodiments relate to a scan driver in which a structure of a simultaneous driving stage and a structure of a progressive driving stage are integrated so that a structure of the scan driver is simplified and to an organic light emitting display including such advances.

Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation.